JP2001168191A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a mask for forming a hard mask from being removed by patterning an inorganic insulating film deposited on an organic insulating film. SOLUTION: After a first organic insulating film 104 and a first inorganic insulating film are sequentially deposited on lower layer wiring 102 and an insulating film 101 provided on a semiconductor substrate 100 via a protection film 103, a first inorganic insulating film 105 is coated with a photosensitive polyimide film. After a mask pattern 106 is formed by patterning the photosensitive polyimide film, dry etching is performed against the first inorganic insulating film 105 and a first hard mask 105A is formed. After a second organic insulating film 107 and a second inorganic insulating film 108 are sequentially deposited on the mask pattern 106, a second hard mask 108A is formed by patterning the second inorganic insulating film 108. Dry etching is performed using the second hard mask 108A as a mask. Subsequently, a via hole 110 is formed on the first organic insulating film 104 and a wiring groove 111 is formed on the second organic insulating film 107.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a via and a buried wiring formed by a dual damascene method, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, progress in miniaturization and high integration of semiconductor integrated circuit devices has been remarkable. Even new technologies are being developed.

For example, a via hole connected to the lower wiring and a wiring groove for the upper wiring are formed in an interlayer insulating film deposited on the lower wiring, and then a metal film is embedded in the via hole and the wiring groove. Therefore, the dual damascene method of forming vias and upper wirings can reduce the contact resistance between the vias and the upper wirings and reduce the number of steps. It is attracting attention.

[0004] Further, as the degree of integration of a semiconductor integrated circuit device increases, an increase in signal delay time due to an increase in capacitance between wirings, which is a parasitic capacitance between wirings, has become a problem. Therefore, in order to suppress an increase in the capacitance between wirings, it is desired to lower the relative dielectric constant of an interlayer insulating film formed between wirings, and an organic insulating film is used instead of a conventional silicon oxide film as an interlayer insulating film. A method using a film has been proposed.

A method of manufacturing a semiconductor device having an embedded wiring formed by a dual damascene method and having an interlayer insulating film made of an organic film, which is disclosed in, for example, JP-A-11-176935, is described below with reference to FIG. ) ~
This will be described with reference to FIG.

First, as shown in FIG. 4A, a lower wiring 12 is buried in an insulating film 11 deposited on a semiconductor substrate 10 and then over the entire surface of the lower wiring 12 and the insulating film 11. A protective film 13 made of a silicon nitride film is deposited, and then a first inorganic insulating film 14 made of a silicon oxide film is deposited on the protective film 13.

Next, as shown in FIG. 4B, a first resist pattern 15 having an opening for forming a via hole is formed on the first inorganic insulating film 14, and then the first inorganic pattern is formed. The opening 14a is formed in the first inorganic insulating film 14 by performing selective dry etching on the insulating film 14 using the first resist pattern 15 as a mask.

Next, as shown in FIG. 4C, after the first resist pattern 15 is removed, the first inorganic insulating film 1 is removed.
An organic insulating film 16 is deposited on the organic insulating film 16 and then a second inorganic insulating film 1 made of a silicon oxide film is formed on the organic insulating film 16.
7 is deposited.

Next, as shown in FIG. 4D, a second inorganic insulating film 17 having an opening for forming a wiring groove is formed on the second inorganic insulating film 17.
After the resist pattern 18 is formed, the second inorganic insulating film 17 is subjected to selective dry etching using the second resist pattern 18 as a mask to form a hard mask 17A made of the second inorganic insulating film 17. Form.

Next, as shown in FIG. 4E, after removing the second resist pattern 18, the organic insulating film 16 and the first inorganic insulating film 14 are selectively dried using a hard mask 17A. By performing etching, the first
The organic insulating film 16 buried in the opening 14a of the inorganic insulating film 14 is removed to form a via hole 19, and a wiring groove 20 is formed in the organic insulating film 16. Thereafter, although not shown, a metal film is formed in the via hole 19.
After filling the wiring groove 20, the portion of the metal film exposed above the hard mask 17A is removed to obtain a multilayer wiring structure.

In this conventional example, by forming the buried wiring by the dual damascene method, it is possible to reduce the contact resistance between the via and the upper layer wiring, to reduce the number of steps, and to increase the capacitance between wirings. The resulting increase in signal delay time can be suppressed.

[0012]

However, according to the above-described conventional method for manufacturing a semiconductor device, the organic insulating film 1 is formed between upper-layer wirings made of a metal film embedded in the wiring grooves 20.
6, the first inorganic insulating film 1 is provided between the vias made of a metal film embedded in the via holes 19.
4, there is a problem that when the size of the semiconductor integrated circuit device is further reduced, the increase in signal delay time due to the capacitance between wires cannot be sufficiently suppressed.

Therefore, as shown in FIG. 5A, after a lower organic insulating film 21 is deposited on the protective film 13, an opening for forming a via hole is formed on the lower organic insulating film 21. A resist pattern 22 is formed, and then the lower organic insulating film 21 is selectively dry-etched using the resist pattern 22 as a mask, thereby forming an opening (via hole) 21 a in the lower organic insulating film 21. It is possible to do. Incidentally, since the resist material is generally inferior in heat resistance, film strength and adhesion, various problems occur if the resist pattern 22 is not removed. Therefore, the opening 21a is formed in the lower organic insulating film 21. Later, the resist pattern 22 needs to be removed.

However, when the lower organic insulating film 21 is used instead of the first inorganic insulating film 14, the resist pattern 2
When removing 2, the following problem occurs.

First, when the resist pattern 22 is removed by ashing using oxygen plasma, since the lower organic insulating film 21 contains an organic component as a main component similarly to the resist pattern 22, the lower organic insulating film 21 is removed. Is ashed by oxygen plasma. That is, as shown in FIG. 5B, the lower organic insulating film 2 is formed.
1, the diameter of the opening 21a increases, and the damage layer 21b is formed on the side wall of the opening 21a. The dash-dot line in FIG.
3A illustrates the shape of the lower organic insulating film 21 in FIG. Therefore, it is extremely difficult to remove the resist pattern 22 formed on the lower organic insulating film 21 by oxygen plasma.

Further, as shown in FIG. 5C, even if the resist pattern 22 formed on the lower organic insulating film 21 could be removed, as shown in FIG. Since the upper organic insulating film 23 is filled in the opening 21a of the organic insulating film 21, the lower organic insulating film 21 and the upper organic insulating film 23 are integrated, and the lower organic insulating film 21 has a via hole. There is a problem that a step of forming a wiring groove in the upper organic insulating film 23 while forming a hole becomes impossible.

To cope with the problem that the lower organic insulating film 21 and the upper organic insulating film 23 are integrated, the following method is considered. That is, as shown in FIG. 6A, after depositing the silicon oxide film 24 on the lower organic insulating film 21, the first film is formed on the silicon oxide film 24 as shown in FIG. A resist pattern 22 is formed, and thereafter, the silicon oxide film 24 is subjected to selective dry etching using the first resist pattern 22 as a mask to form a first hard mask 24A made of the silicon oxide film 24. Next, after the first resist pattern 22 is removed, the lower organic insulating film 21 is dry-etched using the first hard mask 24A, and an opening (via hole) is formed in the lower organic insulating film 21. ) 21a is considered (see FIG. 5 (c)). Thus, dry etching is performed on the upper organic insulating film 23 using the second hard mask (corresponding to the hard mask 17A in FIG. 4E) having an opening for forming a wiring groove. In the step of forming a wiring groove in the upper organic insulating film 23 by using the first hard mask 24A as an etching stopper,
The upper organic insulating film 23 buried in the opening (via hole) of the lower organic insulating film 21 can be removed.

However, this method also requires a step of removing the first resist pattern 22, so that
The following problems occur.

First, when the first resist pattern 22 is removed by ashing using oxygen plasma,
The problem that a damage layer is formed on the side wall of the via hole in the lower organic insulating film 21 occurs. That is, a step of removing the first resist pattern 22 by ashing using oxygen plasma (see FIG. 6B).
In FIG. 6C, as shown in FIG. 6C, a damaged layer 21c is formed in a portion of the lower organic insulating film 21 that is exposed to the opening of the first hard mask 24A. next,
As shown in FIG. 6D, after an upper organic insulating film 23 is deposited on the first hard mask 24A, a second inorganic insulating film made of a silicon oxide film is formed on the upper organic insulating film 23. A film 25 is deposited, and then, as shown in FIG.
Selective dry etching is performed on the second inorganic insulating film 25 using the second resist pattern 26 having an opening for forming a wiring groove as a mask to form a second hard mask 25A.
To form Next, as shown in FIG. 7B, after removing the second resist pattern 26, the upper organic insulating film 2 is removed.
3 and the lower organic insulating film 21 are selectively dry-etched using the second hard mask 25A as a mask, whereby the upper organic insulating film 23 embedded in the opening of the lower organic insulating film 21 is formed. Is removed to form a via hole 27 and a wiring groove 28 is formed in the upper organic insulating film 23.

However, as shown in FIG. 7B, the damage layer 21c is exposed on the side wall of the via hole 27 in the lower organic insulating film 21.
7 and a problem that the adhesion between the metal film embedded in the wiring groove 28 and the underlying organic insulating film 21 is reduced.

When the first resist pattern 22 is removed by wet etching using a resist stripping agent made of, for example, a diamine, the resist stripping agent damages the underlying organic insulating film 21. In addition, there arises a problem that the adhesion between the metal film buried in the via hole 27 and the wiring groove 28 and the underlying organic insulating film 21 is reduced.

When the first resist pattern 22 is removed by, for example, anisotropic etching using a forming gas or the like, an opening is formed in the lower organic insulating film 21. No damage layer is formed, and the opening of the lower organic insulating film 21 is backfilled with the upper organic insulating film 23, so that the above-described problem does not occur.

However, the first hard mask 22 is formed twice in the step of removing the first resist pattern 22 and the step of forming the via hole 27 and the wiring groove 28 shown in FIG. It is exposed to an etching gas. For this reason, the periphery of the opening in the first hard mask 22 is violently sputtered, so that a barrier 29 called a crown is formed inside the via hole 27 as shown in FIG. 7C. And the size of the opening of the first hard mask 24A is enlarged, and the diameter of the via hole 27 becomes larger than a predetermined size.

In view of the above, according to the present invention, it is not necessary to remove a mask pattern for forming a hard mask by selectively etching an inorganic insulating film deposited on an upper organic insulating film. The purpose is to be.

[0025]

In order to achieve the above object, in a method of manufacturing a semiconductor device according to the present invention, a first organic insulating film is deposited so as to cover a lower wiring formed on a semiconductor substrate. And a step of depositing a first inorganic insulating film on the first organic insulating film; and a mask pattern made of a photosensitive organic film and having an opening for forming a via hole on the first inorganic insulating film. Forming a first hard mask made of the first inorganic insulating film by selectively etching the first inorganic insulating film using the mask pattern as a mask; Depositing a second organic insulating film on the substrate, depositing a second inorganic insulating film on the second organic insulating film, and patterning the second inorganic insulating film to form a second inorganic insulating film. Made of insulating film and opened for forming wiring grooves Forming a second hard mask having a portion, and selectively etching the second organic insulating film and the mask pattern using the second hard mask as a mask to form a second organic insulating film and a mask pattern Forming a wiring groove in the first organic insulating film, and selectively etching the first organic insulating film using the first hard mask as a mask to form a via hole in the first organic insulating film. .

A semiconductor device according to the present invention is provided on a lower wiring layer formed on a semiconductor substrate and has a lower first hard mask composed of a lower first organic insulating film and a lower inorganic insulating film. Having a via hole made of a laminate of
And a lower mask pattern made of a photosensitive organic film and a second interlayer insulating film provided on the first interlayer insulating film.
A second interlayer insulating film made of a laminate of an organic insulating film and an upper second hard mask made of a second inorganic insulating film and having a wiring groove; a metal film embedded in the via hole and the wiring groove; It has.

According to the semiconductor device and the method for manufacturing the same of the present invention, the first organic insulating film is used for the first interlayer insulating film, and the second organic insulating film is used for the second interlayer insulating film. An organic insulating film having a low relative dielectric constant is interposed between metal films (vias) embedded in via holes and between metal films (upper wirings) embedded in wiring trenches. Therefore, the inter-wiring capacitance is greatly reduced, so that even if miniaturization and high integration of the semiconductor device progress, an increase in signal delay time accompanying an increase in the inter-wiring capacitance can be suppressed.

The mask pattern provided between the first hard mask made of the first inorganic insulating film and the second organic insulating film is made of a photosensitive organic film. Is excellent in adhesiveness, so that even if not removed, it does not adversely affect the characteristics of the semiconductor device. In addition, since the mask pattern is made of a photosensitive organic film and has a lower relative dielectric constant than that of the inorganic insulating film, the inter-wiring capacitance of the metal film (upper wiring) embedded in the wiring groove does not increase. Increase can be suppressed. further,
Since the mask pattern does not have to be removed, the first organic insulating film is not damaged when the mask pattern is removed, so that the reliability of the first organic insulating film is improved.

In the semiconductor device and the method of manufacturing the same according to the present invention, the photosensitive organic film has a glass transition temperature of 300 ° C.
It is preferable that the film is made of the above-described precursor of the photosensitive material and is cured by heating to form a polymer film.

When such a photosensitive organic film is used, the step of patterning the photosensitive organic film to form a mask pattern becomes easy, and the shape of the mask pattern becomes unstable in a heat treatment step performed later. In addition, in the heat treatment step for depositing the second organic insulating film, the mask pattern is firmly adhered to the second organic insulating film.

In the semiconductor device and the method of manufacturing the same according to the present invention, the photosensitive organic film is preferably a photosensitive polyimide film or a photosensitive polybenzoxazole film.

When such a photosensitive organic film is used, the process of forming a mask pattern is facilitated, the shape of the mask pattern can be prevented from becoming unstable, and the mask pattern is firmly adhered to the second organic insulating film. I do.

In the semiconductor device and the method of manufacturing the same according to the present invention, it is preferable that the thickness of the mask pattern is not more than half the thickness of the second organic insulating film.

In this manner, the relative thickness of the photosensitive organic film having a higher relative dielectric constant than that of the second organic insulating film can be reduced. It is possible to suppress an increase in the relative dielectric constant between them.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to one embodiment of the present invention will be described below with reference to FIG.

As shown in FIG. 1, an insulating film 101 made of, for example, a silicon oxide film is deposited on a semiconductor substrate 100, and a lower wiring 102 made of, for example, copper is embedded in the insulating film 101. . A protective film 1 made of, for example, a Si ₃ N ₄ film on the lower wiring 102 and the insulating film 101.
03 is deposited, and the protective film 103 is
When a via hole and a wiring groove are formed by dry etching in an interlayer insulating film deposited on
02 is protected.

On the protective film 103, a first organic insulating film 104 having a low relative dielectric constant and a first inorganic insulating film 105 made of, for example, a silicon oxide film (see FIG. 2A) are patterned. And a first hard mask 105A formed in this order.
3. First organic insulating film 104 and first hard mask 1
05A constitutes a first interlayer insulating film. As a material of the first organic insulating film 104, for example, polyallyl ether (trade name: FLARE (manufactured by Allied Signal), relative permittivity: 2.7) or the like can be used.

A mask pattern 106 formed by patterning a photosensitive polyimide film made of, for example, a polyimide precursor is formed on the first inorganic insulating film 105 constituting the first interlayer insulating film, Low rate second
Organic insulating film 107 and a second hard mask 108A formed by patterning a second inorganic insulating film 108 (see FIG. 3A) made of, for example, a silicon oxide film. Thus, a second interlayer insulating film is constituted by the mask pattern 106, the second organic insulating film 107, and the second hard mask 108A. As a material of the second organic insulating film 107, for example, polyallyl ether or the like can be used.

Via holes 110 are formed in the first interlayer insulating film.
Is formed, and a wiring groove 111 is formed in the second interlayer insulating film (see FIG. 3C). For example, a copper film is formed in the via hole 110 and the wiring groove 111 by a dual damascene method. Buried, via hole 1
Vias 112 are formed by the copper film embedded in the wiring 10, and upper layer wirings 113 are formed by the copper film embedded in the wiring grooves 111.

Hereinafter, a method for manufacturing the above-described semiconductor device will be described with reference to FIGS. 2 (a) to 2 (c) and 3 (a) to 3 (c).

First, as shown in FIG. 2A, a lower wiring 102 made of, for example, copper is embedded in an insulating film 101 made of, for example, a silicon oxide film deposited on a semiconductor substrate 100, and then, for example, a CVD method A protective film 10 made of, for example, a Si ₃ N ₄ film on the lower wiring 102 and the insulating film 101 to protect the lower wiring 102 during dry etching.
3 is deposited.

Next, the protective film 1 is formed by, for example, a spin coating method.
After the first organic insulating film 104 having a low relative dielectric constant is deposited on the first organic insulating film 104, the first organic insulating film 1 is formed by, for example, a CVD method.
On the substrate 04, a first inorganic insulating film 105 made of, for example, a silicon oxide film is deposited. As a material of the first organic insulating film 104, for example, polyallyl ether or the like can be used.

Next, a photosensitive organic film, for example, a photosensitive polyimide film made of a polyimide precursor is applied over the entire surface of the first inorganic insulating film 105, and a known polyimide film is applied to the photosensitive polyimide film. By performing the lithography method, FIG.
As shown in (b), a mask pattern 106 made of a photosensitive polyimide film and having an opening for forming a via hole is formed.

Next, with respect to the first inorganic insulating film 105,
By performing selective dry etching using the mask pattern 106 as a mask, as shown in FIG. 2C, a first hard mask 105A made of the first inorganic insulating film 105 and having an opening for forming a via hole is formed. I do. In this case, since the mask pattern 106 is made of a photosensitive organic film, for example, a photosensitive polyimide film, etching selectivity between the mask pattern 106 and the first inorganic insulating film 105 is ensured.

Next, as shown in FIG. 3A, a second organic insulating film 1 having a low relative dielectric constant is formed on the mask pattern 106.
After depositing 07, a second inorganic insulating film 108 made of, for example, a silicon oxide film is deposited on the second organic insulating film 107. As a material of the second organic insulating film 107, for example, polyallyl ether or the like can be used as in the case of the first organic insulating film 104. In this case, since the mask pattern 106 is made of a photosensitive polyimide film which is a thermosetting polymer resin, the mask pattern 106 is used as the second organic insulating film 107 in the thermosetting step when depositing the second organic insulating film 107. And firmly adhere.

Next, as shown in FIG. 3B, after forming a resist pattern 109 having an opening for forming a wiring groove on the second inorganic insulating film 108, the second inorganic insulating film 108 is formed. Is selectively etched using the resist pattern 109 as a mask to form a second hard mask 108A made of the second inorganic insulating film 108 and having an opening for forming a wiring groove.

Next, selective dry etching is performed on the second organic insulating film 107 and the mask pattern 106 using the second hard mask 108A as a mask.
First hard mask 1 for first organic insulating film 104
By performing selective dry etching using the mask 05A as a mask, the first organic insulating film 104 is formed as shown in FIG.
A via hole 110 is formed, and a wiring groove 111 is formed in the second organic insulating film 107 and the mask pattern 106. The etching conditions in this case are described in, for example,
Known conditions such as those described in Japanese Patent Application Laid-Open No. 1-67909 may be used. For example, in a chamber of an ECR etching apparatus (the pressure is maintained at 0.93 Pa, for example), a nitrogen gas and a volume flow ratio The mixture gas obtained by mixing 5% hydrogen gas is introduced at a standard flow rate of 2000 (mL / min) as a volume flow per minute, and a microwave is introduced at a power of 1200 W. Since the resist pattern 109 is removed in this etching step, it is not necessary to remove the resist pattern 109 in advance.

Next, the lower wiring 102 is exposed to the via hole 110 by performing selective dry etching on the protective film 103 using the first hard mask 105A as a mask. For example, a copper film is buried, and then a portion of the copper film exposed on the second hard mask 108A is subjected to, for example, CMP.
When removed by the method, as shown in FIG. 1, a semiconductor device having a via 112 made of a copper film and an upper wiring 113 is obtained.

According to the present embodiment, as described above, since the mask pattern 106 is made of a photosensitive polyimide film and is a thermosetting polymer resin film, the second organic insulating film 107 is formed.
Mask pattern 10 in a thermosetting process when depositing
6 strongly adheres to the second organic insulating film 107, so that it is not necessary to remove the mask pattern. That is, the mask pattern 106 does not need to be removed like the first resist pattern 22 shown in FIG. Therefore, the number of steps can be reduced and the mask pattern 106
When the first organic insulating film 105 is removed, there is no possibility that the first organic insulating film 105 is damaged, so that the reliability of the first organic insulating film 105 is improved.

The mask pattern 106 is made of a photosensitive polyimide film and has a relative dielectric constant of about 3.3, which is lower than the relative dielectric constant (about 4.0) of the inorganic insulating film. Since the inter-wire capacitance does not increase,
An increase in signal delay time in the upper layer wiring 113 can be suppressed.

In the present embodiment, the mask pattern 106 is formed of a photosensitive polyimide film. Alternatively, the mask pattern 106 may be formed of a photosensitive polybenzoxazole film. The photosensitive polybenzoxazole film has a low dielectric constant, heat resistance, and adhesion similar to those of the photosensitive polyimide film.

As the photosensitive organic film constituting the mask pattern 106, another photosensitive organic film may be used instead of the photosensitive polyimide film or the photosensitive polybenzoxazole film. The photosensitive organic film to be formed is preferably made of a precursor of a photosensitive material having a glass transition temperature of 300 ° C. or higher, and is cured by heating to form a polymer film. When a photosensitive organic film having such heat resistance is used, it is easy to pattern the photosensitive organic film to form the mask pattern 106, and the shape of the mask pattern 106 becomes unstable in a heat treatment step performed later. In this case, the mask pattern 106 can be firmly adhered to the second organic insulating film 107 in a heat treatment step for depositing the second organic insulating film 107.

The thickness of the photosensitive organic film for forming the mask pattern 106 is preferably not more than の of the thickness of the second organic insulating film 107. The reason is,
The relative permittivity of the photosensitive organic film, for example, the polyimide film and the photosensitive polybenzoxazole film is about 3.3, which is larger than the relative permittivity of the second organic insulating film 107. This is because if the value is large, the relative dielectric constant between the upper layer wirings 113 cannot be significantly reduced.

[0054]

According to the semiconductor device and the method of manufacturing the same according to the present invention, the metal films (vias) buried in the via holes and the metal films (upper wiring) buried in the wiring grooves are provided.
Since the inter-wiring capacitance between the wirings can be greatly reduced, even if the miniaturization and high integration of the semiconductor device further progress, the increase in the signal delay time due to the increase in the inter-wiring capacitance can be suppressed.

Further, since the mask pattern made of the photosensitive organic film has excellent adhesion to the second organic insulating film,
Even if it is not removed, the characteristics of the semiconductor device are not adversely affected, and since the dielectric constant is low, an increase in inter-wiring capacitance of the metal film (upper wiring) embedded in the wiring groove can be suppressed. The first organic insulating film is not likely to be damaged when the mask pattern is removed because the first organic insulating film need not be removed.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIGS. 2A to 2C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIGS. 3A to 3C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIGS. 4A to 4E are cross-sectional views showing steps of a conventional method for manufacturing a semiconductor device.

5A is a cross-sectional view illustrating a method of manufacturing a semiconductor device as a premise of the present invention, and FIG. 5B is a cross-sectional view illustrating a first problem of the method of manufacturing a semiconductor device illustrated in FIG. FIGS. 4C and 4D are cross-sectional views illustrating a second problem of the method of manufacturing the semiconductor device shown in FIG.

FIGS. 6A and 6B are cross-sectional views showing a method for manufacturing a semiconductor device for avoiding the second problem.
(C) and (d) are cross-sectional views explaining problems of the method of manufacturing the semiconductor device shown in (a) and (b).

FIGS. 7A to 7C are cross-sectional views illustrating problems in the method of manufacturing the semiconductor device shown in FIGS. 6A and 6B.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 semiconductor substrate 101 insulating film 102 lower wiring 103 protective film 104 organic insulating film 105 first inorganic insulating film 105A first hard mask 106 mask pattern 107 second organic insulating film 108 second inorganic insulating film 108A second Hard mask 109 Resist pattern 110 Via hole 111 Wiring groove 112 Via 113 Upper layer wiring

Claims (7)

[Claims] A step of depositing a first organic insulating film so as to cover a lower wiring formed on a semiconductor substrate; and a step of depositing a first inorganic insulating film on the first organic insulating film. Forming a mask pattern made of a photosensitive organic film and having an opening for forming a via hole on the first inorganic insulating film; and masking the mask pattern on the first inorganic insulating film. Forming a first hard mask made of the first inorganic insulating film by performing selective etching as follows: depositing a second organic insulating film on the mask pattern; Depositing a second inorganic insulating film on the organic insulating film, and patterning the second inorganic insulating film,
Forming a second hard mask made of the second inorganic insulating film and having an opening for forming a wiring groove; and masking the second hard mask with respect to the second organic insulating film and the mask pattern To form a wiring groove in the second organic insulating film and the mask pattern, and to selectively etch the first organic insulating film using the first hard mask as a mask. Forming a via hole in the first organic insulating film. 2. The photosensitive organic film comprises a precursor of a photosensitive material having a glass transition temperature of 300 ° C. or higher, and is cured by heating to form a polymer film. 2. The method for manufacturing a semiconductor device according to item 1. 3. The method according to claim 1, wherein the photosensitive organic film is a photosensitive polyimide film or a photosensitive polybenzoxazole film. 4. A laminated structure of a lower first hard mask provided on a lower wiring formed on a semiconductor substrate and formed of a lower first organic insulating film and a first inorganic insulating film. A first interlayer insulating film having a via hole, a lower mask pattern provided on the first interlayer insulating film and made of a photosensitive organic film, an intermediate second organic insulating film, and a second inorganic insulating film; A second interlayer insulating film having a wiring groove formed of a laminate of an upper layer of a film and a second hard mask, and a metal film embedded in the via hole and the wiring groove. Semiconductor device. 5. The photosensitive organic film is made of a precursor of a photosensitive material having a glass transition temperature of 300 ° C. or more, and is cured by heating to form a polymer film. 5. The semiconductor device according to 4. 6. The semiconductor device according to claim 4, wherein said photosensitive organic film is a photosensitive polyimide film or a photosensitive polybenzoxazole film. 7. The semiconductor device according to claim 4, wherein the thickness of the mask pattern is not more than half the thickness of the second organic insulating film.