JP2001166847A - Computer system and method for controlling clock - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a computer system capable of saving the power consumption by suitably controlling the supply/interruption of a clock to a bridge device in accordance with the connection/disconnection of an extended unit. SOLUTION: The computer system is provided with the extended unit 200 connected so as to be optionally separated from a system body 100 in order to extend a function, and when the unit 200 is not connected to the computer body 100, the body 100 can be driven by power supplied from any of a built-in buttery and an AC power supply, and when the unit 200 is connected, both of the body 100 and unit 200 are driven by power taken in by the unit 200 from the AC power supply. When the disconnection of the unit 200 is detected, the supply of an operation clock to a P-PCI bridge 300a in a PCI-PCICI bridge 300 for mutually connecting the body 100 and the unit 200 is shut off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system having an expansion unit detachably connected to a system main body via a serial transmission line, and a clock control method of the system. Supply of clock to bridge device according to
The present invention relates to a computer system that appropriately controls cutoff to reduce power consumption and a clock control method for the system.

[0002]

2. Description of the Related Art In recent years, various personal computers, such as notebook computers, which are easy to carry and can be operated by a battery, have been developed. Some of these types of personal computers are configured so that they can be attached to an expansion unit as needed to expand their functions. In order for the resources of the expansion unit to be effectively used from the computer main unit, it is necessary to connect a bus in the computer main unit to a bus in the expansion unit. With this bus connection, devices on the bus in the expansion unit can be handled in the same way as devices in the computer main body.

In recent personal computers, PCs
I (Peripheral Component In)
A terconnect bus is often used. Therefore, the bus connection between the computer main body and the expansion unit is performed by providing docking connectors having a number of pins corresponding to the number of signal lines of the PCI bus on the computer main body side and the expansion unit side, respectively. This is usually done by physically connecting both PCI buses via a connector.

FIG. 11 is a diagram for explaining a state of bus connection between a computer main unit and an expansion unit in a conventional computer system.

As shown in FIG. 11, in the conventional computer system, the PCI bus (primary) 2 is electrically led out of the docking connector on the computer main body 100 only when the expansion unit 200 is mounted. Switch 15 is provided, and the PCI bus (primary) 2 and the PCI
PC for bidirectional connection to bus (secondary) 3
By providing the I-PCI bridge 16, a device on the PCI bus (primary) 2 accesses a device on the PCI bus (secondary) 3, and
A device on the CI bus (secondary) 3 can access a device on the PCI bus (primary) 2.

However, in such a configuration, since a large area is required for mounting the docking connector, miniaturization and thinning of the computer main body are hindered. Since the connector mounting position must be matched, the physical housing structure has been restricted.

For these reasons, recently, a bridge device (PCI-PCI bridge) for connecting between two PCI buses in order to connect a computer main body and an extension unit with a cable having a small number of signal lines. Is divided into two physically different controllers connected to two PCI buses, respectively, and the two controllers are connected by a serial transmission line. It is recommended that this bridge device be constructed so as to be recognized as a single controller from other devices including the CPU from the viewpoint of preventing waste of system resources and preventing complicated resource management. . That is, a logically single controller is physically divided into two controllers.

By the way, in this type of computer system, when the system main unit and the extension unit are connected, the computer system is operated by the power from the AC power taken in by the extension unit. Therefore, unlike the related art, when a physically single PCI-PCI bridge is mounted on the expansion unit, there is no need to perform design in consideration of battery consumption. On the other hand, when a logically single controller is physically divided into two controllers, and these two controllers are mounted on the system body and the expansion unit, when the expansion unit is not connected,
The controller on the system itself doesn't make any sense. Therefore, as in the related art, there is a problem in that finite battery power is unnecessarily consumed unless design is performed in consideration of battery consumption.

[0009]

As described above, in a logically single bridge device divided into two physically different controllers, the controller on the system body side has no meaning when the extension unit is not connected. There is a problem that the device becomes a device and, as it is, wastes a limited amount of battery power.

The present invention has been made in consideration of such circumstances, and a computer system that appropriately controls supply / cutoff of a clock to a bridge device in accordance with presence / absence of an extension unit to reduce power consumption. And a clock control method for the same system.

[0011]

SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, the present invention provides a computer system having an expansion unit detachably connected to a system main unit via a serial transmission line. Two buses on the system main unit side and the extension unit side each configured by a parallel transmission line of a plurality of bits each laid in the expansion unit, and arranged on the system main unit and the expansion unit, respectively; Two physically different system units and expansion units that transmit transactions to each other via the serial transmission line so that devices on one bus of the other bus can access devices on the other bus. A bridge device having a controller, the system comprising: Connection detection means for detecting the presence or absence of connection of the extension unit to the body, and supply of an operation clock to a controller on the system body side when the connection detection means detects that the extension unit is not connected. And clock control means for shutting off the clock.

In the computer system according to the present invention, since the clock supply of the controller in the bridge device is controlled by recognizing the presence or absence of the connection of the extension unit, wasteful power consumption can be reduced.

Further, the computer system according to the present invention is characterized in that the connection detecting means has means for reading data in a nonvolatile semiconductor memory built in the extension unit.

When a plurality of types of extension units can be connected, in order to recognize the type of the extension unit, data in a nonvolatile semiconductor memory built in the extension unit is often read. Therefore, in the computer system of the present invention, the increase in cost for connection detection is suppressed by using the mechanism.

Further, the computer system according to the present invention is characterized in that the connection detecting means has means for identifying a potential of a conductor forced to a predetermined potential by connection of the extension unit.

When a single type of extension unit is connected,
In many cases, the above-described nonvolatile semiconductor memory is not built in the extension unit. In this case, the computer system according to the present invention makes it possible to reduce the cost increase due to the addition of hardware for connection detection.

Further, the computer system according to the present invention is characterized in that the connection detecting means has means for identifying a state of a switch operated by connection of the extension unit.

When a single type of extension unit is connected,
In many cases, the above-described nonvolatile semiconductor memory is not built in the extension unit. In this case, the computer system according to the present invention makes it possible to minimize the cost increase due to the addition of hardware for connection detection.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a computer system according to one embodiment of the present invention.

The computer system is a personal computer of a notebook type or the like, and includes a computer main body 100 and an extension unit 20 for function expansion which can be used by connecting a cable to the computer main body 100.
0. When the computer main body 100 is not connected to the extension unit 200, the computer main body 100 can operate with power from any of the built-in battery and the AC power supply. Both of them operate on power from an AC power supply that is taken in by the extension unit 200.

In addition, this computer system logically replaces a single controller physically with two controllers (P-PCI bridge 30) in order to connect a cable between the computer main body 100 and the expansion unit 200.
0a, PCI divided into S-PCI bridges 300b)
A PCI bridge 300 is provided. The two controllers (P-PCI bridge 300a and S-PCI bridge 300b) are connected by a bus having a protocol different from that of the PCI bus, and appear as one PCI bridge device in software. The present invention detects whether or not the extension unit 200 is connected, and when the extension unit 200 is not connected, the P-
It is characterized in that the supply of the clock to the PCI bridge 300a is cut off to prevent power from being wasted.

In the computer main body 100, a processor bus 1 and a PCI bus (primary) 2 are laid, and a CPU 11, a host-PCI bridge 12, a main memory 13, various PCI devices 14, and a PCI-P
The P-PCI bridge 300a of the CI bridge 300 is mounted.

The CPU 11 controls the operation of the entire computer system.
Operating system or system B loaded on
Executes various application programs including the IOS or utilities. The host-PCI bridge 12 is a bridge device that bidirectionally connects the processor bus 1 and the PCI bus (primary) 2, and has a built-in memory control logic for controlling access to the main memory 13. The host-PCI bridge 12 is connected to a PCI bus (primary) 2.
Can function as the upper bus master. The main memory 13 stores an operating system and a system BIO.
S, or various application programs including utilities, various user data, and the like.

The P-PCI bridge 300a is provided with an S-PCI bridge 300b provided in the extension unit 200.
And a logically single PCI-PCI bridge 30
0. The PCI-PCI bridge 300 is used to bidirectionally connect a PCI bus (primary) 2 in the computer main body 100 and a PCI bus (secondary) 3 in the expansion unit 200, and provides a PCI bus (primary). PCI device 1 on 2)
4 is a PCI device 1 on a PCI bus (secondary) 3
7 and the PCI device 17 on the PCI bus (secondary) 3 can access the PCI device 14 on the PCI bus (primary) 2. In this embodiment, a PC connecting the PCI bus (primary) 2 and the PCI bus (secondary) 3
The I-PCI bridge 300 is connected to two physically different controllers (P-PCI bridge 300a, S-PCI
The bridge is divided into bridges 300b), and a serial transmission line is connected between the bridges to realize a PCI serial interface.

Next, the internal configuration of the P-PCI bridge 300a and the S-PCI bridge 300b will be described with reference to FIG. Since the configurations of the P-PCI bridge 300a and the S-PCI bridge 300b are basically the same, the P-PCI bridge 300a will be described here as an example.

(Explanation of Block) P-PCI Bridge 3
00a is a clock (CLK) stop circuit 31, a PCI bus control block (PCI_CT
L) 32, a transaction buffer & control block (TBC) 33, a block & word buffer block (BWB) 34, a block transfer buffer block (BLB) 35, and a configuration register block (CF_REG) 36.

The clock (CLK) stop circuit 31 is connected to the P-PCI bridge 300 when the extension unit 200 is not connected.
The control for cutting off the clock supply in a is performed.

A PCI bus control block (PCI
The _CTL) 32 is a block for controlling a PCI bus interface as a PCI bus master and a target, and includes a master latency timer.

The transaction buffer & control block (TBC) 33 manages a PCI bus cycle as a transaction, and generates a TB_DIN signal to be described later.

Block & word buffer block (BW
B) 34 is a block for bridging between the transaction buffer & control block (TBC) 33 and the block transfer buffer block (BLB) 35, and is mainly constituted by a buffer.

Block transfer buffer block (BLB)
35 is a block & word buffer block (BWB)
This block controls data transfer to / from, and parallel / serial and serial / parallel conversion of data.

The configuration register block (CF_REG) 36 is a so-called PCI configuration register for storing environment setting information for defining the operating environment of the PCI device.

(Explanation of Signals) a1 is FRST #, which is a reset of the bridge device. a2 is PR
SEL, which is a signal for the bridge device to identify whether the connection is primary connection or secondary connection, and is a signal for primary connection (P-PCI bridge 300
In the case of (a), it becomes '1' and the secondary connection (S_PC)
In the case of the I-bridge 300b), it is '0'. a3 is
DOCK #, which is “0” when the computer main body 100 and the docking station 200 are connected, and “1” when the computer is not connected. a4 is CLKEN, which is used as enable control of the clock (CLK) stop control circuit 31. Here, the product with PRSEL (AND)
And enable control. a5 is PCLK
And the clock of the bridge device. a6 is
PCLK_CTS, which is a signal used as CLK of the internal block. a7 is TB_DIN,
It is output from the TBC block and becomes "1" when the operation of the bridge device is not completed, that is, when there is an operation request and data in the buffer of the TBC block. a8 is PIDLE, which becomes '1' when the PCI bus is idle.

FIG. 3 shows a clock (CLK) stop circuit 31.
2 shows the internal configuration of FIG. PRSEL of external input signal = '1'
When CLKEN # = '0', the clock stop enable (CKSTPEN = '1') is set. It is not connected (DOCK # = “1”), and PIDLE (when both FRAMEZ and IRDYZ are “1”) = “1” and TB_DIN (TBC
No request and no data in the buffer inside) = '0'
At this time, CLK is stopped. The state of these signals is controlled by a state machine (FIG. 4), and CKSP is output.

Then, a signal obtained by multiplying the product (AND) of CKSP and CKSTPEN is a clock stop request signal, and the sum (OR) of this signal and PCLK is taken to stop the clock. Also, the clock can be stopped when FRST # = '0'.

Next, the operation principle of the state machine will be described with reference to FIGS. Here, the state machine generates a clock stop signal in accordance with the state transition shown in FIG. 4, and the condition for transition to the next state is such that the higher the priority, the higher the position on each column in FIG. And

(Description of Operation of State Machine) After reset, the state makes a RUN transition. And CKSTP
EN = '1' (CLK stop enable signal) and
When DOCK2TZ = “1” (a signal obtained by pulling out a DOCK # that becomes “1” when disconnected when it is disconnected twice) by FF, the state transitions to UNDOC in the next state.

In the UNDOC state, it is confirmed by TB_DIN output from the TBC block that the internal state of the device is in a state where there is no problem even if CLK is stopped. That is, if TB_DIN = '0' and P
When IDLE = '1', transition to the next state WAIT is made.

In the case of WAIT, TB_DIN and D
Unless there is a change in OCK2TZ, a wait of about 10 CLK is made. And after 10 CLK wait, the state is
The state transits to the next state STP. This STP state indicates that CLK is stopped.

(Explanation of Output Signal Generation) (1) Generation of CKSP When the state state of the state machine in FIG. 4 becomes the STP state, CKSP is set to “1”.

(Description example) CKSP = “1” when (CLK_NOW = STP) else “0”; (2) Generation of CKSPEN The product (AND) of CKSP and CKSTPEN generated in (1) is taken, and the clock is stopped. CKS which is a request signal
Make PEN.

(Description example) CKSPEN = CKSPEN and CKSTP
EN; As described above, the clock (CLK) stop circuit 31 controls the supply / interruption of the clock to the bridge device according to the presence or absence of the connection of the extension unit 200.

Next, detection of the presence or absence of connection of the extension unit 200 will be described.

(1) Detection by EC and EP-ROM As shown in FIG. 6, when the computer main body 100 and the docking station 200 in the figure are connected by a docking I / F (cable) or a dedicated connector, the system When the EP-ROM of the docking station 200 is read via the EC 41 of the computer main body 100 and it is determined that the docking station 200 is connected, the EC 41 sets DOCK # to “0”, Then, the EC 41 sets DOCK # to “1”. The EC 41 is a microcomputer that controls detection, activation, and stop of a hardware device, and is a device that transmits information to an OS, a BIOS, and the like.

(2) Detection by Docking Connect Unit (Part 1) In this case, the detection of the connection of the docking station 200 is performed as follows. The DOCK # signal is pulled up on the computer main body 100 side. for that reason,
When not connected to the docking station 200,
“1” is output. When the docking station 200 is connected to the docking station 200 by a docking cable or a dedicated connector,
DOCK # is set to “0” by GND on the 0 side.

The above-mentioned (1) EC and EP-RO
M, and (2) detection by the docking connect unit (part 1), the computer main body 100 and the docking station 200 are connected to the docking I / F.
(Cable) or a dedicated connector is exemplified, but the present invention is not limited to this. As shown in FIGS. 8 and 9, the computer main body 100 and the docking station 200 are directly connected by the docking connectors. It is useful even in this case.

(3) Detection by Docking Connect Unit (No. 2) As shown in FIG. 10, when the computer main body 100 and the docking station 200 shown in FIG.
0 is provided on the computer main body 10.
0 switch 43 is turned on, and DOCK # is set to “0”.
To On the other hand, when the connection is not established, the switch 43 of the computer main body 100 is turned off, and DOCK # is set to “1”.

As described above, by detecting the connection / non-connection of the extension unit 200, the clock (CLK) stop circuit 31 controls the supply / cutoff of the clock to the bridge device according to the connection / non-connection of the extension unit 200. enable.

[0049]

As described in detail above, according to the computer system of the present invention, the presence or absence of the connection of the extension unit is recognized and the clock supply of the controller in the bridge device is controlled, so that unnecessary power consumption is reduced. It becomes possible.

Also, when a plurality of types of extension units can be connected, it is noted that in order to recognize the type of the extension unit, data in the nonvolatile semiconductor memory built in the extension unit is often read. By using this mechanism, it is possible to suppress an increase in cost for connection detection.

Also, a single type of extension unit is connected,
Even in the case where the nonvolatile semiconductor memory as described above is not built in the extension unit, it is possible to reduce the cost increase due to the addition of hardware for connection detection.

[Brief description of the drawings]

FIG. 1 is an exemplary view showing the configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is an exemplary view showing the internal configuration of two controllers constituting the PCI-PCI bridge of the embodiment.

FIG. 3 is an exemplary view showing the internal configuration of a clock (CLK) stop circuit according to the embodiment;

FIG. 4 is an exemplary view showing state transition in the computer system of the embodiment.

FIG. 5 is an exemplary view showing the priority of a condition for transition to the next state in the computer system of the embodiment.

FIG. 6 is an exemplary view for explaining detection of the presence / absence of connection of the docking station 200 by the EC and the EP-ROM according to the embodiment (when connected by a cable or a connector);

FIG. 7 is an exemplary view for explaining the connection presence / absence detection of the docking station 200 by the docking connection unit of the embodiment (part 1) (at the time of connection by a cable or a connector);

FIG. 8 is a view for explaining detection of the presence or absence of connection of the docking station 200 by the EC and EP-ROM of the embodiment (when directly connected by a docking connector).

FIG. 9 is an exemplary view for explaining the connection presence / absence detection (No. 1) of the docking station 200 by the docking connection unit of the embodiment (at the time of direct connection by the docking connector).

FIG. 10 is a diagram showing the connection presence / absence detection of the docking station 200 by the docking connection unit of the embodiment (part 2);
FIG. 7 (when directly connected by a docking connector).

FIG. 11 is a view for explaining a state of bus connection between a computer main body and an expansion unit in a conventional computer system.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Processor bus 2 ... PCI bus (primary) 3 ... PCI bus (secondary) 11 ... CPU 12 ... Host-PCI bridge 13 ... Main memory 14 ... PCI device (computer main body side) 15 ... Switch 16 ... Conventional type PCI-PCI Bridge 17 PCI device (extension unit side) 31 Clock (CLK) stop circuit 32 PCI bus control block (PCI_CT)
L) 33: Transaction buffer & control block (TBC) 34: Block & word buffer block (BWB) 35: Block transfer buffer block (BLB) 36: Configuration register block (CF_)
REG) 41 EC 100 Computer body 200 Expansion unit

Claims (6)

[Claims] 1. A computer system comprising an expansion unit detachably connected to a system main unit via a serial transmission line, comprising: a plurality of bit-width parallel transmission lines respectively laid on the system main unit and the expansion unit. Two buses on the system main unit side and the expansion unit side, and a device on one of the system main unit side and the expansion unit side buses arranged on the system main unit and the expansion unit side, respectively. A bridge device having two controllers, physically different from each other, on the system main unit side and the expansion unit side, which mutually transmit a transaction via the serial transmission path so as to be accessible. A connection detecting means for detecting whether or not the extension unit is connected; And clock control means for interrupting the supply of an operation clock to the controller on the system main body side when the connection detection means detects that the extension unit is not connected. Computer system. 2. A computer system comprising an extension unit detachably connected to a system main unit, wherein the system main unit includes: connection control means for controlling interconnection with the extension unit; and connection of the extension unit. Connection detection means for detecting the presence / absence of the expansion unit, and clock control means for interrupting supply of an operation clock to the connection control means when the connection detection means detects that the extension unit is not connected. A computer system characterized by: 3. The computer system according to claim 1, wherein said connection detecting means includes means for reading data in a nonvolatile semiconductor memory built in said extension unit. 4. The computer system according to claim 1, wherein said connection detecting means includes means for identifying a potential of a conductor forced to a predetermined potential by connection of said extension unit. 5. The computer system according to claim 1, wherein said connection detecting means includes means for identifying a state of a switch operated by connection of said extension unit. 6. A clock control method for a computer system having an expansion unit detachably connected to a system main body, the method comprising: detecting whether or not the expansion unit is connected; and indicating that the expansion unit is not connected. And c. Cutting off the supply of an operation clock to connection control means for controlling interconnection with the extension unit when detecting the clock signal.