JP2001156629A - Phase locked loop and frequency synthesizer having the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase locked loop that can ensure a stable operation even when the frequency division number of a frequency divider is changed and to provide a frequency synthesizer having the loop. SOLUTION: When an N-value data latch circuit 6 receives N-value data denoting a frequency division number, a frequency divider 5 multiplies the output signal of a VCO 4 by (1/N) and a memory 7 outputs a voltage VC stored in an address corresponding to the frequency division number N. A charge pump current control circuit 8 whose resistor 11 receives the voltage VC controls a current outputted from the charge pump 2 so that a phase difference - current conversion gain Kp of the charge pump 2 is multiplied by (N/NR) when the frequency division number is NR. Thus, even when the frequency division number is increased to M-fold, since the phase difference - current conversion gain Kp is also multiplied by M based on the data stored in the memory 7, an open loop gain A(s) is not fluctuated. Since the open loop gain A(s) is not fluctuated, no phase margin is fluctuated and the stability of the operation of the PLL is ensured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked loop suitable for a communication device such as a portable telephone and a frequency synthesizer having the same, and more particularly, to a phase-locked loop having improved operation stability and a frequency synthesizer having the same. About.

[0002]

2. Description of the Related Art Conventionally, a phase locked loop (PLL: Phase Rock Loop) is incorporated in a frequency synthesizer. FIG. 5 is a block diagram showing the configuration of a conventional PLL.

A conventional PLL includes a voltage controlled oscillator (VC)
O) 104 and a frequency divider 105 for dividing the output signal of the VCO 104. Also, a phase comparator 101 that compares the phase of the frequency-divided signal from the frequency divider 105 with the phase of the reference signal, a charge pump 102 that converts the phase difference detected by the phase comparator 101 into a current, and a predetermined frequency A loop filter 103 that extracts only a signal and outputs the signal to the VCO 104 is provided.

A loop filter 103 is connected between the signal line between the charge pump 102 and the VCO 104 and the ground, and has a capacitance of C1 and is connected in series with the capacitor between the signal line and the ground in parallel with the capacitor. Are connected to a capacitor having a capacitance value of C2 and a resistance element having a resistance value of R.

[0005] In this conventional PLL, VC
The modulation sensitivity Kv (Hz / V) of O104 and the phase difference-current conversion gain Kp (mA / rad) of the charge pump 102 are fixed values. Therefore, the unity gain angular frequency (ω
p) and the phase margin (θp) are determined, and the filter constant of the loop filter is determined.

The unity gain angular frequency (ωp)
Is the angular frequency when the open loop gain is 1 (0 dB), and the phase margin is the phase when the angular frequency (ωp).

The parameters that determine the stability of the PLL are the unity gain angular frequency (ωp) and the phase margin.
The transfer characteristic of LL is obtained as follows.

The open loop gain H (s) and the closed loop gain A (s) are expressed by the following equations 1 and 2, respectively.

[0009]

(Equation 1)

[0010]

(Equation 2)

The transfer function F (s) of the loop filter 103
Is represented by Equation 3 below.

[0012]

(Equation 3)

Here, τ1, τ2 and τ3 are defined by the following equations 4 to 6, respectively.

[0014]

(Equation 4)

[0015]

(Equation 5)

[0016]

(Equation 6)

Accordingly, the following equation 7 is derived from equations 2 and 3.

[0018]

(Equation 7)

Here, K is defined by the following equation (8).

[0020]

(Equation 8)

Therefore, if the angular frequency is ω, the open loop gain can be obtained by the following equation (9).

[0022]

(Equation 9)

At this time, the open loop phase θ (j
.Omega.) Is represented by the following equation (10).

[0024]

(Equation 10)

[0025]

However, in the conventional PLL, even if the N value of the frequency divider 105 changes,
Since the filter constant of the loop filter 103, the modulation sensitivity of the VCO 104, and the gain Kp of the charge pump 102 do not change, the transfer characteristics of the PLL change, and the unity gain angular frequency and phase margin change. Therefore, there is a problem that the stability of the PLL is deteriorated.

FIG. 6 is a graph showing the relationship between the frequency, the open gain and the phase by taking the frequency on the horizontal axis and the open gain and phase on the vertical axis. In FIG. 6, the lowermost curve shows the phase, and the other two curves show the open gain.

For example, when the unity gain angular frequency is ωp
When the frequency division number at the time of 1 is N and the frequency division number is doubled (2 × N), the open loop gain A (s) becomes １ ／ as shown in Expression 2. As a result, as shown in FIG. 6, the unity gain angular frequency is
To ωp2.

On the other hand, since the phase margin is determined only by the filter constant of the loop filter 103 as shown in Expression 10, the phase margin is maximized from the N value before the frequency division number is changed to the unity gain angular frequency. The filter constant is determined. Accordingly, when the frequency division number N doubles, the phase margin decreases from θp1 to θp2, as shown in FIG.

As described above, in the conventional PLL, the condition (K
v, Kp and F (s)) are constant, and if the frequency division number N is changed to twice, the unity gain angular frequency (ω
p) is halved, and the phase margin (θp) is reduced.
The decrease in the phase margin (θp) indicates that the damping increases and the operation of the PLL becomes unstable.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a phase locked loop capable of ensuring stable operation even when the frequency division number of the frequency divider changes, and a frequency synthesizer having the same. The purpose is to provide.

[0031]

A phase locked loop according to the present invention comprises an oscillator, a frequency divider for dividing an output signal of the oscillator, a phase of a frequency divided signal from the frequency divider and a reference signal. A phase comparator that compares the phase with a charge pump that converts the phase difference detected by the phase comparator into a current,
A filter that integrates an output signal of the charge pump, extracts only a signal of a predetermined frequency, and negatively feeds back the signal to the oscillator, and converts the phase difference of the charge pump into a current in association with a frequency division number by the frequency divider. And control means for controlling the gain at the time.

In the present invention, the gain at the time of converting the phase difference of the charge pump pump into current by the control means is automatically set in conjunction with the frequency division number of the frequency divider. However, the open loop gain and the phase margin do not change, and the transfer characteristics are kept constant. Therefore, the PLL of the present invention is always maintained in a stable state.

The control means includes a memory for storing an output voltage set for each frequency dividing number, and a latch circuit for designating an address in the memory in relation to the frequency dividing number set for the frequency divider. And a control circuit for determining a gain when converting the phase difference of the charge pump into a current based on an output signal of the memory, and a frequency division number set in the frequency divider. A selection circuit that outputs a selection signal in association with the control signal, and a gain when converting the phase difference of the charge pump into a current by switching on / off of the switching element by an output signal of the selection circuit. And a control circuit for determining.

The control circuit may include the same number of switching elements as the number of frequency divisions set in the frequency divider, and resistance elements connected to the respective switching elements. Further, the switching element may include a field effect transistor.

A frequency synthesizer according to the present invention includes any one of the above phase locked loops.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a phase locked loop (PLL) according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a block diagram showing the configuration of the PLL according to the first embodiment of the present invention.

In the first embodiment, VCO 4 and this VC
A frequency divider 5 for dividing the output signal of O4 is provided.
Also, a phase comparator 1 for comparing the phase of the frequency-divided signal from the frequency divider 5 with the phase of the reference signal, a charge pump 2 for converting the phase difference detected by the phase comparator 1 into an electric current as an error output, and A loop filter 3 is provided which integrates an output signal of the charge pump 2, extracts only a signal of a predetermined frequency, and negatively feeds back to the VCO 4.

In the first embodiment, an N-value data latch circuit 6 for latching N-value data set in the frequency divider 5 is provided. Further, the charge pump 2 set in association with the output signal from the N-value data latch circuit 6
Gain when converting the phase difference into a current (hereinafter referred to as “phase difference−
A memory 7 in which a voltage value VC for obtaining a current conversion gain “Kp (mA / rad)” is provided. For example, based on a certain frequency division number (NR), the phase difference-current conversion gain Kp is (N / N
The voltage value (VC) that is multiplied by R) is stored in the memory 7.

Further, a charge pump current control circuit 8 for controlling a phase difference-current conversion gain of the charge pump 2 based on data stored at a selected address of the memory 7 is provided.

FIG. 2 is a circuit diagram showing the configuration of the charge pump 2 and the charge pump current control circuit 8 in the first embodiment.

The charge pump current control circuit 8 includes a resistor 11 connected to the memory 7 and an N-channel MOS transistor 12 having a source and a drain connected between the resistor 11 and the ground. The gate of transistor 12 is connected to its drain. An N-channel MOS transistor 13 having a gate connected to the gate of the transistor 12 and a source connected to the ground is provided.

Further, P-channel MOS transistors 14, 15, and 17 whose sources are supplied with the power supply potential VDD are provided. The drain of the transistor 13, the drain and gate of the transistor 14, the drain and gate of the transistor 15, and the gate of the transistor 17 are commonly connected.

Further, N-channel MOS transistors 16 and 20 whose sources are connected to the ground are provided.
The drain and gate of the transistor 16 and the gate of the transistor 20 are connected to the drain of the transistor 15 and the like.

On the other hand, the charge pump 2 has a P-channel MO having a source connected to the drain of the transistor 17.
S transistor 18 and N-channel MOS transistor 19 whose source is connected to the drain of transistor 20
Is provided. The drains of the transistors 18 and 19 are commonly connected, and this common connection point is connected to the loop filter 3. A signal UP instructing a voltage increase from the phase comparator 1 is input to the gate of the transistor 18, and a signal DOWN instructing a voltage drop from the phase comparator 1 is input to the gate of the transistor 19. .

Next, the operation of the PLL of the first embodiment configured as described above will be described. When N-value data indicating the frequency division number is input to the N-value data latch circuit 6, the frequency divider 5 multiplies the output signal of the VCO 4 by (1 / N),
The memory 7 outputs the voltage VC stored at the address corresponding to the frequency division number N.

Then, the charge pump current control circuit 8 in which the voltage VC is applied to the resistor 11 outputs (N / N) when the phase difference-current conversion gain Kp of the charge pump 2 is the frequency division number NR.
The output current of the charge pump 2 is controlled so as to be NR) times.

Therefore, even if the frequency division number increases twice, the phase difference-current conversion gain Kp of the charge pump 2 also doubles based on the data stored in the memory 7, so that the open loop gain A (s) does not change. Since the open loop gain A (s) does not change, the phase margin does not change. Therefore, even if the frequency division number increases twice, PL
The operation stability of L is ensured.

It should be noted that the change of the frequency division number is not limited to two times, and the stability of the PLL according to the present embodiment is ensured regardless of the magnification.

Next, a second embodiment of the present invention will be described. The second embodiment is a PLL suitable for a type in which the number of division numbers set is relatively small. Since the memory 7 in the first embodiment requires a relatively large number of elements, if the memory 7 is formed into a large-scale integrated circuit (LSI), the area of the LSI becomes large. It is suitable when there are many. However, if the memory 7 is used even when the number of frequency divisions is small, the circuit scale becomes unnecessarily large, so there is no need to use the memory. Therefore, in the second embodiment, a selection circuit is provided instead of the memory. FIG. 3 shows a PLL according to a second embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG. In addition, the second shown in FIG.
In this embodiment, the same components as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the second embodiment, there is provided a frequency division number selection circuit 9 which is input before N-value data set in the frequency divider 5 is input to the N-value data latch circuit 6. . The division number selection circuit 9 selects a selection signal input terminal provided in a charge pump current control circuit 10 to be described later in association with the N value selection data input signal, and the N number data latch circuit 6 Is provided. In the second embodiment, the phase difference-current conversion gain K of the charge pump 2 is related to the signal from the frequency division number selection circuit 9.
A charge pump current control circuit 10 for controlling p (mA / rad) is provided.

FIG. 4 is a circuit diagram showing the configuration of the charge pump 2 and the charge pump current control circuit 10 in the second embodiment. In the circuit in the second embodiment shown in FIG. 4, the same components as those in the circuit in the first embodiment shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. . The type of frequency division number set in frequency divider 5 is k
Type.

In the charge pump current control circuit 10, the same number (k) of P-channel MOS transistors 21-1, 21-2,...
-K is provided. Transistors 21-1 to 21-
The power supply voltage VDD is supplied to each source of k. The gates of the transistors 21-1 to 21-k are connected to the frequency division number selection circuit 9.

The charge pump current selection circuit 10 further includes transistors 21-1, 21-2,.
K resistance elements 22-1, 22-22 connected between each drain of the transistor 12 and the drain and gate of the transistor 12.
2,... 22-k are provided. Resistance elements 22-1 to 22-1
22-k have different resistance values, and
With respect to the frequency division number for turning on 1-1 to 21-k, the phase difference-current conversion gain Kp is set based on a certain frequency division number (NR).
Is set to be (N / NR) times. For example, when obtaining the reference frequency division number NR, the transistor 21-1
Is turned on, and the phase difference-current conversion gain at that time is Kp
1 and the frequency division number when the transistor 21-2 is turned on is 2 × NR, the resistance value of the resistance element 22-2 is equal to the phase difference obtained when the transistor 21-2 is turned on. The current conversion gain Kp2 is set to be twice as large as Kp1.

Next, the operation of the PLL of the second embodiment configured as described above will be described. Dividing number selection circuit 9
When N-value selection data indicating the number of divisions is input to the N-value data latch circuit 6, the N-number selection circuit 9 sets the number of divisions.
To output N-value data. As a result, the frequency divider 5
4 is multiplied by (1 / N).

Further, the frequency division number selection circuit 9 outputs the selected data to the charge pump current control circuit 10 at the same time as outputting the N value data. The charge pump current control circuit 10 to which the selection data is input switches on / off of the transistors 21-1 to 21-k based on the selection data, and switches the on / off of the resistance elements 22-1 to 22-k. The phase difference-current conversion gain Kp is determined by the resistance value of the connection.

As a result, according to the second embodiment, even if the frequency division number is increased by M times, the frequency difference selection circuit 9 and the charge pump current control circuit 10 control the phase difference-current conversion gain of the charge pump 2. Since Kp also becomes M times, the open loop gain A (s) does not change. Since the open loop gain A (s) does not change, the phase margin does not change. Therefore, even if the frequency division number changes, the stability of the operation of the PLL is ensured.

Note that these PLLs can be used, for example, by being built in a frequency synthesizer.

[0058]

As described in detail above, according to the present invention,
Since the control means for automatically setting the phase difference-current conversion gain of the charge pump pump in conjunction with the frequency division number of the frequency divider is provided, even if the frequency division number changes, the open loop gain and the phase margin And the transfer characteristics can be kept constant. Thereby, it is possible to always maintain a stable state.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a PLL according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a charge pump 2 and a charge pump current control circuit 8 in the first embodiment.

FIG. 3 is a block diagram illustrating a configuration of a PLL according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a charge pump 2 and a charge pump current control circuit 10 in a second embodiment.

FIG. 5 is a block diagram showing a configuration of a conventional PLL.

FIG. 6 is a graph showing the relationship between frequency, open gain, and phase.

[Explanation of symbols]

 1, 101; phase comparator 2, 102; charge pump 3, 103; loop filter 4, 104; voltage controlled oscillator (VCO) 5, 105; frequency divider 6, N-value data latch circuit 7, memory 8, 10; Charge pump current control circuit 9; frequency division number selection circuit

Claims (6)

[Claims] An oscillator; a frequency divider for dividing an output signal of the oscillator; a phase comparator for comparing a phase of a frequency-divided signal from the frequency divider with a phase of a reference signal; A charge pump that converts the phase difference detected by the divider into a current, a filter that integrates an output signal of the charge pump, extracts only a signal of a predetermined frequency, and negatively feeds back to the oscillator, and a frequency divider by the frequency divider Control means for controlling a gain when converting the phase difference of the charge pump into a current in relation to a number. 2. The memory according to claim 1, wherein said control means stores an output voltage set for each frequency division number, and a latch circuit for specifying an address in said memory in relation to the frequency division number set for said frequency divider. The phase-locked loop according to claim 1, further comprising: a control circuit that determines a gain when converting the phase difference of the charge pump into a current based on an output signal of the memory. 3. A selection circuit for outputting a selection signal in association with a frequency division number set in the frequency divider,
A control circuit that has a built-in switching element and switches on / off of the switching element according to an output signal of the selection circuit to determine a gain when the phase difference of the charge pump is converted into a current. The phase-locked loop according to claim 1. 4. The control circuit according to claim 1, wherein the control circuit includes the same number of switching elements as the number of frequency divisions set in the frequency divider, and resistance elements connected to the respective switching elements. A phase locked loop according to claim 3. 5. The phase locked loop according to claim 3, wherein the switching element includes a field effect transistor. 6. A frequency synthesizer comprising the phase-locked loop according to claim 1.