JP2001144188A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, that mixedly mounts a two-layer polysilicon capacity element with small voltage dependence and a MOS transistor with small threshold fluctuation. SOLUTION: A LOCOS film 7 is formed (A), a sacrificial oxide film 29 and a silicon nitride film 30 are formed (B), a polysilicon film 31 is deposited (C), the silicon nitride film 30 prevents phosphor from diffusing into a MOS transistor region, and at the same time, the phosphor is introduced to the polysilicon film 31 with high concentration, and a lower electrode 31a is formed by a polysilicon film 31 (D). The silicon nitride film 30 is removed, impurities for controlling threshold are injected into the MOS transistor region across the sacrificial oxide film 29, the sacrificial oxide film 29 is removed (E), an interlayer insulating film 33 and a silicon oxide film 35 are simultaneously formed (F), a polysilicon film 37 is deposited on them (G), and an upper electrode 37a and a gate electrode pattern 37b are formed simultaneously by the polysilicon film 37.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device including at least a MOS transistor and a two-layer polysilicon capacitor (a capacitor having a polysilicon-interlayer insulating film-polysilicon structure) on the same substrate. Things.

[0002]

2. Description of the Related Art FIG. 1 is a process sectional view showing a conventional method for manufacturing a semiconductor device including a MOS transistor and a two-layer polysilicon capacitor. (A) On the surface of a silicon substrate 1, an oxidation-resistant film made of a laminated film of a buffer oxide film 3 and a silicon nitride film 5 is formed. A LOCOS film 7 as a field oxide film for element isolation is formed by performing a thermal oxidation process to form an active region of the MOS transistor. (B) After removing the buffer oxide film 3 and the silicon nitride film 5 used for patterning the LOCOS film 7, a sacrificial oxide film 9 is formed on the surface of the silicon substrate 1, and a sacrificial oxide film 9 is further formed thereon by, for example, CVD. A polysilicon film 11 serving as a lower electrode is deposited.

(C) After an impurity is introduced at a high concentration into the polysilicon film 11 by an impurity diffusion technique, the lower electrode 11 is subjected to a photolithography step and an etching step.
a is formed. (D) After removing the exposed sacrificial oxide film 9, an oxidation process is performed to form an interlayer insulating film 13 on the exposed surface of the lower electrode 11a, and a gate oxide is formed on the surface of the active region of the MOS transistor. A silicon oxide film 15 for a film is formed. Next, a polysilicon film 17 serving as an upper electrode of the capacitor and a gate electrode of the MOS transistor is deposited on the silicon substrate 1.

(E) After an impurity is introduced into the polysilicon film 17 by an impurity diffusion technique, an upper electrode 17a is formed on the lower electrode 11a via an interlayer insulating film 13 through a photolithography step and an etching step. 2 composed of electrode 11a-interlayer insulating film 13-upper electrode 17a
A layer polysilicon capacitor is formed on the LOCOS film 7. At the same time as the formation of the upper electrode 17a, a gate electrode pattern 17b is formed on the active region of the MOS transistor via the silicon oxide film 15. Next, the silicon oxide film 15 excluding the portion under the gate electrode pattern 17b is removed to form a gate oxide film 15a, and a diffusion layer is formed to form a MOS transistor.

[0005]

The impurity concentration introduced into the polysilicon film 11 for the lower electrode 11a is, for example, 1 × 10 5 in order to reduce the voltage dependency of the capacitor.
It is often set to a high concentration of about ²⁰ cm ^-3 . As a result, the impurity concentration gradient between the polysilicon film 11 and the surrounding sacrificial oxide film 9 becomes steep, and the polysilicon film 11 is subjected to a heat treatment at the time of impurity introduction into the polysilicon film 11 and a heat treatment by a process step after the introduction. A phenomenon occurs in which impurities in 11 diffuse and redistribute into sacrificial oxide film 9.

Japanese Patent Application Laid-Open No. 05-121735 discloses a method of positively using this for controlling the threshold value of a transistor, in which diffusion of impurities in an oxide film is accelerated in a hydrogen atmosphere. I have. Also, as a method of preventing diffusion of impurities into the peripheral silicon oxide film,
In the method disclosed in Japanese Patent Application Laid-Open No. 10-303410, the barrier layer is used as a barrier layer in order to prevent boron in the P-type polysilicon gate electrode from diffusing into the surrounding silicon oxide film and depleting the gate electrode. A method of covering an upper portion and a side portion of a polysilicon gate electrode with a silicon nitride film has been proposed. However, this method cannot prevent the diffusion of impurities from the lower portion of the polysilicon to the silicon substrate.

In the case of a conventional two-layer polysilicon process,
As shown in FIG. 1B, a relatively thin sacrificial oxide film is formed between the silicon substrate 1 and the polysilicon film 11 during the introduction of impurities into the polysilicon film 11 for the lower electrode 11a or during the subsequent heat treatment. Since only 9 exists, impurities are easily introduced into the silicon substrate 1 side. By the unintended impurity introduction, a MOS formed later is formed.
There is a problem that the threshold value of the transistor varies.

Therefore, the present invention provides a method of manufacturing a semiconductor device in which a MOS transistor and a capacitance element having a polysilicon-interlayer insulating film-polysilicon structure are mixedly mounted. It is an object of the present invention to provide a method of manufacturing a semiconductor device in which the variation in the threshold value of a MOS transistor is small by preventing the above.

[0009]

According to a first aspect of the present invention, there is provided:
A method of manufacturing a semiconductor device including at least a MOS transistor and a polysilicon-interlayer insulating film-capacitor having a polysilicon structure on the same substrate, wherein the capacitor is formed by the following steps (A) to (D). Form.
(A) After forming an element isolation region using an oxidation-resistant element isolation patterning film having an opening in the element isolation region, covering the MOS transistor region, the semiconductor substrate is left in a state where the element isolation patterning film is left. A step of forming a first polysilicon film for a lower electrode constituting a capacitor element thereon, and (B) introducing an impurity into the first polysilicon film and patterning the same to form a capacitor element on the element isolation region. Forming a lower electrode, (C) forming an interlayer insulating film constituting the capacitor on the surface of the lower electrode, and (D) forming an upper electrode of the capacitor on the lower electrode via the interlayer insulating film. Process.

Since the first polysilicon film for the lower electrode constituting the capacitive element is formed with the patterning film for element isolation left, the semiconductor substrate of the active region (MOS transistor region) of the MOS transistor and the first polysilicon film are formed. A patterning film for element isolation remains between the polysilicon and the polysilicon. As a result, when the impurity is introduced into the first polysilicon film, even if the impurity diffuses from the first polysilicon film to the semiconductor substrate side, the remaining element isolation patterning film is not doped into the semiconductor substrate. M to prevent diffusion
Unintended diffusion of impurities into the active region of the OS transistor can be prevented.

In a second aspect of the present invention, the following step (A)
The method is a method for manufacturing a semiconductor device in which a capacitive element is formed from step (E) to step (E). (A) An element isolation region is formed using an element isolation patterning film covering the MOS transistor region, and after the element isolation patterning film is removed, diffusion of impurities into the MOS transistor region is performed at least on the MOS transistor region. Forming a base film to be prevented, (B) forming a first polysilicon film for a lower electrode constituting a capacitor on a semiconductor substrate, and (C) introducing impurities into the first polysilicon film. And forming a lower electrode of the capacitive element on the element isolation region by patterning, (D) forming an interlayer insulating film constituting the capacitive element on the surface of the lower electrode, and (E) forming a lower electrode on the lower electrode. Forming an upper electrode of the capacitive element via an interlayer insulating film;

After removing the patterning film for element separation,
Since the base film is formed at least on the MOS transistor region, the base film exists between the semiconductor substrate and the first polysilicon in the active region of the MOS transistor. As a result, when impurities are introduced into the first polysilicon film, even if the impurities diffuse from the first polysilicon film toward the semiconductor substrate, the base film prevents the impurities from diffusing into the semiconductor substrate. In addition, unintended diffusion of impurities into the active region of the MOS transistor can be prevented. Also, since the underlying film is not patterned, there is no steep step,
During the patterning of the first polysilicon film, a residue of the polysilicon film hardly occurs.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the manufacturing method according to the first aspect,
The patterning film for element isolation preferably includes a silicon nitride film layer. Further, the interlayer insulating film forming the capacitive element is a silicon oxide film. In the step (C), before forming the interlayer insulating film, the patterning film for element isolation is removed to expose the surface of the MOS transistor region. It is preferable that a silicon oxide film for a gate oxide film of a MOS transistor is simultaneously formed on the surface of the MOS transistor region when the interlayer insulating film is formed. As a result, the number of manufacturing steps can be reduced.

Further, the element isolation patterning film is a laminated film of a silicon oxide film as a lower layer and a silicon nitride film as an upper layer. In the step (C), when the patterning film for element isolation is removed, the patterning for element isolation is performed. After removing only the silicon nitride film of the film, the silicon oxide film of the element isolation patterning film remaining in the MOS transistor region is used as a protective film for impurity implantation for threshold value control via the silicon oxide film through the silicon oxide film. It is preferable to include a step of implanting impurities into the substrate. As a result, the number of manufacturing steps can be reduced.

Further, the step (D) includes the steps of:
Forming a second polysilicon film for the upper electrode;
Forming an upper electrode by introducing an impurity into the polysilicon film and patterning the upper electrode. When patterning the second polysilicon film, a step of forming an upper electrode on a region including a silicon oxide film for a gate oxide film is performed. It is preferable to form a gate electrode pattern for a MOS transistor made of the second polysilicon film. As a result, the number of manufacturing steps can be reduced.

In the manufacturing method according to the second aspect, it is preferable that the underlying film is any one of a silicon oxide film and a silicon nitride film, or a laminated film of a lower silicon oxide film and an upper silicon nitride film. In the case of a silicon oxide film, it is preferable to make the thickness sufficiently large with respect to the diffusion distance of the impurity seeping out. Further, the interlayer insulating film constituting the capacitive element is a silicon oxide film, and the step (D) includes a step of removing a base film and exposing a surface of the MOS transistor region before forming the interlayer insulating film. When forming the interlayer insulating film, it is preferable to simultaneously form a silicon oxide film for a gate oxide film of the MOS transistor on the surface of the MOS transistor region. As a result, the number of manufacturing steps can be reduced.

The underlying film is a laminated film in which the lower layer is a silicon oxide film and the upper layer is a silicon nitride film. In the step (D), when the underlying film is removed, only the underlying silicon nitride film is removed. Preferably, the method further includes a step of implanting impurities into the MOS transistor region via the silicon oxide film using the underlying silicon oxide film remaining in the MOS transistor region as a protective film for impurity implantation for controlling a threshold value. As a result, the number of manufacturing steps can be reduced.

Further, the step (E) includes the steps of:
Forming a second polysilicon film for the upper electrode;
Forming an upper electrode by introducing an impurity into the polysilicon film and patterning the upper electrode. When patterning the second polysilicon film, a step of forming an upper electrode on a region including a silicon oxide film for a gate oxide film is performed. It is preferable to form a gate electrode pattern for a MOS transistor made of the second polysilicon film. As a result, the number of manufacturing steps can be reduced.

[0019]

FIG. 2 is a process sectional view showing an embodiment of the first aspect of the method for manufacturing a semiconductor device according to the present invention. However, the embodiments described below do not limit the method of manufacturing a semiconductor device according to the present invention, and various modifications can be made within the scope of the present invention described in the claims.

(A) A buffer oxide film 3 having a film thickness of 25 nm and a film thickness of 100 n are formed on a silicon substrate 1 to form a patterning film for element isolation for forming a LOCOS film.
After the m silicon nitride film 5 is formed on the MOS transistor region, a LOCOS film 7 having a thickness of, for example, 450 nm is formed using a normal LOCOS film method. (B) With the buffer oxide film 3 and the silicon nitride film 5 used when forming the LOCOS film 7 remaining,
A polysilicon film 21 serving as a lower electrode of the layered polysilicon capacitor is formed with a thickness of, for example, 350 nm by a CVD method.

(C) An energy of, eg, 40 keV, 5 × 1 is applied to the polysilicon film 21 by using an impurity diffusion technique.
Phosphorus is implanted under the condition of a dose of 0 ¹⁵ cm ^-2 ,
Phosphorus is introduced at a concentration of × 10 ²⁰ cm ^-3 . At this time, in order to diffuse phosphorus into the polysilicon film 21, 90
A heat treatment of about 0 degrees is performed. In the prior art, at the time of this heat treatment, phosphorus diffuses into the active region of the MOS transistor on the silicon substrate 1 and causes a variation in the threshold value of the MOS transistor. Since the oxide film 3 and the silicon nitride film 5 are left, the diffusion of phosphorus does not reach the silicon substrate 1 unlike the prior art, and the variation in the threshold value of the MOS transistor can be suppressed. Then, the lower electrode 21a of the capacitor is formed on the LOCOS film 7 by using a photolithography technique and a patterning technique.

(D) The buffer oxide film 3 and the silicon nitride film 5 on the active region of the MOS transistor are removed by an etching technique. At this time, the silicon nitride film 5 may be removed using a dry etching method or may be selectively removed using a wet etching method. After removing only the silicon nitride film 5, ion implantation for threshold control is performed on the region of the silicon substrate 1 serving as an active region of the MOS transistor via the buffer oxide film 3,
Thereafter, the buffer oxide film 3 may be removed.

(E) A heat treatment is performed to form an interlayer insulating film 23 with a thickness of, for example, 30 nm on the exposed surface of the lower electrode 21a and, for example, on the surface of the silicon substrate 1 in the active region of the MOS transistor. A silicon oxide film 25 for a gate oxide film is formed to a thickness of 15 nm. (F) The upper electrode of the capacitive element and M
Polysilicon film 2 serving as gate electrode of OS transistor
7 is deposited to a thickness of, for example, 350 nm by the CVD method.

(G) Polysilicon by impurity diffusion technology
The energy of 40 keV, 5 × 10
^Fifteencm^-2The phosphorus is implanted under the condition of the dose amount of 1.times.
10 ²⁰cm^-3After introducing phosphorus to a concentration of
After a roughing process and an etching process, the lower electrode 21
upper electrode 27a is formed on interlayer insulating film 23 via interlayer insulating film 23
Lower electrode 21a-interlayer insulating film 23-upper electrode 27a
A two-layer polysilicon capacitor composed of LOCOS film 7
Formed. Further, simultaneously with the formation of the upper electrode 27a, M
A silicon oxide film 25 is formed on the active region of the OS transistor.
, A gate electrode pattern 27b is formed.

Next, the gate oxide film 25a is formed by removing the silicon oxide film 25 except under the gate electrode 27b, and a diffusion layer is formed to form a MOS transistor. The final sheet resistance (resistance per unit area) of the lower electrode 21a is 15Ω / □ or less. As described above, the lower electrode 21a-the interlayer insulating film 23-the upper electrode 27
A two-layer polysilicon capacitor element made of a and having a lower electrode 21a having a high impurity concentration and a low voltage dependency and a MOS transistor having a small threshold variation can be formed on the same silicon substrate 1. Further, since only the buffer oxide film 3 and the silicon nitride film 5 are left, the present invention can be realized without increasing the number of steps.

FIG. 3 is a process sectional view showing an embodiment of the second aspect of the method for manufacturing a semiconductor device according to the present invention. (A) After a LOCOS film 7 is formed on a silicon substrate 1 by using a normal LOCOS film method, for example, by wet etching, an element isolation composed of a stacked film of a buffer oxide film and a silicon nitride film used in the LOCOS film method is used. The pattern film is removed. (B) A sacrificial oxide film 2 made of a silicon oxide film having a thickness of 11 ± 1 nm on the silicon substrate 1 by a thermal oxidation process.
9 and then LPCVD (Low Pressu
A silicon nitride film 30 having a thickness of 100 ± 10 nm is formed by a re-CVD method. The underlayer film according to the second aspect of the present invention comprises a sacrificial oxide film 29 and a silicon nitride film 30 in this embodiment. (C) Further, on the silicon nitride film 30, a polysilicon film 31 to be a lower electrode of the two-layer polysilicon capacitance element is formed with a thickness of, for example, 350 nm by the CVD method.

(D) An energy of, for example, 40 keV, 5 × 1 is applied to the polysilicon film 31 by using an impurity diffusion technique.
Phosphorus is implanted under the condition of a dose of 0 ¹⁵ cm ^-2 ,
Phosphorus is introduced at a concentration of × 10 ²⁰ cm ^-3 . At this time, in order to diffuse phosphorus into the polysilicon film 21, 90
A heat treatment of about 0 degrees is performed. In the prior art, at the time of this heat treatment, phosphorus diffuses into the MOS transistor region of the silicon substrate 1 and causes a variation in the threshold value of the MOS transistor. In this embodiment, however, a base film is formed on the MOS transistor region. Since the sacrificial oxide film 29 and the silicon nitride film 30 are formed as described above, the diffusion of phosphorus does not reach the silicon substrate 1 as in the prior art.
Variations in the threshold value of the MOS transistor can be suppressed.

Then, using a photolithography technique, a photoresist mask is formed on the polysilicon film 31 in a predetermined region where the lower electrode of the capacitor is to be formed, and the polysilicon film 31 is selectively etched using the photoresist mask as a mask. Thus, a lower electrode 31a is formed on the LOCOS film 7. At this time, as shown in step (C) of the embodiment of FIG.
Since there is no step due to the buffer oxide film 3 and the silicon nitride film 5, no residue is generated when the polysilicon film 31 is etched.

(E) The silicon nitride film 30 existing in a region other than under the lower electrode 31a is removed by, for example, wet etching using hot phosphoric acid. Then, in order to adjust the threshold value of the MOS transistor to a desired value, an impurity is added to the region of the silicon substrate 1 serving as the active region of the MOS transistor through the sacrificial oxide film 29 by a normal photolithography process and an ion implantation process. Implant ions. Thereafter, the sacrificial oxide film 29 existing in a region other than the region below the lower electrode 31a is removed by, for example, wet etching using hydrofluoric acid, exposing a region of the silicon substrate 1 which becomes an active region of the MOS transistor. When the silicon nitride film 30 is removed by etching, the sacrificial oxide film 29 is removed.
Is hardly removed by hot phosphoric acid. Therefore, the thickness of the sacrificial oxide film 29 can be reduced, and impurity ions for controlling the threshold can be implanted through the sacrificial oxide film 29 having a small thickness variation.
Variations in the threshold value of the S transistor can be suppressed.

(F) A heat treatment is performed to form an interlayer insulating film 33 having a thickness of, for example, 30 nm on the exposed surface of the lower electrode 31a, and to form, for example, on the surface of the silicon substrate 1 in the active region of the MOS transistor. A silicon oxide film 35 for a gate oxide film is formed to a thickness of 15 nm. (G) On the silicon substrate 1, the upper electrode of the capacitive element and M
Polysilicon film 3 serving as gate electrode of OS transistor
7 is deposited to a thickness of, for example, 350 nm by the CVD method.

(H) Polysilicon by impurity diffusion technology
The energy of 40 keV, for example, 5 × 10
^Fifteencm^-2The phosphorus is implanted under the condition of the dose amount of 1.times.
10 ²⁰cm^-3After introducing phosphorus to a concentration of
After a roughing process and an etching process, the lower electrode 31
upper electrode 37a is formed on interlayer insulating film 33 via interlayer insulating film 33
Lower electrode 31a-interlayer insulating film 33-upper electrode 37a
A two-layer polysilicon capacitor composed of LOCOS film 7
Formed. Further, simultaneously with the formation of the upper electrode 37a, M
A silicon oxide film 35 is formed on the active region of the OS transistor.
, A gate electrode pattern 37b is formed.

Next, the silicon oxide film 35 except the portion under the gate electrode 27b is removed to form a gate oxide film 35a, and a diffusion layer is formed to form a MOS transistor. The final sheet resistance (resistance per unit area) of the lower electrode 21a is 15Ω / □ or less. As described above, the lower electrode 31a-the interlayer insulating film 33-the upper electrode 37
A two-layer polysilicon capacitor element made of a and having a lower impurity concentration of the lower electrode 31a with a high concentration and low voltage dependency and a MOS transistor with a small variation in threshold voltage can be formed on the same silicon substrate 1.

Further, according to this embodiment, no residue is generated when the polysilicon film 31 is etched, and there is an effect of preventing a decrease in product yield. Further, since the formation of the sacrificial oxide film 29 used for ion implantation for controlling the threshold value of the MOS transistor is performed before the formation of the lower electrode 31a, a thermal oxidation process and an etching process are performed after the formation of the lower electrode 31a. It is possible to reduce the number of times, that is, omit the formation of a sacrificial oxide film exclusively for controlling the threshold value, and to reduce the variation in the two-layer polysilicon capacitance element due to the roughness of the surface of the interlayer insulating film 33 formed on the surface of the lower electrode 31a. There is an effect that can be reduced. Also in the embodiment of FIG. 2, if the buffer oxide film 3 is used as a sacrificial oxide film for controlling the threshold value, the number of times of performing the thermal oxidation process and the etching process after the formation of the lower electrode 21a can be reduced. Variations in polysilicon capacitance elements can be reduced.

Here, a laminated film of the sacrificial oxide film 29 and the silicon nitride film 30 is used as a base film of the polysilicon film 31. However, the base film is not limited to this. Even if a single-layer film composed of any one of a film (high-temperature oxide film), a silicon nitride film or a silicon oxynitride film, and a laminated film thereof is used, it is possible to prevent a decrease in product yield due to generation of residues. In addition, there is an effect of preventing the diffusion of phosphorus into the active region silicon substrate. In these examples, ion implantation is used as a method for introducing phosphorus into the polysilicon film.
The present invention is not limited to this, and solid phase diffusion technology may be used.

[0035]

In the method of manufacturing a semiconductor device according to the first aspect, after forming an element isolation region using an element isolation patterning film for forming a LOCOS film that covers the MOS transistor region, the element isolation patterning film is formed. In the remaining state, a first polysilicon film for a lower electrode constituting a capacitive element is formed, and when impurities are introduced into the first polysilicon film, a first polysilicon film is formed between the first polysilicon film and the semiconductor substrate. Since the patterning film for element isolation is made to remain, even if the impurity seeps out of the first polysilicon film toward the semiconductor substrate, the remaining patterning film for element isolation blocks the diffusion of the impurity. It is possible to prevent unintentional seepage of impurities into the active region of a MOS transistor, and to reduce variations in the electrical characteristics of the transistor. Kill.

In the method of manufacturing a semiconductor device according to the second aspect, since the patterning film for element isolation includes a silicon nitride film layer having a high impurity blocking ability, the first polysilicon film is moved from the first polysilicon film to the semiconductor substrate side. Of the MOS transistor can be improved, and the variation in the electrical characteristics of the MOS transistor can be further reduced. In the method of manufacturing a semiconductor device according to the third and eighth aspects, the interlayer insulating film forming the capacitive element is a silicon oxide film, and the interlayer insulating film and the silicon oxide film for the gate oxide film of the MOS transistor are formed simultaneously. As a result, the number of manufacturing steps can be reduced, and variations in the two-layer polysilicon capacitance element can be reduced.

In the method of manufacturing a semiconductor device according to the present invention, the patterning film for element isolation is a laminated film of a silicon oxide film as a lower layer and a silicon nitride film as an upper layer. Since it is also used as a protective film for impurity injection for controlling the threshold value, the number of steps can be reduced, and the cost can be reduced.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device, the second polysilicon film is patterned.
Since the upper electrode of the capacitor and the gate electrode pattern of the MOS transistor are formed at the same time, the number of manufacturing steps can be reduced.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device, after removing the element isolation patterning film, a base film for preventing diffusion of impurities into the MOS transistor region is formed at least on the MOS transistor region. Therefore, a base film remains between the semiconductor substrate in the active region of the MOS transistor and the first polysilicon,
When introducing impurities into the first polysilicon film, the first
Even if an impurity seeps out of the polysilicon film to the semiconductor substrate side, the remaining element isolation patterning film blocks the diffusion of the impurity, thereby preventing unintentional seepage of the impurity into the active region of the MOS transistor. Accordingly, variation in electrical characteristics of the transistor can be reduced.

In the method of manufacturing a semiconductor device according to the present invention, the base film may be any one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminated film of a lower silicon oxide film and an upper silicon nitride film. In the case of a silicon oxide film, the thickness of the silicon oxide film is set to be sufficiently large with respect to the diffusion distance of the impurity seeping out, so that the diffusion of the impurity from the first polysilicon film to the semiconductor substrate side can be prevented. And the variation in the electrical characteristics of the MOS transistor can be further reduced.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device, the underlying film is a laminated film including a silicon oxide film as a lower layer and a silicon nitride film as an upper layer, and the silicon oxide film as the underlying film is used for controlling a threshold. Since it is also used as a protective film for impurity implantation, the number of steps can be reduced, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a conventional method for manufacturing a semiconductor device including a MOS transistor and a two-layer polysilicon capacitor.

FIG. 2 shows a first example of a method of manufacturing a semiconductor device according to the present invention.
It is a process sectional view showing an example of an aspect.

FIG. 3 shows a second example of the semiconductor device manufacturing method according to the present invention.
It is a process sectional view showing an example of an aspect.

[Explanation of symbols]

Reference Signs List 1 silicon substrate 3 buffer oxide film for device isolation patterning film 5 silicon nitride film for device isolation patterning film 7 LOCOS film 9 buffer oxide film 11, 21, 31 polysilicon film for lower electrode of capacitive element 11a, 21a , 31a Lower electrode of capacitive element 13, 23, 33 Interlayer insulating film of capacitive element 15 Silicon oxide film for gate oxide film 15a Gate oxide film 17, 27, 37 Polysilicon film 17a, 27a for upper electrode of capacitive element 37a Upper electrode of capacitive element 29 Buffer oxide film for base film 30 Silicon nitride film for base film

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Kazumi Hara 1-3-6 Nakamagome, Ota-ku, Tokyo Stock inside Ricoh Company (72) Naohiro Ueda 1-3-6 Nakamagome, Ota-ku, Tokyo Stock Ricoh Company (72) Inventor Masato Takashima 1-3-6 Nakamagome, Ota-ku, Tokyo F-term (reference) 5R038 AC03 AC05 AC15 AC18 AV06 EZ13 EZ15 EZ16 EZ20 5F048 AA07 AA09 AC10 BB05 BB14 BD04 BG12 DA09 DA18 DA19 DB04

Claims (10)

[Claims] 1. A method of manufacturing a semiconductor device including at least a MOS transistor and a polysilicon-interlayer insulating film-capacitance element having a polysilicon structure on the same substrate by the following steps (A) to (D). A method for manufacturing a semiconductor device, comprising forming a capacitor. (A) After forming an element isolation region by using an oxidation-resistant element isolation patterning film having an opening in the element isolation region and covering the MOS transistor region, a semiconductor is formed while the element isolation patterning film is left. Forming a first polysilicon film for a lower electrode constituting the capacitive element on a substrate; (B) introducing an impurity into the first polysilicon film and patterning the first polysilicon film to form a first polysilicon film on the element isolation region; Forming a lower electrode of the capacitive element, (C) forming an interlayer insulating film constituting the capacitive element on the surface of the lower electrode, (D) interposing the interlayer insulating film on the lower electrode. Forming an upper electrode of the capacitor element made of a second polysilicon film. 2. The method according to claim 1, wherein the element isolation patterning film includes a silicon nitride film layer. 3. The method according to claim 2, wherein the interlayer insulating film is a silicon oxide film. In the step (C), the element isolation patterning film is removed before forming the interlayer insulating film.
3. The method according to claim 1, further comprising the step of exposing a surface of the S transistor region, wherein a silicon oxide film for a gate oxide film of the MOS transistor is simultaneously formed on the surface of the MOS transistor region when the interlayer insulating film is formed. A method for manufacturing a semiconductor device. 4. The patterning film for element isolation, wherein the lower layer is a laminated film of a silicon oxide film and the upper layer is a laminated film of a silicon nitride film, and in the step (C), when the patterning film for element isolation is removed, After removing only the silicon nitride film of the device isolation patterning film, the silicon oxide film of the device isolation patterning film remaining in the MOS transistor region is used as a protective film for impurity implantation for threshold value control. 4. The method according to claim 3, further comprising a step of implanting impurities into the MOS transistor region through a film. 5. The step (D) includes: forming a second polysilicon film for the upper electrode on a semiconductor substrate; introducing an impurity into the second polysilicon film; and patterning the second polysilicon film. Forming a second electrode on the region including the silicon oxide film for the gate oxide film when patterning the second polysilicon film. 5. The method for manufacturing a semiconductor device according to claim 1, wherein said gate electrode pattern is formed. 6. A method for manufacturing a semiconductor device including at least a MOS transistor and a polysilicon-interlayer insulating film-capacitive element having a polysilicon structure on the same substrate by the following steps (A) to (E). A method for manufacturing a semiconductor device, comprising forming a capacitor. (A) An element isolation region is formed using an oxidation-resistant element isolation patterning film having an opening in the element isolation region, covering the MOS transistor region, and removing the element isolation region patterning film. Forming a base film on the transistor region to prevent diffusion of impurities into the MOS transistor region; (B) forming a first polysilicon film for a lower electrode constituting the capacitive element on the semiconductor substrate (C) a step of introducing an impurity into the first polysilicon film and patterning the same to form a lower electrode of the capacitive element on the element isolation region; and (D) forming a lower electrode on the surface of the lower electrode. Forming an interlayer insulating film constituting the capacitive element; and (E) forming an upper electrode of the capacitive element on the lower electrode via the interlayer insulating film. 7. The semiconductor according to claim 6, wherein the base film is any one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a stacked film of a silicon oxide film as a lower layer and a silicon nitride film as an upper layer. Device manufacturing method. 8. The method according to claim 1, wherein the interlayer insulating film is a silicon oxide film. In the step (D), before forming the interlayer insulating film, the base film is removed to expose a surface of the MOS transistor region. 8. The method of manufacturing a semiconductor device according to claim 6, further comprising the step of simultaneously forming a silicon oxide film for a gate oxide film of a MOS transistor on the surface of the MOS transistor region when forming the interlayer insulating film. 9. The base film, wherein the lower layer is a silicon oxide film,
The upper layer is a laminated film of a silicon nitride film, and in the step (D), when the underlying film is removed, after removing only the underlying silicon nitride film, the lower layer remaining in the MOS transistor region is removed. 8. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of implanting an impurity into said MOS transistor region through said silicon oxide film using a silicon oxide film of a ground film as a protective film for impurity implantation for controlling a threshold value. . 10. The method according to claim 1, wherein the step (E) is performed on a semiconductor substrate.
Forming a second polysilicon film for the upper electrode, introducing impurities into the second polysilicon film and patterning the second polysilicon film to form the upper electrode,
When patterning the polysilicon film, the second silicon oxide film is formed on the region including the silicon oxide film for the gate oxide film.
10. The method of manufacturing a semiconductor device according to claim 6, wherein a gate electrode pattern for said MOS transistor is formed of said polysilicon film.