JP2001136738A - Control circuit for switching DC-DC converter - Google Patents

Abstract

(57) [Summary] A set value V of an output DC voltage so that an output DC voltage Vout of a switching DC-DC converter is kept constant.
The difference between ref and the detection value obtained through the resistors R1 and R2 is represented by O
The voltage Vop amplified via the P amplifier 1 and the triangular wave generator 2
The control circuit 010 compares the triangular wave Vosc via the comparator 3 to obtain a gate drive signal Vg via the gate driver 4 and turns on / off the semiconductor switch element Q0 (not shown) which interrupts the input DC voltage. Therefore, the switching frequency is increased without increasing the frequency of the triangular wave generator 2 in which the oscillation becomes unstable due to the delay time at a high frequency, and the magnetic element is downsized. A pulse generator (5) generates two pulse signals (Vp1, Vp2) having different Hi / Lo ratios at a switching frequency higher than the frequency of a triangular wave (Vosc). In response, Vp1 and Vp2 are switched and applied to the gate driver 4 to amplify the current to obtain a gate drive signal Vg.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching DC
-A voltage obtained by amplifying a deviation between a set value and a detection value of the output DC voltage and a triangular wave are compared so that an output DC voltage of a DC converter (abbreviated as a switching power supply) is constant, and the input DC voltage is intermittently switched. A control circuit for a switching power supply for controlling on / off of a semiconductor switching element, in particular, stably oscillating a triangular wave, reducing a loss of a triangular wave generating circuit, and increasing a switching frequency for turning on / off the semiconductor switching element. Even when the switching power supply is of the voltage resonance type or current resonance type in order to reduce the size of the magnetic element and to further reduce the switching loss of the semiconductor switching element, the variable range of the output DC voltage which can be controlled by the switching power supply. Without narrowing
The present invention relates to a switching DC-DC converter control circuit capable of reliably reducing switching loss. In the drawings, the same reference numerals indicate the same or corresponding parts.

[0002]

2. Description of the Related Art FIG. 9 shows a main circuit configuration of a step-down DC-DC converter 101 which is an example of a switching DC-DC converter. In general, a switching DC-DC converter is a semiconductor transistor Q0 (P in this example) which is a switch element that switches an input DC voltage Vin at a predetermined frequency.
A channel MOSFET (hereinafter, referred to as a main switch element), a magnetic element (in this example, a choke coil) L0 for storing energy when the main switch element Q0 is turned on, an output smoothing capacitor Cout, and an output DC voltage Vout are set to be constant. A control circuit 01 for turning on / off the switch element Q0 and the like. The voltage output from a battery or the like, which is taken in as the input DC voltage Vin,
This is a device that converts a constant DC voltage required for driving a load of an electronic device or the like and outputs it as an output DC voltage Vout.

In FIG. 9, Cin is an input capacitor for keeping the input DC voltage Vin smooth, and D0 is a flywheel diode that becomes a flow path of a load current when the main switch element Q0 is turned off. The control circuit 01 outputs the output DC voltage Vou
A control method for driving the main switch element Q0 on / off in order to make t constant is usually PWM (pulse width modulation).
A control method is used.

FIG. 10 shows a circuit of a PWM control IC as a configuration example of a conventional control circuit 01. 11 shows respective voltage waveforms of the output Vop of the OP amplifier 1, the triangular wave Vosc as the output of the triangular wave generator 2, the output Vcmp of the comparator 3, and the gate drive signal Vg as the output of the gate driver 4 in FIG. . FIG. 10 will be described with reference to FIG. 11. The difference voltage (deviation voltage) between the feedback voltage (detection voltage) of the output DC voltage Vout obtained by dividing the output DC voltage Vout via the resistors R1 and R2 and the reference voltage Vref. Is amplified by the OP amplifier 1, the output Vop of the OP amplifier 1 is compared with the output Vosc of the triangular wave generator 2 by the comparator 3, and the comparator 3 outputs a rectangular wave Vcmp having a width corresponding to the fluctuation of the converter output voltage Vout. Is done.

That is, in this embodiment, the converter output voltage Vout
Becomes too large with respect to the set value, the output voltage Vou
Since the feedback voltage of t is input to the (-) input terminal of the OP amplifier 1 and the reference voltage Vref is input to the (+) input terminal of the OP amplifier 1, the output Vop of the OP amplifier decreases. Since the OP amplifier output Vop is input to the (-) input terminal of the comparator 3 and the triangular wave Vosc is input to the (+) input terminal of the comparator 3, when the OP amplifier output Vop decreases, the triangular wave Vosc is output to the OP amplifier output. The period of Hi of the comparator output Vcmp as a period exceeding Vop (the period in which the main switch element Q0 is turned off in this example) increases, and the triangular wave Vos
The period during which the comparator output Vcmp is Lo during the period when c is lower than the OP amplifier output Vop (in this example, the main switching element Q0
(The period during which the power supply is turned on) is reduced, and the output voltage Vout is lowered to return to a normal value.

Conversely, if the converter output voltage Vout attempts to become too small with respect to the set value, the OP amplifier output Vop rises, the Hi period of the comparator output Vcmp (the OFF period of the main switch element) decreases, and Lo The period (the ON period of the main switch element) increases, and the output voltage Vout is increased to return to a normal value. The gate driver 4 uses this Lo / H
A gate drive signal Vg as a signal obtained by current-amplifying the comparator output Vcmp of i is output to the gate of the main switch element Q0, and the main switch element Q0 (in this example, a P-channel MOS
FET) is turned on / off, respectively.

As can be seen from FIG. 11, the frequency of the triangular wave Vosc is equal to the on / off switching frequency of the main switch element Q0, and the pulse width of the gate drive signal Vg, that is, the main switch element Q0, depends on the OP amplifier output Vop.
The on-time (or off-time) of 0 changes, so the on-time ratio [= (on-time) / (switching cycle)]
[Or off-time ratio = (off-time) / (switching cycle)] has changed.

FIG. 12 shows a schematic configuration of a generally used triangular wave generator 2. In the figure, Vdd is the power supply voltage of the triangular wave generator 2, Vref is the reference voltage, VH and V
L is a voltage value obtained by dividing the reference voltage Vref using resistors R11 to R13, and 21 and 22 are capacitors Cos, respectively.
This is a comparator for comparing the voltage across c with the divided voltages VH and VL. IS1 and IS2 are MOSF
The constant current sources SW1 and SW2 are configured by ET and the like, and flow the same current. SW1 and SW2 are switches configured by MOSFETs and the like, respectively.

The operation of FIG. 12 will now be described.
It is assumed that the capacitor Cosc is charged through the constant current source IS1 when W1 is turned on, and the voltage between both ends is increasing. When the voltage across the capacitor Cosc exceeds VH, the output of the comparator 21 becomes Lo and the output of the comparator 22 becomes Hi, so that the output Q of the RS flip-flop 23 becomes Hi,
The switch SW1 is turned off, and the switch SW2 is turned on via the inverter 24. Therefore, the discharge of the capacitor Cosc starts via the constant current source IS2, and the voltage between both ends decreases.

Next, when the voltage between both ends of the capacitor Cosc is VL
When the voltage becomes lower, the output of the comparator 22 becomes Lo and the output of the comparator 21 becomes Hi. Therefore, the output Q of the RS flip-flop 23 becomes Lo, the switch SW1 is turned on, and the switch SW2 is turned off via the inverter 24. Is done. Therefore, charging of the capacitor Cosc starts via the constant current source IS1, and the voltage between both ends increases. In this way, the voltage between both ends of the capacitor Cosc becomes a triangular wave Vosc whose maximum value is VH and whose minimum value is VL.

Next, a description will be given of a resonance type switching DC-DC converter in which a resonance switch circuit is used to reduce the switching loss of the main switch element Q0 of FIG. FIG. 14 shows an example of a main circuit configuration of a voltage-resonant / fall-down switching DC-DC converter 102 as a resonant converter using a half-wave voltage resonant switch circuit 02 which is an example of a typical resonant switch circuit.

Here, the voltage resonance type converter 102 is different from the normal converter 101 shown in FIG. 9 in that a diode D1 is connected in series with the main switch element Q0 in the forward direction, and is connected in parallel with a series circuit of the main switch element Q0 and the diode D1. , A resonance capacitor Cr and a resonance inductance Lr are added in series with the flywheel diode D0.

The half-wave voltage resonance switch circuit 02 comprises a main switch element Q0, a diode D1, a resonance capacitor Cr, a flywheel diode D0, and a resonance inductance Lr. This voltage resonance type converter 102
During the period in which the main switch element Q0 is off, the voltage across the main switch element Q0 is made sinusoidal, and after the voltage reaches 0 V, the main switch element Q0 is turned on to reduce switching loss.

FIG. 15 shows a gate drive signal Vg for driving the gate of the main switch element Q0 of FIG.
The waveforms of the voltage (drain-source voltage) Vds and the current (drain current) Id between the two terminals are shown. Next, the operation of the half-wave voltage resonance switch circuit 02 will be described with reference to FIGS. Here, the P channel M is connected to the main switch element Q0.
The case where an OSFET is used is shown. Therefore, when the gate drive signal Vg is Hi, the main switch element Q0 is turned off. When the gate drive signal Vg is Lo, the main switch element Q0 is turned off.
Turns on. During the off-period of the main switch element Q0, the voltage Vds across the element Q0 becomes sinusoidal due to the resonance between the resonance capacitor (abbreviated as capacitance) Cr and the resonance inductance (abbreviated as coil) Lr.

That is, when the main switch element Q0 is turned off, the choke coil L0 causes the current up to that point (in this case, FIG.
5 (equal to the drain current Id), the capacitor Cr first supplies this current, so that the voltage across the capacitor Cr first increases in the forward direction (positive direction) of the main switch element Q0. When the voltage of the capacitor Cr becomes equal to or higher than the input voltage Vin, the diode D0 also conducts and the coil Lr
Also starts increasing from zero. In this way, the resonance due to Cr and Lr starts, and the voltage of the capacitor Cr changes in a sine-wave shape in which the horizontal axis moves in the positive direction (upward in FIG. 15) by the input voltage Vin.

FIG. 15 shows a period on the positive side of the sine-wave voltage of the capacitor Cr as t1, and a period on the negative side as t2. The period (t1 + t2) = Tres is the cycle of this LC resonance. Here, the voltage on the positive side of the capacitor Cr in the period t1 is applied to the main switch element Q0 and becomes the drain-source voltage Vds, but the voltage on the negative side in the period t2 is blocked by the diode D1. Element Q0
, And the drain-source voltage Vds in FIG.
Are shown by broken lines.

If the time when the main switch element Q0 is turned on next falls within the period t2, the element voltage Vds is already 0 V when the element Q0 is turned on. Therefore, the switching loss when the main switch element Q0 is turned on is 0 W. Becomes FIG.
2 shows an example of the main circuit configuration of the current resonance / down-conversion type switching DC-DC converter 103 using the half-wave current resonance switch circuit 03. Here, the current resonance type converter 103 is different from the converter 101 of FIG.
A forward diode D1 and a resonance inductance Lr are added in series with the flywheel diode D1.
A resonance capacitor Cr is added in parallel with 0.

The half-wave current resonance switch circuit 03 includes a main switch element Q0, a diode D1, a resonance inductance (coil) Lr, a flywheel diode D0,
It consists of a resonance capacitor (capacitance) Cr. This current resonance type converter 103 reduces the switching loss by making the current of the main switching element Q0 a sine wave while the main switching element Q0 is on, and turning off the main switching element Q0 after the current reaches 0A. .

FIG. 18 shows a gate drive signal Vg for driving the gate of the main switch element Q0 of FIG.
(Drain current) Id and voltage (drain-source voltage) Vds at both ends. Next, the operation of the half-wave current resonance switch circuit 03 will be described with reference to FIGS. Again, P-channel M is connected to main switch element Q0.
The case where an OSFET is used is shown. Therefore, when the gate drive signal Vg is Hi, the main switch element Q0 is turned off. When the gate drive signal Vg is Lo, the main switch element Q0 is turned off.
Turns on. Then, during the ON period of the main switch element Q0, the current Id of the element Q0 becomes sinusoidal due to resonance between the capacitor Cr and the coil Lr.

That is, before the main switch element Q0 is turned on, the flywheel diode D0 conducts, and the choke coil L0 maintains the current supplied to the load side. Here, when the main switch element Q0 is turned on, the current of the coil Lr (that is, the current Id of the element Q0) first rises from 0, and when the current of the coil Lr exceeds the sustain current of the choke coil L0, the diode D0 is turned on. Since the capacitor Cr is disconnected and charging of the capacitor Cr starts, resonance by Cr and Lr starts thereafter.

As a result, the current of the coil Lr (that is, the drain current Id of the element Q0) changes as a sinusoidal waveform in which the horizontal axis moves in the positive direction (upward in FIG. 18) by the sustaining current of the choke coil L0. Then, the current flows in the positive direction during the period indicated by t1, but does not flow in the negative direction due to the presence of the diode D1 in series, and remains at 0 during the period indicated by t2.

The period t2 is determined as a period from the end of the period t1 until the capacitor Cr discharges while supplying the sustain current of the choke coil L0, and the voltage of the capacitor Cr becomes equal to the input voltage Vin. However, in FIG. 18, for the sake of convenience, the period t2 is shown as a period of a virtual negative current (broken line) following the positive sinusoidal current in a form corresponding to FIG. Here, the period (t1 + t2) is set to the resonance cycle T
res

Thus, FIG. 18 is different from FIG. 15 in that the drain-source voltage Vds and the drain current I
The waveform of d is replaced, and the sine wave drain current Id flows during the ON period of the main switch element Q0. In FIG. 18 as well, if the time when the main switch element Q0 turns off falls within the period t2, the switching element current Id = 0 A when the main switch element Q0 turns off. The loss is 0W.

Actually, a fixed time determined by a circuit constant or the like obtained by adding a slight margin time to the period t1 (this time can be a predetermined time corresponding to the resonance period Tres = (t1 + t2)). Is the main switching element Q0
(In the case of the voltage resonance type switch circuit) or the ON time (in the case of the current resonance type switch circuit), the switching loss at the time of turning on or turning off the main switching element can be reduced to zero.

[0025]

(Problem 1) By the way,
In the circuit system of the conventional control circuit 01 shown in FIG. 10, when it is desired to increase the switching frequency in order to reduce the size of the switching DC-DC converter, a triangular wave Vosc is used.
It is also necessary to increase the frequency. However, when the frequency of the triangular wave is increased, especially in the MHz band or higher, the delay in the switching timing of the charging and discharging of the capacitor Cosc due to the delay time of the comparators 21 and 22 shown in FIG.

Therefore, as shown in FIG. 13, the maximum voltage Vma of the triangular wave Vosc increases as the frequency (horizontal axis) of the triangular wave increases.
As x increases above VH, the minimum voltage Vmin decreases below VL, and the amplitude Vp-p of the triangular wave Vosc increases.
Thus, in switching in the MHz band, DC-D
There is a problem that the stability of the operation of the C converter is impaired.

In order to avoid this problem, when the switching frequency is several MHz, the delay time of the comparators 21 and 22 may be increased to about 1 ns. There is a problem that current consumption increases. For example, in the comparator manufactured by the CMOS process of the 2 μm rule, the current consumption is about 30 μA when the delay time is 10 ns, whereas the current consumption is about 300 μA when the delay time is 1 ns.

(Problem 2) Next, a problem when the resonance switch circuit shown in FIGS. 14 and 17 is used will be described. FIG.
4, the off-time ratio of the main switch element Q0 is increased by the PWM control.
When the resonance period Tres indicated by the period (t1 + t2) in the period 5 becomes shorter than the off period of the element Q0, the element voltage Vds increases again before the element Q0 is turned on as shown in FIG. Become. Therefore, a switching loss occurs during the turn-on period indicated by T in FIG.

In order to avoid this phenomenon, it is necessary to add a limit circuit for limiting the off-time ratio of the main switching element Q0. At this time, the allowable time of the off-period of the element Q0 is limited. That is, switching D
The controllable variable range of the output voltage Vout of the C-DC converter 102 is reduced. Similarly, in the case of the current resonance type converter of FIG. 17, the ON time ratio of the main switch element Q0 is increased by the PWM control, and the resonance cycle Tres indicated by the period (t1 + t2) in FIG.
When it is shorter than the ON period of 0, as shown in FIG. 19, the switching element current Id increases again before the element Q0 turns off, and Id> 0A at the time of turning off. Therefore, FIG.
Switching loss occurs during the turn-off period indicated by T in FIG.

In order to avoid this phenomenon, it is necessary to add a limit circuit for limiting the ON time ratio of the main switch element Q0, and at this time, the allowable time of the ON period of the element Q0 is limited. That is, switching D
The controllable variable range of the output voltage Vout of the C-DC converter 103 is reduced. The object of the present invention is
The comparator in the triangular wave generator stably generates a triangular wave without speeding up, and prevents an increase in current consumption of the comparator. -When the DC converter is of the resonance type, the turn-on loss of the main switch element is reduced by keeping the off time of the main switch element constant without reducing the controllable variable range of the converter output voltage. In the case of a current resonance type converter, the above problem 2 can be solved by making the ON time of the main switch element constant and making the turn-off loss of the main switch element zero.
An object of the present invention is to provide a control circuit for a C converter.

[0031]

In order to solve the above-mentioned problems, a control circuit for a switching DC-DC converter according to a first aspect of the present invention provides an input direct-current voltage (Vin) via a semiconductor switching element (Q0). Switching D that generates and outputs a stable output DC voltage (Vout) intermittently at a frequency of 1
A control circuit (01) for controlling on / off of the semiconductor switch element in a C-DC converter (101 or the like)
0), wherein the predetermined second frequency is lower than the first frequency.
A triangular wave generating means (triangular wave generator 2) for generating a triangular wave (Vosc) having a predetermined maximum value and a predetermined minimum value at the frequency, and the output DC voltage (voltage dividing resistor R1, R2) with respect to a set voltage (reference voltage Vref). A means (OP amplifier 1) for calculating and amplifying a deviation voltage of the detection feedback voltage (R2 detected by R2), a comparing means (comparator 3) for comparing the level of the calculated amplification value (Vop) of the deviation voltage with the triangular wave, At a first frequency, at least for each of a plurality of predetermined periods, the period of Hi and the period of Lo correspond to one of ON and OFF or OFF and ON of the semiconductor switch element, respectively. Two pulse signals (Vp1 and Vp2, or Vp and its processed signal) having different ratios between the Hi period and the Lo period are generated, and the output DC voltage is likely to be excessive (under) for the set voltage. You When the ratio of the off (on) period of the semiconductor switch element to the two pulse signals is increased during a period on the increasing side in the time series Hi / Lo binary period output from the comparing means. A large pulse signal is selected, and the ratio of the ON (OFF) period of the semiconductor switch element to the two pulse signals is large during the period of decreasing time in the binary period of Hi / Lo in the time series. Drive signal generation means (pulse generator 5, logic circuit 6, gate driver 4, etc.) for selecting a pulse signal (amplifying the current and as a gate drive signal Vg) to drive the semiconductor switch element on / off. Shall be.

A control circuit for a switching DC-DC converter according to a second aspect of the present invention is the control circuit for a switching DC-DC converter according to the first aspect, wherein the switching DC-DC converter (the half-wave voltage resonance switch circuit 02 is connected to the switching circuit). A voltage resonance type (e.g., converter 102) in which a sine-wave-like resonance voltage based on LC resonance (by the resonance inductance Lr and the resonance capacitor Cr) is applied to both ends of the semiconductor switch element during the off-period of the semiconductor switch element. In such a configuration, in the Hi or Lo period of the two pulse signals, the end of the period corresponding to the turning-off of the semiconductor switch element enters a period in which the resonance voltage applied to the semiconductor switch element is zero. The period corresponding to the off state is defined as [resonance cycle Tres = (t
1 + t2)], one or a plurality of predetermined lengths corresponding to one or a plurality of predetermined periods of the LC resonance, and the periods of the plurality of lengths are regularly arranged on the pulse signal in a time-series manner. To be.

Further switching DC-DC converter control circuit according to claim 3 is the switching DC-DC converter control circuit according to claim 2, wherein the drive signal generating means, [logic circuit 6 (6 _{4-6 7} ) The two pulse signals are switched so that the period corresponding to the turning off of the semiconductor switch element is maintained at any of the predetermined lengths.

A control circuit for a switching DC-DC converter according to a fourth aspect of the present invention is the control circuit for a switching DC-DC converter according to the first aspect, wherein the switching DC-DC converter (the half-wave current resonance switch circuit 03 is connected to the switching DC-DC converter). During the ON period of the semiconductor switch element, the semiconductor switch element is configured as a current resonance type (such as the converter 103) in which a sinusoidal resonance current based on the LC resonance (by the resonance inductance Lr and the resonance capacitor Cr) flows. In the Hi or Lo period of the two pulse signals, the end of the period corresponding to the turning on of the semiconductor switching element enters a period in which the resonance current flowing through the semiconductor switching element is absent.
The period corresponding to the ON state is defined as [resonance cycle Tres = (t1 + t
2)] one or a plurality of predetermined lengths corresponding to one or a plurality of predetermined periods of the LC resonance, and the periods of the plurality of lengths are regularly arranged on the pulse signal in a time-series manner. To become.

Further switching DC-DC converter control circuit according to claim 5 is the switching DC-DC converter control circuit according to claim 4, wherein the drive signal generating means, [logic circuit 6 (6 _{4-6 7} ) The two pulse signals are switched so that the period corresponding to the turning on of the semiconductor switch element is maintained at any of the predetermined lengths.

A control circuit for a switching DC-DC converter according to a sixth aspect of the present invention is the control circuit for a switching DC-DC converter according to the first aspect, wherein the pulse generator 5 for the pulse signal Vp and the logic circuit 6 (6 ₂ )), One of the two pulse signals is H
The signal is fixed at i or Lo.

The control circuit for a switching DC-DC converter according to a seventh aspect of the present invention is the control circuit for a switching DC-DC converter according to the first aspect, wherein the pulse generator 5 for the pulse signal Vp and the logic circuit 6 (6 ₃ ) So that one of the two pulse signals is an inverted signal of the other. The control circuit for a switching DC-DC converter according to claim 8 is the control circuit for a switching DC-DC converter according to claim 2 or 3, wherein one of the two pulse signals is turned on of the semiconductor switch element. A corresponding Hi or Lo fixed signal is used.

A control circuit for a switching DC-DC converter according to a ninth aspect is the control circuit for a switching DC-DC converter according to the fourth or fifth aspect, wherein one of the two pulse signals is the semiconductor switch element. Is a fixed signal of Hi or Lo corresponding to the turning off of. A switching DC-DC converter control circuit according to a tenth aspect of the present invention is the switching DC-DC converter control circuit according to any one of the first to fifth aspects, wherein one of the two pulse signals is the other Hi.
Alternatively, the Lo period is maintained at Lo or Hi at predetermined intervals, respectively.

A switching DC-DC according to claim 11
A converter control circuit according to any one of claims 1 to 5, wherein a rising edge or a falling edge of the two pulse signals is synchronized.

The operation of the present invention is as follows. That is, in the invention according to claim 1 (hereinafter referred to as the first invention), the switching DC-D is conventionally used for PWM control.
Gate drive for turning on / off the main switch element by lowering the frequency of the triangular wave, which is compared with a voltage obtained by amplifying the deviation of the output voltage of the C converter from the set value, from on / off driving of the main switch element of the converter Two pulse signals having the same frequency and different Hi / Lo ratios are generated as pulse signals serving as signal original signals, and a comparison result between a voltage obtained by amplifying the deviation and a triangular wave so as to keep the output voltage of the converter constant is obtained. In accordance with / Lo, a predetermined one of the two pulse signals and the other are switched and selected, and a current is amplified and then used as a gate drive signal, so that the frequency of the triangular wave is reduced, thereby delaying the comparator in the triangular wave generator. High-speed drive of the main switch element without affecting the triangular wave generator and reducing the current consumption of the magnetic element. Type conductivity, and therefore the switching DC-
The size of the DC converter can be reduced.

Further, in the invention mainly referred to as claims 2 and 3 (hereinafter referred to as a second invention), the switching DC-D
In the control circuit according to the first invention, a gate drive signal for driving the main switch element is provided so that the C converter is of a voltage resonance type, and the main switch element is turned on during a non-voltage period of the main switch element during the voltage resonance operation. The main switch element is turned off without reducing the controllable variable range of the converter output voltage by keeping the period during which the main switch element is turned off in the two pulse signals serving as the original signals at a predetermined value corresponding to the resonance cycle. In the invention according to claims 4 and 5 (hereinafter referred to as a third invention), the switching DC-DC converter is of a current resonance type, and the main switch element is turned off during current resonance operation. In the control circuit according to the first aspect of the present invention, the main switch is operated during the non-current period of the main switch element. The controllable variable range of the converter output voltage is reduced by keeping the period during which the main switch element is turned on in two pulse signals, which are the original signals of the gate drive signal for driving the switch element, at a predetermined value corresponding to the resonance cycle. Without switching, the switching loss at the time of turning off the main switching element is reduced.

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The above-mentioned problems 1 and 2 are described first with reference to FIG.
And the output of the OP amplifier 1 (that is, the amplified voltage of the deviation from the set value of the converter output voltage Vout) V
The problem is solved by disconnecting the direct connection between the output Vcmp of the comparator 3 for comparing op with the signal Vg for driving the gate of the main switch element Q0.

FIG. 1 shows a schematic configuration of a control circuit 010 applied through the first to third inventions. In FIG.
0, a new logic circuit 6 is inserted between the comparator 3 and the gate driver 4 in addition to the output Vcmp of the comparator 3 and a new pulse generator 5. Output Vp or Vp1, Vp2.

The triangular wave generator 2 of the control circuit 010 has the configuration shown in FIG.
2 is used, the frequency of the output triangular wave Vosc is determined by the comparator 2 in the triangular wave generator 2.
The frequency is set to a low frequency at which the effects of the delay times 1 and 22 do not appear, for example, 1 MHz. In this example, the maximum value Vmax and the minimum value Vmin of the triangular wave Vosc are respectively the reference value V
Let H = 1.5V and VL = 0.5V.

The pulse generator 5 uses a multivibrator or the like to generate an arbitrary frequency higher than the triangular wave Vosc, for example, a 5 MHz pulse wave Vp or Vp1, Vp2.
Is output. The logic circuit 6 determines the output Vcmp of the comparator 3 as H
In accordance with i / Lo, two types of pulse signals Vp1 and Vp2 having different ratios of Hi / Lo periods from the pulse generator 5 are switched and selected, or Hi / Lo generated from one type of pulse signal Vp. And two signals (for example, two pulse signals or a pulse signal and a fixed value signal) having different ratios in each period are switched and selected and output to the gate driver 4.

That is, the main switch element Q0 is connected to the P-channel M
In the case of this example using an OSFET, the comparator output Vcmp is Hi.
Conventionally, each period of / Lo is a period in which the main switch element Q0 is simply turned off / on. However, in the present invention, the logic circuit 6 switches the two signals to be switched during the period when the comparator output Vcmp is Hi. Of the two signals to be switched during the period when the comparator output Vcmp is Lo, a signal having a large ratio of the period during which the main switch element Q0 is turned off is selected. A large signal is selected and given to the gate driver 4. The logic circuit 6 is configured by a gate circuit as described later, and can perform high-speed operation with negligible delay time.

The gate driver 4 current-amplifies the pulse signal input from the logic circuit 6 to generate a gate drive signal Vg, and drives the main switch element Q0 on / off. In this way, in this example, when the converter output voltage Vout is going to be excessive with respect to the set value, the OP amplifier output Vop decreases, and the Hi period of the comparator output Vcmp increases (Lo period decreases). The off period of the main switch element Q0 increases (the on period decreases) and the converter output voltage Vout operates to decrease. Conversely, the converter output voltage Vout tends to be smaller than the set value, and the comparator output Vcmp H
When the i period decreases (Lo period increases), the off period of the main switch element Q0 decreases (the on period increases), and the converter output voltage Vout operates to increase. As a result, the output voltage Vout becomes the set value. Kept close.

The control circuit 010 is connected to any of the switching DC-DC converters 101 to 1 shown in FIGS.
In the following embodiments, the control circuit 010 is connected to the converters 101 to 101 for convenience.
3, the main switch element Q0 will be described as a P-channel MOSFET. In each of the following embodiments, the input voltage Vin of the switching DC-DC converters 101 to 103 is 5 V, the output voltage Vout is 2.5 V, and the input capacitor Cin is 4.7 μm.
F, output capacitor Cout is 2μF, choke coil L
0 is 1 μH.

The main switch element Q0 is connected to an N-channel M
When an OSFET is used, the polarity of the drive signal for turning on / off the main switch element needs to be Hi / Lo. Also, the control circuit 010 of FIG. 1 operates such that the output voltage Vop of the OP amplifier 1 decreases when the converter output voltage Vout is excessively large relative to the set value, and increases when the converter output voltage Vout is excessively small relative to the set value. When the input of the OP amplifier 1 is connected and the triangular wave Vosc is higher than the OP amplifier output Vop, the output Vcmp of the comparator 3 becomes Hi. When the triangular wave Vosc is lower than the OP amplifier output Vop, the comparator output Vcmp. Is connected to the input of the comparator 3 so as to be Lo.

However, even when the connection method is changed, if the converter output voltage Vout becomes excessively large with respect to the set value, the logic circuit 6 correspondingly changes the two signals to be switched (for example, the pulse signal Vp1 and the pulse signal Vp1). Vp2), when the converter output voltage Vout becomes too small with respect to the set value so that the drive period of the main switch element by the signal in which the ratio of the period in which the main switch element is turned off is large is increased. By selecting a signal to be switched so that the drive period of the main switch element is increased by a signal having a large ratio of a period during which the main switch element is turned on of the two signals, the converter output voltage Vout is set to a constant voltage. Can be controlled.

This is true regardless of the circuit type of the switching DC-DC converter: step-down type, step-up type, and step-up / step-down type. [Embodiment 1] First, an embodiment of the first invention in which the control circuit 010 is applied to a normal switching DC-DC converter 101 will be described as "Embodiment 1".

FIGS. 2, 3, and 4 show configuration examples of the logic circuits 6 ₁ , 6 ₂ , and 6 ₃ used in the control circuit 010 in the first embodiment. In FIGS. 2 to 4, OG1 is an OR gate, and AG1 to AG3 are AND gates. (Embodiment 1-1) FIGS. 20 (a) and 20 (b) show signals of respective parts of a control circuit 010 as a first embodiment (referred to as Embodiment 1-1) of the first invention, that is, OP amplifiers. Output Vop, triangular wave Vosc, comparator output Vcmp, pulse generator output Vp1,
The waveforms of Vp2 and the gate drive signal Vg are shown. Here, the logic circuit 6 of FIG.
(6 ₁₎ is used.

In this embodiment, the pulse generator 5 of the control circuit 010 generates two kinds of pulse signals Vp1 and Vp2 having different waveforms, and Vp1 is a pulse in which the ON period of the main switch element Q0 is longer than Vp2. Signal. That is, in the example of FIG. 20, the pulse signals Vp1 and Vp2 have the same frequency Hi /
Signals having different Lo ratios (that is, a ratio between the Hi period and the Lo period) are set as (Lo period of Vp1)> (Lo period of Vp2).

In this embodiment, when the output Vcmp of the comparator 3 is Lo, the logic circuit 6 (6 ₁ ) selects the main switch element Q0 of the two types of pulse signals Vp1 and Vp2 input from the pulse generator 5. The signal Vp1 having a long ON period is supplied to the AND gate AG2.
, And applied to the gate driver 4 via the OR gate OG1. When the comparator output Vcmp is Hi, the pulse signal Vp2 of which the main switch element Q0 has a long OFF period among the pulse signals Vp1 and Vp2 is supplied to the AND gate AG1. Select through
The signal is supplied to the gate driver 4 via the OR gate OG1.

(Embodiment 1-2) FIG. 21 shows a control circuit 0 as a second embodiment (hereinafter referred to as Embodiment 1-2) of the first invention.
The ten main signals, ie, the waveforms of the comparator output Vcmp, the pulse generator output Vp, and the gate drive signal Vg are shown. Is used here logic circuit 6 in FIG. 3 to the logic circuit 6 of the control circuit 010 (6 _2).

As shown in FIG. 21, in this embodiment, the pulse generator 5 of the control circuit 010 generates one kind of pulse signal Vp, and the logic circuit 6 (6 ₂ ) has an OR gate O.
When the comparator output Vcmp is Lo via G1, a pulse signal Vp is supplied to the gate driver 4 and the comparator output Vcmp is output.
Is Hi, the output of Hi is given to the gate driver 4 irrespective of the pulse signal Vp to fix the main switch element Q0 in the off state.

[0057] Further alternatively in this embodiment, the pulse signal generated by the pulse generator 6 of the control circuit 010 in a similar manner to one type of signal Vp, and replace the OR gate OG1 logic circuit 6 ₂ to the AND gate , Comparator output Vcmp
Is high, the replaced AND gate supplies the pulse signal Vp to the gate driver 4, and if the comparator output Vcmp is Lo, the AND gate outputs the output of Lo regardless of the pulse signal Vp. 4 to fix the main switch element Q0 in the ON state.

(Embodiment 1-3) FIG. 22 shows a control circuit 0 as a third embodiment (hereinafter referred to as Embodiment 1-3) of the first invention.
The ten main signals, ie, the waveforms of the comparator output Vcmp, the pulse generator output Vp, and the gate drive signal Vg are shown. Is used here logic circuit 6 of FIG. 4 to the logic circuit 6 of the control circuit 010 (6 _3).

As shown in FIG. 22, in this embodiment, the pulse signal generated by the pulse
p, and the Hi / Lo ratio of the signal Vp is set to a value other than 1. In this example, Lo period> Hi period. Logic circuit 6
(6 ₃ ) indicates that when the comparator output Vcmp is Lo, AN
The pulse signal Vp is selected as it is via the D gate AG2, and applied to the gate driver 4 via the OR gate OG1. On the other hand, when the comparator output Vcmp is Hi, AND
The pulse signal Vp is inverted and selected via the gate AG3 (this inverted signal satisfies Hi period> Lo period in this example), and is supplied to the gate driver 4 via the OR gate OG1.

(Embodiment 1-4) FIG. 23 shows a control circuit 0 as a fourth embodiment (hereinafter referred to as Embodiment 1-4) of the first invention.
The ten main signals, that is, the waveforms of the comparator output Vcmp, pulse generator outputs Vp1, Vp2, and gate drive signal Vg are shown. Here, the logic circuit 6 of the control circuit 010 is shown in FIG.
Of the logic circuit 6 (6 ₁ ).

In the present embodiment, the pulse generator 5
The pulse signal Vp1 shown in FIG. 3 is generated, and then the pulse signal Vp1 is outputted at regular intervals through a counter, a gate element and the like (not shown).
The pulse signal Vp2 is generated with the Lo period of Hi being Hi.
Therefore, the ratio of the pulse signal Vp1 during the Lo period is larger than the ratio of the pulse signal Vp2Lo during the period. Logic circuit 6 (6
₁ ) is the first embodiment when the comparator output Vcmp is Lo.
Similarly to -1, the pulse signal Vp1 is selected and supplied to the gate driver 4, and when the comparator output Vcmp is Hi, the pulse signal Vp2 is selected and supplied to the gate driver 4.

(Embodiment 1-5) FIG. 24 shows a control circuit 0 as a fifth embodiment (hereinafter referred to as Embodiment 1-5) of the first invention.
The ten main signals, that is, the waveforms of the comparator output Vcmp, pulse generator outputs Vp1, Vp2, and gate drive signal Vg are shown. Here, the logic circuit 6 of the control circuit 010 is shown in FIG.
Of the logic circuit 6 (6 ₁ ).

In this embodiment, the pulse generator 5 first operates as shown in FIG.
4 is generated, and then the pulse signal Vp2 is generated at regular intervals through a counter, a gate element, and the like (not shown).
A pulse signal Vp1 in which the period of Hi is set to Lo is generated.
Therefore, the ratio of the pulse signal Vp1 during the Lo period is larger than the ratio of the pulse signal Vp2Lo during the period. Logic circuit 6 (6
₁ ) In the _first embodiment, when the comparator output Vcmp is Lo.
1, the pulse signal Vp1 is selected and the gate driver 4
When the comparator output Vcmp is Hi, the pulse signal Vp2 is selected and supplied to the gate driver 4.

Next, when the switching DC-DC converter for solving the above-mentioned problem 2 is a resonance type converter, the off period of the main switch element Q0 is fixed (in the case of a voltage resonance type converter, the second invention). And a method of fixing the ON period of the main switch element Q0 (in the case of a current resonance type converter, the third invention) will be described. The second problem can also be solved by using the control circuit 010 having the configuration shown in FIG. 1 and devising the waveform of the pulse signal generated by the pulse generator 5 and the configuration of the logic circuit 6.
0 is any switching DC-D using the half-wave voltage resonance switch circuit 02 or the half-wave current resonance switch circuit 03
It can be applied to a C converter.

FIG. 5, FIG. 6, FIG. 7, and FIG.
Logic circuit 6 (6) used in control circuit 010 of the third invention.
_4, 6 _{5, 6} 6, showing a configuration example of a 6 _7). Each of these figures 5
8, OG1 to OG3 are OR gates, AG1 to A
G6 is an AND gate that summarizes NAND gates, FF1
Is an inverting input type RS flip-flop. In this case, two types of pulse signals Vp1 and Vp2 generated by the pulse generator 5 are used as the gate drive signal Vg. Here, too, the pulse signal Vp1 is a pulse signal in which the ratio of the ON period of the main switch element Q0 is larger than that of the pulse signal Vp2.

The on-period and off-period of the pulse signals Vp1 and Vp2 can be adjusted and fixed in accordance with the set resonance time Tres. Since the pulse signal is used to drive the main switch element, The switch element can be turned on without voltage (in the case of a voltage resonance type converter) or turned off without a current (in the case of a current resonance type converter).

Here, each of the logic circuits 6 (6 ₄ , 6 ₅ ,
6 _6, explaining the function of the 6 _7). First, the logic circuit 6 in FIG.
(6 ₄ ) has a configuration in which a flip-flop FF1 and an OR gate OG2 are added to the previous stage of the logic circuit 6 (6 ₁ ) in FIG. In the logic circuit 6 (6 _4), the comparator output Vcm
When p is Lo, the inverting input terminals R and S of the flip-flop FF1 both have the value of the pulse signal Vp2.
From the time when p2 once becomes Lo, the output Q of FF1 becomes Hi.
And the pulse signal Vp1 changes to the AND gate AG1,
The signal is output to the gate driver 4 via the OR gate OG1.

On the other hand, when the comparator output Vcmp is Hi, the inverting input terminal S of the flip-flop FF1 is kept Hi via the OR gate OG2, and the inverting input terminal R of the FF1 has the value of the pulse signal Vp2. , Vp2 once becomes Lo, the output Q of FF1 remains Lo,
The pulse signal Vp2 is supplied to the AND gate AG2 and the OR gate OG.
1 to the gate driver 4.

Accordingly, the logic circuit 6 (6 ₄ ) outputs the pulse signal V immediately after the comparator output Vcmp switches from Hi to Lo.
The pulse signal Vp1 is selected and output from the time when p2 = Lo, and the pulse signal Vp2 is selected and output from the time when the pulse signal Vp2 = Lo immediately after the comparator output Vcmp switches from Lo to Hi. I do. Logic circuit 6 (6 _{5, 6} 6, 6
₇ ) is also the same as 6 (6 ₄ ), but the output of the comparator is normally Vcm.
The pulse signal Vp1 is selected and output when p is Lo, and the pulse signal Vp2 is selected and output when the comparator output Vcmp is Hi. The timings at which the pulse signals Vp1 and Vp2 are switched are as follows. There are differences.

The logic circuit 6 (6 ₅ ) of FIG.
An AND gate AG4 is added before (6 ₄ ), and the output of AG4 is input to the OR gate OG2 instead of the pulse signal Vp2. Here, the output of the AND gate AG4 becomes Lo when both the pulse signals Vp1 and Vp2 are Lo or Hi. Thus the logic circuit 6 (6 ₅₎
Output the pulse signal Vp1 immediately after the comparator output Vcmp has switched from Hi to Lo, and both the pulse signals Vp1 and Vp2 have become Lo or Hi, and the comparator output Vcmp has switched from Lo to Hi. Immediately after pulse signals Vp1, Vp2
From the point when both become Lo or Hi, the pulse signal Vp2
Is output.

[0071] logic circuit 6 (6 ₆₎ of FIG. 7 is a logic circuit 6
AND gate AG4 (6 ₅₎ is configured have been replaced in the OR gate OG3. Here, the output of the OR gate OG3 becomes Lo when the pulse signals Vp1 and Vp2 are both Lo. Thus the logic circuit 6 (6 _6), the pulse signal immediately after the comparator output Vcmp is switched to Lo from Hi Vp1, Vp2
Outputs a pulse signal Vp1 from the time when both become Lo,
Immediately after the comparator output Vcmp switches from Lo to Hi, the pulse signal Vp2 is output from the time when both the pulse signals Vp1 and Vp2 become Lo.

The logic circuit 6 (6 ₇ ) of FIG.
OR gate OG2 the AND gate of the ₍₆ 6) (NAND
(Gate) AG5, and an OR gate OG3 is replaced with an AND gate (NAND gate) AG6. Here, the logical function of the AND gate AG5 is equivalent to that of the OR gate OG2, and the output of the AND gate AG6 becomes Lo when the pulse signals Vp1 and Vp2 are both Hi.

Accordingly, the logic circuit 6 (6 ₇ ) outputs the pulse signal V immediately after the comparator output Vcmp switches from Hi to Lo.
The pulse signal Vp1 is output from the time when both p1 and Vp2 become Hi, and the pulse signal Vp2 is output from the time when both the pulse signals Vp1 and Vp2 become Hi immediately after the comparator output Vcmp switches from Lo to Hi. I do. [Embodiment 2] Next, a second embodiment in which the control circuit 010 is applied to a voltage resonance type switching DC-DC converter 102 will be described.
An example of the invention will be described as “Embodiment 2”.

(Embodiment 2-1) FIG. 25 shows a first embodiment of the second invention.
Control circuit 01 as an example (hereinafter referred to as Example 2-1)
It is a waveform diagram which shows the main signal of each part of 0. 2A and 2B show two types of pulse signals Vp1 and Vp2 generated by a pulse generator 5, and these pulse signals are supplied to a gate driver 4 via a logic circuit 6 to provide a main switch. The waveform of the voltage Vds across the main switch element Q0 corresponding to each of the pulse signals Vp1 and Vp2 when the element Q0 is driven is shown. This is the logic circuit 6 of the control circuit 010 can use any of the aforementioned logic circuit 6 (6 _{4-6 7).}

In the present embodiment, the pulse generator 5 first generates the pulse signal Vp2, and further sets the pulse signal Vp2 to Hi at a predetermined period using a counter and a gate circuit (not shown). Vp1 is generated, and pulse signals Vp1 and Vp2 are given to the logic circuit 6 concerned. FIG.
As shown in the waveforms of the voltage Vds across the main switch element in (a) and (b), since the Hi period of the pulse signals Vp1 and Vp2 is constant, if this time is THi, the time t1 and the time t1 described in FIG. It is easy to set t2 to t1 <THi <Tres, where Tres: resonance cycle = (t1 + t2), and to prevent switching loss at turn-on by performing turn-on during the no-voltage period of the main switch element Q0. Can be.

FIG. 25C shows Hi, of the comparator output Vcmp.
FIG. 9 is an explanatory diagram of the timing at which the logic circuit 6 switches the pulse signals Vp1 and Vp2 shown in FIGS. That is, when the pulse signals Vp1 = Lo and Vp2 = Hi, the comparator output Vcmp changes from Lo to Hi or from Hi to L.
o, the pulse signal Vp1
And Vp2, the Hi period in the gate drive signal deviates from the set period like the signals in the periods ta and tb in the gate drive signal Vg '.

[0077] However, this problem is, the logic circuit 6 (6 _4-6
7 ) Can be avoided by using either of them. That is, the logic circuit 6
When (6 ₄ , 6 ₅ , 6 ₆ ) is used, the comparator output Vcmp changes from Lo to Hi or from Hi to Lo, as described above.
Pulse signal Vp1 = Lo, Vp2 = Lo immediately after switching to
Once tc1, tc2 became, in the case of using the logic circuit 6 (6 _7), likewise a pulse signal Vp1 = Hi, Vp2 = time becomes Hi tc1 ', tc2' since the Vp1 and Vp2 switching at The shift of the Hi period in the gate drive signal can be prevented like the gate drive signal Vg shown below the gate drive signal Vg ′.

As an extreme case of the present embodiment, the pulse signal Vp1 may be a fixed Lo signal.
In this case, any one of 6 ₄ , 6 ₅ , and 6 ₆ must be used for the logic circuit 6. (Embodiment 2-2) FIG. 26 is a waveform diagram showing main signals of respective parts of a control circuit 010 according to a second embodiment (referred to as Embodiment 2-2) of the second invention. 2A and 2B show two types of pulse signals Vp1 and Vp2 generated by a pulse generator 5, and these pulse signals are supplied to a gate driver 4 via a logic circuit 6 to provide a main switch. Pulse signals Vp1 and Vp2 when driving element Q0
The voltage Vds between both ends of the corresponding main switch element Q0
3 shows the waveforms of FIG. To the logic circuit 6 of the control circuit 010 can use any of the logic circuit 6 above (6 _{4-6 7).}

In the present embodiment, the pulse generator 5 first generates the pulse signal Vp1, and further sets the pulse signal Vp1 to a high level at regular intervals using a counter and a gate circuit (not shown). Vp2 is generated, and pulse signals Vp1 and Vp2 are given to the logic circuit 6 concerned. FIG.
As shown in the waveforms of the voltage Vds across the main switch element in (a) and (b), the Hi period of the pulse signal Vp1 is represented by THi, Lo
Is defined as TLo, times t1 and t2 in FIG.
To t1 <THi <Tres, (2t1 + t2) <(2THi
+ TLo) <2Tres, where Tres: resonance period = (t1
+ T2)], a sinusoidal resonance voltage waveform for one peak is included in the Hi period of the time width THi on the pulse signals Vp1 and Vp2, and the time width on the pulse signal Vp2 (2Thi + TLo). In the Hi period, a sinusoidal resonance voltage waveform is included in two peaks in a manner of continuing the resonance. However, even if the main switch element is driven by any of the pulse signals Vp1 and Vp2, the main switch element Q0 Turn-on can be performed during a non-voltage period.

FIG. 26C shows Hi, of the comparator output Vcmp.
FIG. 9 is an explanatory diagram of the timing at which the logic circuit 6 switches the pulse signals Vp1 and Vp2 shown in FIGS. That is, when the pulse signals Vp1 = Lo and Vp2 = Hi, the comparator output Vcmp changes from Lo to Hi or from Hi to L.
o, the pulse signal Vp1
And Vp2, the Hi period in the gate drive signal deviates from the set period like the signals in the periods ta and tb in the gate drive signal Vg '.

[0081] However, this problem is, the logic circuit 6 (6 _4-6
7 ) Can be avoided by using either of them. That is, the logic circuit 6
When (6 ₅ , 6 ₇ ) is used, the pulse signal Vp1 = Hi, Vp2 = Hi immediately after the comparator output Vcmp switches from Lo to Hi or from Hi to Lo as described above. When the logic circuit 6 (6 ₄ , 6 ₆ ) is used at tc1 and tc2, Vp1 and Vp2 are switched at time tc1 ′ and tc2 ′ when the pulse signals Vp1 = Lo and Vp2 = Lo. As in the gate drive signal Vg shown below the gate drive signal Vg ′, it is possible to prevent a shift in the Hi period in the gate drive signal.

(Embodiment 2-3) FIG. 27 shows a third embodiment of the second invention.
Control circuit 01 as an example (hereinafter referred to as Example 2-3)
It is a waveform diagram which shows the main signal of each part of 0. 2A and 2B show two types of pulse signals Vp1 and Vp2 generated by a pulse generator 5, and these pulse signals are supplied to a gate driver 4 via a logic circuit 6 to provide a main switch. The waveform of the voltage Vds across the main switch element Q0 corresponding to each of the pulse signals Vp1 and Vp2 when the element Q0 is driven is shown. The above-described logic circuit 6 ( ₆₆ ) is used as the logic circuit 6 of the control circuit 010.

As shown in FIGS. 27A and 27B, in this embodiment, the pulse signals Vp1 and Vp2 have the same frequency Hi /
Signals with different Lo ratios, (Lo period of Vp1)> (Lo period of Vp2). As shown in the waveforms of the voltage Vds across the main switch element in FIGS. 27A and 27B, the Hi period of the pulse signal Vp1 is THi1, and the Hi period of the pulse signal Vp2 is Hi.
Is defined as THi2, the times t1 and t2 in FIG. 15 are defined as t1 <THi1 <Tres and t1 <THi2 <Tres.
[Where Tres: resonance cycle = (t1 + t2)], the main switch element Q0 is turned on during the non-voltage period even if the main switch element Q0 is driven by any of the pulse signals Vp1 and Vp2. be able to.

[0084] Figure 27 (c1), (c2) , (c3) is Hi comparator output Vcmp, in switched point of Lo, the logic circuit 6 (6 ₆₎ of the drawing (a), shown in (b) FIG. 7 is an explanatory diagram of timings at which the pulse signals Vp1 and Vp2 are switched and given to the gate driver 4. That is, the pulse signal Vp1 = Lo, V
When p2 = Hi (see FIG. 27 (c1)), or when Vp1 =
At the time when Hi, Vp2 = Lo (see FIG. 27 (c2)) or at the time when Vp1 = Hi, Vp2 = Hi (see FIG. 27 (c3)), the comparator output Vcmp changes from Lo to Hi or Hi.
When the pulse signals Vp1 and Vp2 are switched immediately at this point in time when the pulse signal is switched from Lo to Lo, each of the diagrams (c1), (c2),
The Hi period in the gate drive signal deviates from the set period like the signals in the periods ta and tb in the gate drive signal Vg 'in (c3).

However, this problem can be avoided by using the logic circuit 6 ( ₆₆ ). That is, by switching between Vp1 and Vp2 at the time point of the pulse signal Vp1 = Lo and Vp2 = Lo immediately after the comparator output Vcmp is switched from Lo to Hi or from Hi to Lo, each of FIGS. (C2), (c
It is possible to prevent the Hi period in the gate drive signal from being shifted as in the gate drive signal Vg shown below the gate drive signal Vg 'in 3).

(Embodiment 2-4) FIG. 28 shows a fourth embodiment of the second invention.
Control circuit 01 as an embodiment (hereinafter referred to as embodiment 2-4)
It is a waveform diagram which shows the main signal of each part of 0. 2A and 2B show two types of pulse signals Vp1 and Vp2 generated by a pulse generator 5, and these pulse signals are supplied to a gate driver 4 via a logic circuit 6 to provide a main switch. The waveform of the voltage Vds across the main switch element Q0 corresponding to each of the pulse signals Vp1 and Vp2 when the element Q0 is driven is shown. To the logic circuit 6 of the control circuit 010 can use any of the logic circuit 6 above (6 _{4-6 7).}

In this embodiment, as shown in FIGS. 28A and 28B, the pulse signals Vp1 and Vp2 have the same frequency Hi /
This is a signal having different Lo ratios and further synchronized with rising edges. Then (Lo period of Vp1)> (Lo period of Vp2)
Period). As shown in the waveforms of the voltage Vds across the main switch element in FIGS. 28 (a) and (b), the pulse signal Vp1
15 is THi1 and the Hi period of the pulse signal Vp2 is THi2, the times t1 and t2 in FIG.
Where t1 <THi1 <Tres, t1 <THi2 <Tres,
By setting [Tres: resonance cycle = (t1 + t2)], even if the main switch element is driven by any one of the pulse signals Vp1 and Vp2, it is possible to turn on during the non-voltage period of the main switch element Q0. it can.

FIG. 28 (c) shows Hi, of the comparator output Vcmp.
FIG. 9 is an explanatory diagram of the timing at which the logic circuit 6 switches the pulse signals Vp1 and Vp2 shown in FIGS. That is, when the pulse signals Vp1 = Lo and Vp2 = Hi, the comparator output Vcmp changes from Lo to Hi or from Hi to L.
o, the pulse signal Vp1
And Vp2, the Hi period in the gate drive signal deviates from the set period like the signals in the periods ta and tb in the gate drive signal Vg '.

[0089] Also this problem can be avoided using any of the logic circuit 6 (6 _{4-6 7).} That is, the logic circuit 6
When (6 ₄ , 6 ₅ , 6 ₆ ) is used, the comparator output Vcmp changes from Lo to Hi or from Hi to Lo, as described above.
Pulse signal Vp1 = Lo, Vp2 = Lo immediately after switching to
Once tc1, tc2 became, in the case of using the logic circuit 6 (6 _7), likewise a pulse signal Vp1 = Hi, Vp2 = time becomes Hi tc1 ', tc2' since the Vp1 and Vp2 switching at The shift of the Hi period in the gate drive signal can be prevented like the gate drive signal Vg shown below the gate drive signal Vg ′.

(Embodiment 2-5) FIG. 29 shows a fifth embodiment of the second invention.
Control circuit 01 as an example (hereinafter referred to as Example 2-5)
It is a waveform diagram which shows the main signal of each part of 0. 2A and 2B show two types of pulse signals Vp1 and Vp2 generated by a pulse generator 5, and these pulse signals are supplied to a gate driver 4 via a logic circuit 6 to provide a main switch. The waveform of the voltage Vds across the main switch element Q0 corresponding to each of the pulse signals Vp1 and Vp2 when the element Q0 is driven is shown. To the logic circuit 6 of the control circuit 010 can use any of the logic circuit 6 above (6 _{4-6 7).}

In this embodiment, as shown in FIGS. 29A and 29B, the pulse signals Vp1 and Vp2 have the same frequency Hi /
This is a signal having different Lo ratios and further synchronized with falling edges. Then (Lo period of Vp1)> (Lo period of Vp2)
Period). As shown in the waveforms of the voltage Vds across the main switch element in FIGS. 29A and 29B, the pulse signal Vp1
15 is THi1 and the Hi period of the pulse signal Vp2 is THi2, the times t1 and t2 in FIG.
Where t1 <THi1 <Tres, t1 <THi2 <Tres,
By setting [Tres: resonance cycle = (t1 + t2)], even if the main switch element is driven by any of the pulse signals Vp1 and Vp2, it is possible to turn on the main switch element Q0 during the non-voltage period. it can.

FIG. 29 (c) shows Hi, of the comparator output Vcmp.
FIG. 9 is an explanatory diagram of the timing at which the logic circuit 6 switches the pulse signals Vp1 and Vp2 shown in FIGS. That is, when the pulse signals Vp1 = Lo and Vp2 = Hi, the comparator output Vcmp changes from Lo to Hi or from Hi to L.
o, the pulse signal Vp1
When the input of the gate drive signal Vp2 to the gate driver 4 is switched, the Hi period in the gate drive signal is shifted from the set period like the signals in the periods ta and tb in the gate drive signal Vg '.

[0093] Also this problem can be avoided using any of the logic circuit 6 (6 _{4-6 7).} That is, the logic circuit 6
When (6 ₅ , 6 ₇ ) is used, the pulse signal Vp1 = Hi, Vp2 = Hi immediately after the comparator output Vcmp switches from Lo to Hi or from Hi to Lo as described above. When the logic circuit 6 (6 ₄ , 6 ₆ ) is used at tc1 and tc2, Vp1 and Vp2 are switched at time tc1 ′ and tc2 ′ when the pulse signals Vp1 = Lo and Vp2 = Lo. As in the gate drive signal Vg shown below the gate drive signal Vg ′, it is possible to prevent a shift in the Hi period in the gate drive signal.

[Embodiment 3] Next, an embodiment of the third invention in which the control circuit 010 is applied to the current resonance type switching DC-DC converter 103 will be described as "Embodiment 3". (Embodiment 3-1) FIG. 30 is a waveform diagram showing main signals of respective parts of a control circuit 010 as a first embodiment (hereinafter referred to as Embodiment 3-1) of the third invention. 2A and 2B show two types of pulse signals Vp1 and Vp2 generated by a pulse generator 5, and these pulse signals are supplied to a gate driver 4 via a logic circuit 6 to provide a main switch. Pulse signals Vp1 and Vp2 when driving element Q0
The waveform of the current Id of the main switch element Q0 corresponding to each is shown. To the logic circuit 6 of the control circuit 010 can use any of the logic circuit 6 above (6 _{4-6 7).}

In the present embodiment, the pulse generator 5 first generates the pulse signal Vp1, and further sets the pulse signal Vp1 to a high level at regular intervals using a counter and a gate circuit (not shown). Vp2 is generated, and pulse signals Vp1 and Vp2 are given to the logic circuit 6 concerned. FIG.
As shown in the waveforms of the main switch element current Id in FIGS. 18A and 18B, the Lo period of the pulse signals Vp1 and Vp2 is constant. If this period is TLo, the time t1 and the time t1 described in FIG. Let t2 be t1 <TLo <Tres, where T1
res: resonance cycle = (t1 + t2)], and the switching loss at the time of turn-off can be prevented by turning off the main switch element Q0 during the non-current period.

FIG. 30 (c) shows Hi, of the comparator output Vcmp.
FIG. 9 is an explanatory diagram of the timing at which the logic circuit 6 switches the pulse signals Vp1 and Vp2 shown in FIGS. That is, when the pulse signals Vp1 = Lo and Vp2 = Hi, the comparator output Vcmp changes from Lo to Hi or from Hi to L.
o, the pulse signal Vp1
And Vp2, the Lo period in the gate drive signal deviates from the set period like the signals in periods ta and tb in the gate drive signal Vg '.

[0097] Also this problem can be avoided using any of the logic circuit 6 (6 _{4-6 7).} That is, the logic circuit 6
When (6 ₅ , 6 ₇ ) is used, the pulse signal Vp1 = Hi, Vp2 = Hi immediately after the comparator output Vcmp switches from Lo to Hi or from Hi to Lo as described above. When the logic circuit 6 (6 ₄ , 6 ₆ ) is used at tc1 and tc2, Vp1 and Vp2 are switched at time tc1 ′ and tc2 ′ when the pulse signals Vp1 = Lo and Vp2 = Lo. As in the gate drive signal Vg shown below the gate drive signal Vg ′, it is possible to prevent a shift in the period of Lo in the gate drive signal.

In the extreme case of the present embodiment, the pulse signal Vp2 may be a fixed Hi signal.
In this case, the logic circuit 6 6 _5, 6 ₇ it is necessary to use either. (Embodiment 3-2) FIG. 31 is a waveform diagram showing main signals of respective parts of a control circuit 010 as a second embodiment (hereinafter referred to as Embodiment 3-2) of the third invention. 2A and 2B show two types of pulse signals Vp1 and Vp2 generated by a pulse generator 5, and these pulse signals are supplied to a gate driver 4 via a logic circuit 6 to provide a main switch. When the element Q0 is driven, the pulse signals Vp1 and Vp2
The waveform of the current Id of the main switch element Q0 corresponding to each is shown. To the logic circuit 6 of the control circuit 010 can use any of the logic circuit 6 above (6 _{4-6 7).}

In this embodiment, the pulse generator 5 first generates the pulse signal Vp2, and further sets the pulse signal Vp2 to Hi at a predetermined period by using a counter and a gate circuit (not shown). Vp1 is generated, and pulse signals Vp1 and Vp2 are given to the logic circuit 6 concerned. FIG.
As shown in the waveforms of the main switch element current Id in FIGS. 18A and 18B, assuming that the Hi period of the pulse signal Vp2 is THi and the Lo period is TLo, the times t1 and t2 in FIG.
t1 <TLo <Tres, (2t1 + t2) <(THi + 2T
Lo) <2Tres, [where Tres: resonance period = (t1 + t)
2)], the pulse signal V
One sinusoidal resonance current waveform enters the Lo period of the time width TLo on p1 and Vp2, and a sinusoidal resonance current waveform resonates during the Lo period of the time width (Thi + 2TLo) on the pulse signal Vp1. , But the main switch element is driven by any of the pulse signals Vp1 and Vp2, so that the main switch element Q0 can be turned off during the non-current period.

FIG. 31 (c) shows Hi, of the comparator output Vcmp.
FIG. 9 is an explanatory diagram of the timing at which the logic circuit 6 switches the pulse signals Vp1 and Vp2 shown in FIGS. That is, when the output Vcmp of the comparator 3 switches from Lo to Hi or from Hi to Lo at the time of the pulse signals Vp1 = Lo and Vp2 = Hi, the pulse signal Vp1 and the gate driver 4 of Vp2 are immediately transmitted to the gate driver 4 at this time. Switching the input of
The Lo period in the gate drive signal deviates from the set period like the signals in the periods ta and tb in the gate drive signal Vg ′.

[0102] Also this problem can be avoided using any of the logic circuit 6 (6 _{4-6 7).} That is, the logic circuit 6
When (6 ₄ , 6 ₅ , 6 ₆ ) is used, the comparator output Vcmp changes from Lo to Hi or from Hi to Lo, as described above.
Pulse signal Vp1 = Lo, Vp2 = Lo immediately after switching to
Once tc1, tc2 became, in the case of using the logic circuit 6 (6 _7), likewise a pulse signal Vp1 = Hi, Vp2 = time becomes Hi tc1 ', tc2' since the Vp1 and Vp2 switching at The shift of the period of Lo in the gate drive signal can be prevented like the gate drive signal Vg shown below the gate drive signal Vg ′.

(Embodiment 3-3) FIG. 32 shows a third embodiment of the third invention.
Control circuit 01 as an example (hereinafter referred to as Example 3-3)
It is a waveform diagram which shows the main signal of each part of 0. 2A and 2B show two types of pulse signals Vp1 and Vp2 generated by a pulse generator 5, and these pulse signals are supplied to a gate driver 4 via a logic circuit 6 to provide a main switch. The waveform of the current Id of the main switch element Q0 corresponding to each of the pulse signals Vp1 and Vp2 when the element Q0 is driven is shown. The logic circuit 6 of the control circuit 010
Use the logic circuit 6 ( ₆₇ ).

As shown in FIGS. 32A and 32B, in this embodiment, the pulse signals Vp1 and Vp2 have the same frequency Hi /
Signals with different Lo ratios, (Lo period of Vp1)> (Lo period of Vp2). As shown in the waveforms of the main switch element current Id in FIGS. 32 (a) and (b), the pulse signal Vp1
If the Lo period of the pulse signal Vp2 is TLo2 and the Lo period of the pulse signal Vp2 is TLo2, the times t1 and t2 in FIG.
, T1 <TLo1 <Tres, t1 <TLo2 <Tres,
By setting [Tres: resonance cycle = (t1 + t2)], even if the main switch element Q0 is driven by either of the pulse signals Vp1 and Vp2, the main switch element Q0 is driven.
The turn-off can be performed during the zero currentless period.

[0104] Figure 32 (c1), (c2) , (c3) is Hi comparator output Vcmp, in switched point of Lo, the logic circuit 6 (6 ₇₎ FIG. (A), shown in (b) FIG. 7 is an explanatory diagram of timings at which the pulse signals Vp1 and Vp2 are switched and given to the gate driver 4. That is, the pulse signal Vp1 = Lo, V
When p2 = Hi (see FIG. 32 (c1)), or when Vp1 =
When Hi, Vp2 = Lo (see FIG. 32 (c2)), or when Vp1 = Lo, Vp2 = Lo (see FIG. 32 (c3)), the comparator output Vcmp changes from Lo to Hi or Hi.
When the pulse signal Vp1 and the input of the pulse signal Vp2 to the gate driver 4 are immediately switched at this time, the period within the gate drive signal Vg 'in each of FIGS. (C1), (c2), and (c3) is changed. Like the signals ta and tb, the period of Lo in the gate drive signal is shifted from the set period.

However, this problem can be avoided by using the logic circuit 6 (6 ₇ ). That is, at the time when the pulse signal Vp1 = Hi and Vp2 = Hi immediately after the comparator output Vcmp switches from Lo to Hi or from Hi to Lo.
By switching between p1 and Vp2, each figure (c) in FIG.
1), (c2) and (c3) gate drive signals Vg ′
The shift of the period of Lo in the gate drive signal can be prevented like the gate drive signal Vg shown below.

(Embodiment 3-4) FIG. 33 shows a fourth embodiment of the third invention.
Control circuit 01 as an embodiment (hereinafter referred to as embodiment 3-4)
It is a waveform diagram which shows the main signal of each part of 0. 2A and 2B show two types of pulse signals Vp1 and Vp2 generated by a pulse generator 5, and these pulse signals are supplied to a gate driver 4 via a logic circuit 6 to provide a main switch. The waveform of the current Id of the main switch element Q0 corresponding to each of the pulse signals Vp1 and Vp2 when the element Q0 is driven is shown. The logic circuit 6 of the control circuit 010
It can be used any of the logic circuit 6 above (6 _{4-6 7).}

In this embodiment, as shown in FIGS. 33A and 33B, the pulse signals Vp1 and Vp2 have the same frequency Hi /
This is a signal having different Lo ratios and further synchronized with rising edges. Then (Lo period of Vp1)> (Lo period of Vp2)
Period). As shown in the waveforms of the main switch element current Id in FIGS. 33A and 33B, the L level of the pulse signal Vp1 is low.
Assuming that the period of o is TLo1 and the period of Lo of the pulse signal Vp2 is TLo2, the times t1 and t2 in FIG.
1 <TLo1 <Tres, t1 <TLo2 <Tres, where Tr
es: resonance period = (t1 + t2)], even if the main switch element Q0 is driven by any of the pulse signals Vp1 and Vp2, the main switch element Q0 can be turned off during the non-current period. .

FIG. 33 (c) shows Hi, of the comparator output Vcmp.
FIG. 9 is an explanatory diagram of the timing at which the logic circuit 6 switches the pulse signals Vp1 and Vp2 shown in FIGS. That is, when the output Vcmp of the comparator 3 switches from Lo to Hi or from Hi to Lo at the time of the pulse signals Vp1 = Lo and Vp2 = Hi, if the pulse signals Vp1 and Vp2 are immediately switched at this time, the gate The Lo period in the gate drive signal deviates from the set period like the signals in the periods ta and tb in the drive signal Vg ′.

[0109] Also this problem can be avoided using any of the logic circuit 6 (6 _{4-6 7).} That is, the logic circuit 6
When (6 ₄ , 6 ₅ , 6 ₆ ) is used, the comparator output Vcmp changes from Lo to Hi or from Hi to Lo, as described above.
Pulse signal Vp1 = Lo, Vp2 = Lo immediately after switching to
Once tc1, tc2 became, in the case of using the logic circuit 6 (6 _7), likewise a pulse signal Vp1 = Hi, Vp2 = time becomes Hi tc1 ', tc2' since the Vp1 and Vp2 switching at The shift of the period of Lo in the gate drive signal can be prevented like the gate drive signal Vg shown below the gate drive signal Vg ′.

(Embodiment 3-5) FIG. 34 shows a fifth embodiment of the third invention.
Control circuit 01 as an example (hereinafter referred to as Example 3-5)
It is a waveform diagram which shows the main signal of each part of 0. 2A and 2B show two types of pulse signals Vp1 and Vp2 generated by a pulse generator 5, and these pulse signals are supplied to a gate driver 4 via a logic circuit 6 to provide a main switch. The waveform of the current Id of the main switch element Q0 corresponding to each of the pulse signals Vp1 and Vp2 when the element Q0 is driven is shown. The logic circuit 6 of the control circuit 010
It can be used any of the logic circuit 6 above (6 _{4-6 7).}

In this embodiment, as shown in FIGS. 34A and 34B, the pulse signals Vp1 and Vp2 have the same frequency Hi /
This is a signal having different Lo ratios and further synchronized with falling edges. Then (Lo period of Vp1)> (Lo period of Vp2)
Period). As shown in the waveforms of the main switch element current Id in FIGS. 34A and 34B, the L level of the pulse signal Vp1 is low.
Assuming that the period of o is TLo1 and the period of Lo of the pulse signal Vp2 is TLo2, the times t1 and t2 in FIG.
1 <TLo1 <Tres, t1 <TLo2 <Tres, where Tr
es: resonance cycle = (t1 + t2)], the main switch element can be turned off during the non-current period of the main switch element Q0, regardless of which of the pulse signals Vp1 and Vp2 drives the main switch element.

FIG. 34 (c) shows Hi, of the comparator output Vcmp.
FIG. 9 is an explanatory diagram of the timing at which the logic circuit 6 switches the pulse signals Vp1 and Vp2 shown in FIGS. That is, when the output Vcmp of the comparator 3 switches from Lo to Hi or from Hi to Lo at the time of the pulse signals Vp1 = Lo and Vp2 = Hi, if the pulse signals Vp1 and Vp2 are immediately switched at this time, the gate The Lo period in the gate drive signal deviates from the set period like the signals in the periods ta and tb in the drive signal Vg ′.

[0113] Also this problem can be avoided using any of the logic circuit 6 (6 _{4-6 7).} That is, the logic circuit 6
When (6 ₅ , 6 ₇ ) is used, the pulse signal Vp1 = Hi, Vp2 = Hi immediately after the comparator output Vcmp switches from Lo to Hi or from Hi to Lo as described above. When the logic circuit 6 (6 ₄ , 6 ₆ ) is used at tc1 and tc2, Vp1 and Vp2 are switched at time tc1 ′ and tc2 ′ when the pulse signals Vp1 = Lo and Vp2 = Lo. As in the gate drive signal Vg shown below the gate drive signal Vg ′, it is possible to prevent a shift in the period of Lo in the gate drive signal.

[0114]

According to the first aspect of the present invention, the frequency of the triangular wave, which is compared with the amplified voltage of the deviation from the set value of the output voltage of the switching DC-DC converter for PWM control, is turned on / off by turning the main switch element of the converter on / off. Two pulse signals having the same frequency and different Hi / Lo ratios are generated as pulse signals serving as original signals of a gate drive signal for turning on / off the main switch element by making the switching frequency lower than the switching frequency for off driving, and the output voltage of the converter. In accordance with Hi / Lo of the comparison result between the amplified voltage of the deviation and the triangular wave, a predetermined one of the two pulse signals and the other of the two pulse signals are switched and selected to amplify the current, and the gate drive signal and Therefore, the lower frequency of the triangular wave reduces the frequency of the triangular wave without affecting the delay of the comparator in the triangular wave generator. Eve becomes possible, current consumption can be reduced in the triangular wave generator with can maintain the stability of the triangular wave, further miniaturization of the magnetic element according to faster switching, thus enabling miniaturization of the switching DC-DC converter.

Further, in order to maintain the output voltage constant, the control of switching the output voltage between the rising side and the falling side (that is, switching and selecting two pulse signals) uses a triangular wave as in the conventional case. In addition, stable control can be performed even with excessive disturbance, and the same level of suppression capability against malfunction as in the conventional circuit system can be secured. For example, when the switching frequency is 5 MHz, the current consumption of the triangular wave generator can be reduced to 1/5 of that of the conventional circuit by setting the frequency of the triangular wave to 1/5 of the switching frequency. Consumption current of 350 mA for a total of 2 mA
μA could be reduced.

According to the second invention, the switching DC
The DC converter is of a voltage resonance type, and the original signal of the gate drive signal for driving the main switch element in the first invention is so set that the turn-on of the main switch element is performed during the non-voltage period of the main switch element during the voltage resonance operation. Since the period during which the main switch element of the two pulse signals is turned off is kept at a predetermined value corresponding to the resonance cycle, it is possible to reliably reduce the switching loss when the main switch element is turned on.

According to the third invention, the switching DC
The DC converter is of a current resonance type, and the original signal of the gate drive signal for driving the main switch element according to the first invention is such that the turn-off of the main switch element is performed during the non-current period of the main switch element during the current resonance operation. Since the period during which the main switch element of the two pulse signals is turned on is kept at a predetermined value corresponding to the resonance cycle, it is possible to reliably reduce the switching loss when the main switch element is turned off.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of a control circuit as an embodiment of the first to third inventions;

FIG. 2 is a diagram showing a first embodiment of a logic circuit used for the control circuit of the first invention;

FIG. 3 is a diagram showing a second embodiment of the logic circuit used in the control circuit of the first invention;

FIG. 4 is a diagram showing a third embodiment of the logic circuit used in the control circuit of the first invention;

FIG. 5 is a diagram showing a first embodiment of a logic circuit used in the control circuits of the second and third inventions;

FIG. 6 is a diagram showing a second embodiment of the logic circuit used in the control circuits of the second and third inventions;

FIG. 7 is a diagram showing a third embodiment of the logic circuit used for the control circuits of the second and third inventions;

FIG. 8 is a diagram showing a fourth embodiment of the logic circuit used in the control circuits of the second and third inventions;

FIG. 9 is a diagram showing an example of a main circuit configuration of a step-down switching DC-DC converter.

FIG. 10 is a configuration diagram of a conventional control circuit.

FIG. 11 is a waveform chart for explaining the operation of FIG. 10;

FIG. 12 is a diagram showing a basic configuration of a triangular wave generator in a control circuit.

FIG. 13 is a characteristic diagram showing a change in a triangular wave output voltage when the frequency of the triangular wave increases.

FIG. 14 is a diagram illustrating a main circuit configuration example of a voltage resonance / step-down switching DC-DC converter.

FIG. 15 is a diagram showing an example of desirable waveforms of a voltage, a current, and a gate drive signal of the main switch element of FIG. 14;

FIG. 16 is a diagram showing examples of undesired waveforms of the voltage, current, and gate drive signal of the main switch element of FIG.

FIG. 17 is a diagram illustrating a main circuit configuration example of a current resonance / step-down switching DC-DC converter.

18 is a diagram showing an example of desirable waveforms of a voltage, a current, and a gate drive signal of the main switch element of FIG.

FIG. 19 is a diagram showing an example of undesired waveforms of the voltage, current, and gate drive signal of the main switch element of FIG. 17;

FIG. 20 is a waveform chart illustrating a gate drive signal according to the first embodiment of the first invention.

FIG. 21 is a waveform chart illustrating a gate drive signal according to a second embodiment of the first invention.

FIG. 22 is a waveform chart illustrating a gate drive signal according to a third embodiment of the first invention.

FIG. 23 is a waveform chart illustrating a gate drive signal according to a fourth embodiment of the first invention.

FIG. 24 is a waveform chart illustrating a gate drive signal according to a fifth embodiment of the first invention.

FIG. 25 is a waveform chart for explaining a gate drive signal according to the first embodiment of the second invention.

FIG. 26 is a waveform chart illustrating a gate drive signal according to a second embodiment of the second invention.

FIG. 27 is a waveform chart for explaining a gate drive signal according to a third embodiment of the second invention.

FIG. 28 is a waveform chart illustrating a gate drive signal according to a fourth embodiment of the second invention.

FIG. 29 is a waveform chart illustrating a gate drive signal according to a fifth embodiment of the second invention.

FIG. 30 is a waveform chart for explaining a gate drive signal according to the first embodiment of the third invention.

FIG. 31 is a waveform chart illustrating a gate drive signal according to a second embodiment of the third invention.

FIG. 32 is a waveform chart for explaining a gate drive signal according to a third embodiment of the third invention.

FIG. 33 is a waveform chart illustrating a gate drive signal according to a fourth embodiment of the third invention.

FIG. 34 is a waveform chart illustrating a gate drive signal according to a fifth embodiment of the third invention.

[Explanation of symbols]

010 Control circuit 02 Half-wave voltage resonance switch circuit 03 Half-wave current resonance switch circuit 1 OP amplifier 2 Triangular wave generator 3 Comparator 4 Gate driver 5 Pulse generator 6 (6 _{1 to} 6 ₇ ) Logic circuit 21, 22 Comparator 23 RS flip-flop 24 inverter 101 step-down switching DC-DC converter 102 voltage resonance / step-down switching D
C-DC converter 103 Current resonance / step-down switching D
C-DC converter Cin Input capacitor Cout Output smoothing capacitor Cosc Triangular wave generation capacitor Cr Resonance capacitor D0 Flywheel diode D1 Diode IS1, IS2 Constant current source L0 Choke coil Lr Resonance inductance Q0 Main switch elements R1, R2, R11 to R13 Resistance SW1, SW2 Switch Tres = (t1 + t2) Resonance period Vcmp Comparator output Vg Gate drive signal Vin Input DC voltage Vop OP amplifier output Vosc Triangular wave Vout Output DC voltage Vp, Vp1, Vp2 Pulse signal Vref Reference voltage

Claims (11)

[Claims] 1. An on / off control of a semiconductor switching element in a switching DC-DC converter for generating and outputting a stable output DC voltage by intermittently inputting an input DC voltage via a semiconductor switching element at a predetermined first frequency. A control circuit, comprising: a triangular wave generating means for generating a triangular wave having a predetermined maximum value and a predetermined minimum value at a predetermined second frequency lower than the first frequency; and a deviation of the output DC voltage from a set voltage. Means for calculating and amplifying the voltage; comparing means for comparing the level of the calculated amplified value of the deviation voltage with the level of the triangular wave; and wherein the frequency is the first frequency, and the period of Hi and the period of Lo are the semiconductor switches, respectively. Element on and off,
Or two pulse signals having different ratios of the Hi period and the Lo period for at least a plurality of predetermined cycles, which correspond to one of the off and on states, and the output DC voltage Is too high (low) for the set voltage
In the time period which is on the increasing side of the time-series binary period of Hi / Lo outputted from the comparing means, the semiconductor switch element of the two pulse signals is turned off (on). A pulse signal having a large period ratio is selected, and an ON (OFF) period of the semiconductor switch element of the two pulse signals is selected during a period of decreasing time in the binary series of Hi / Lo in the time series. And a drive signal generating means for selecting a pulse signal having a large ratio of (1) and driving the semiconductor switch element on / off. 2. The switching DC-DC according to claim 1,
In the converter control circuit, the switching DC-DC converter is configured as a voltage resonance type in which a sinusoidal resonance voltage based on LC resonance is applied to both ends of the semiconductor switch element during an off period of the semiconductor switch element. Of the Hi or Lo period of the pulse signal,
The period corresponding to the off-state is set to one or a plurality of predetermined periods of the LC resonance so that the end of the period corresponding to the off-state of the semiconductor switch element enters a period where no resonance voltage is applied to the semiconductor switch element. Predetermined one corresponding to
Alternatively, a control circuit for a switching DC-DC converter, wherein the control circuit has a plurality of lengths, and the plurality of length periods are regularly arranged in time series on the pulse signal. 3. The switching DC-DC according to claim 2,
In the converter control circuit, the drive signal generation unit may be configured to maintain the period corresponding to the turning off of the semiconductor switch element at any one of the predetermined lengths.
A control circuit for a switching DC-DC converter, characterized by switching between two pulse signals. 4. The switching DC-DC according to claim 1,
In the converter control circuit, the switching DC-DC converter is connected to the semiconductor switch element during the ON period of the semiconductor switch element.
It is configured as a current resonance type in which a sinusoidal resonance current based on resonance flows, and in the Hi or Lo period of the two pulse signals,
The period corresponding to ON is set to one or a plurality of cycles of the LC resonance so that the end of the period corresponding to ON of the semiconductor switch element enters a period during which no resonance current flows through the semiconductor switch element. Predetermined one corresponding to
Alternatively, a control circuit for a switching DC-DC converter, wherein the control circuit has a plurality of lengths, and the plurality of length periods are regularly arranged in time series on the pulse signal. 5. The switching DC-DC according to claim 4,
In the converter control circuit, the drive signal generation unit may be configured to maintain the period corresponding to the turning on of the semiconductor switch element at any one of the predetermined lengths.
A control circuit for a switching DC-DC converter, characterized by switching between two pulse signals. 6. The switching DC-DC according to claim 1,
A control circuit for a switching DC-DC converter, wherein one of the two pulse signals is a fixed signal of Hi or Lo. 7. The switching DC-DC according to claim 1,
A control circuit for a switching DC-DC converter, wherein one of the two pulse signals is an inverted signal of the other. 8. The switching D according to claim 2, wherein
A control circuit for a switching DC-DC converter, wherein one of the two pulse signals is a fixed signal of Hi or Lo corresponding to turning on of the semiconductor switch element. 9. The switching D according to claim 4, wherein
A control circuit for a switching DC-DC converter, wherein one of the two pulse signals is a fixed signal of Hi or Lo corresponding to turning off of the semiconductor switch element. 10. The control circuit for a switching DC-DC converter according to claim 1, wherein one of said two pulse signals has a Hi or Lo period of the other at predetermined intervals. A control circuit for a switching DC-DC converter, which is maintained at Lo or Hi. 11. The switching DC-DC converter control circuit according to claim 1, wherein a rising edge or a falling edge of said two pulse signals is synchronized. D
Control circuit for C converter.