JP2001134522A - San type intelligent data cache device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a SAN type intelligent data cache capable of connecting a computer to its I/O device efficiently transferring data and drastically improving retrieval capability. SOLUTION: A three-dimensional bus is formed by arraying devices, composed of memory units, etc., and bus controllers, symmetrically in stages at 90 deg. on both the surfaces of a mother board which is mounted with a common cache memory unit 2 of tens of GB inside and arranged in the center, and the memories are shared and made accessible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data cache, and more particularly, to a data cache that can be connected to a computer and its I / O devices and the like.
SAN-type intelligent data transmission / reception system that has an arbitrated loop (hereinafter referred to as “FC-AL”) interface and can transfer and search large amounts of data.
It relates to a cache device.

[0002]

2. Description of the Related Art At present, SAN is remarkably spread as a computer network. SAN is a storage and
This is an abbreviation of Air Area Network (Storage Area Network). Unlike a LAN, which is simply a network for computer communication, a SAN has a computer assuming that computer data will have a large capacity. This is a data-centric computer network that can share the data disk itself and access it directly to avoid unnecessary data transfer.

[0003] In the FC-AL data communication under the SAN configuration, when searching for information in a shared disk device from a plurality of computers, a large amount of waiting time occurs because access is concentrated at one time, and a server is required. The response to is reduced. Although the ability to transfer data is high, the ability to search and distribute data is low, so many servers (computers serving other computers in the network system) are required.
There is a problem with the increasing number of data searches that will continue to increase in the future.

Conventionally, in the FC-AL system,
An FC-AL switch (HU
B) is used, and RA is used for the data redundancy.
An ID disk device was attached. FC-AL
The switch HUB is used merely for the purpose of branching the data transmission path, and does not itself provide data redundancy.

A conventional FC-AL switch is shown in FIG.
As schematically shown in (a), it is merely a switching means for mediating data, and therefore does not have an intelligent function for improving speed or data search capability.
When connecting an FC-AL disk or tape device, it is necessary to transfer data in accordance with the processing speed of these connected devices. As a result, the transfer speed increases as the number of connected devices increases. (At most about 100 MB), the search ability tended to decrease.

As shown in FIG. 4A, a technique of providing a cache memory in an input / output unit of a computer is well known. However, this technique is used only when reading data from a connected disk. It is cached (stored). Therefore, the recent Internet, WWW
Updating (writing) of data required by the server necessitates simultaneous reading and writing.

The bus structure of the conventional cache memory (the entire structure including the memory unit and the bus)
As shown in FIG. 3 (b), the structure is basically a two-dimensional arrangement in which a bus is formed on a motherboard and a memory unit is also mounted. I will. For this reason, the conventional SCSI base having a slow input / output I / O can still cope with it,
In the C-AL multiplex communication, a large amount of memory request could not be handled, and as a result, non-wait transfer was impossible.

Further, in the conventional silicon disk device, when this is used as a main memory area, not only the speed at the time of reading data but also the speed at the time of writing are increased.
Normally, the user needs to write data in advance, and a rewriting operation occurs for each operation. In order to adopt an expensive semiconductor memory, it is difficult to increase the capacity in terms of cost, and a process of writing only limited data in advance is required.

A RAID controller conventionally used exists as a disk RAID controller to ensure disk redundancy. However, as shown in FIG. 5A, the connection position with the computer is certainly connected by an interface such as SCSI or FC-AL. However, considering its function, the device is merely connected to the computer. It is merely a connection and does not ensure the redundancy of data transfer in the FC-AL switch for network transfer.

[0010]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to provide a computer and its I / O.
/ O device, etc., and a multi-channel FC-AL channel as an external connection interface that can be connected at the same time.
It is an object of the present invention to realize a SAN type intelligent data cache device capable of searching, that is, an intelligent data cache device applied to a SAN.

Then, this data cache device is
Positioned as an FC-AL switch, in FC-AL data communication, it is positioned between a computer and its device to temporarily cache data search and rewrite, and read / write data in cache memory without directly writing to disk. Instead, it increases the data search capability. As a result, the speed of data processing of high-speed and high-density information, which cannot be dealt with by conventional cache memory or silicon disk technology, is realized.

[0012]

SUMMARY OF THE INVENTION The present invention relates to a SAN type intelligent data cache device having a three-dimensional bus structure inside and one or more shared cache memory units mounted on the three-dimensional bus structure. The three-dimensional bus structure includes a motherboard having a data bus arranged in the center, and 9
It comprises a plurality of devices arranged in multiple stages and symmetrically so as to stand at an angle of 0 degrees, wherein the devices are a bus controller and the shared cache memory unit, a bus controller and the CPU, and a bus controller and the FC-FC. A SAN-type intelligent memory, including a combination of the AL I / F units, wherein the shared cache memory unit is shared and made accessible, and data delay is eliminated. Provide a data cache device.

The above-mentioned SAN type intelligent data
The cache device is connected to a disk device that stores data, and for block addresses of the disk device, write and read access frequencies are counted within a preset sampling time, and the shared cache memory unit is In a part of the area, data of the block address having a high access frequency is stored as a fixed memory group, and the area has a memory structure having a self-learning function corresponding to writing and reading. By adopting a configuration in which the memory area allocation for writing and reading can be arbitrarily determined, it is possible to increase the efficiency of database search and tune it.

The above-mentioned SAN type intelligent data
On the device side of the cache device, a plurality of the above disk devices are connected, and a mirroring structure for storing data in a double or triple manner in order to obtain redundancy of the data stored in the disk device is provided, and offline. A configuration having both redundancy and high speed is provided by making it possible to make a backup of the data and to make it possible to construct high-speed divisional writing in order to cope with high-speed retrieval of data.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a SAN type intelligent data cache device (hereinafter, referred to as "data cache device") according to the present invention will be described based on embodiments with reference to the drawings. FIG. 1 is a diagram illustrating an outline of an embodiment of the present invention. In FIG. 1, the basic configuration of the data cache device 1 according to the present invention is as follows.
A shared cache memory unit (hereinafter, simply referred to as a memory unit) 2 that can be mounted up to several tens of gigabytes, which is a shared memory, and a plurality of FC-AL I / F units (INPs) connected to a computer 3 on a LAN and communicating with the outside.
UT) 4 and FC-AL connected to storage device 5
I / F unit (OUTPUT) 6 and C controlling these
It comprises a PU (CPU unit) 7 and a data bus 8.

In the present invention, a huge memory unit 2 in GB (gigabyte) units is provided together with the FC-AL interfaces 4 and 6, so that a plurality of computers 3 and storage devices 5 (specifically,
DMA (direct /
(Memory access) to realize a silicon disk area with zero latency. The data search capability of this memory area can achieve 120,000 times per second.

(Bus Structure) The configuration of the data cache device 1 according to the present invention will be further described with reference to a detailed system block diagram shown in FIG. A data bus 8 is provided at the center of the data cache device 1, and the data bus 8
To the FC-AL I / F unit 4 and the FC-AL I /
It is equivalently connected to each unit such as the F unit 6, the CPU unit 7, and the plurality of memory units 2.

That is, each bus controller 9
Are connected by a module connector of the same standard, a plurality of memory units 2, a plurality of CPUs 7, and a plurality of FC-ALIs.
/ F units 4, 6 and other internal bus extension modules (bus extension modules, not shown) attached as necessary. This bus controller 9
Achieves a significant increase in search capability by synchronizing and performing zero-latency memory transfers.

More specifically, in the present invention, FIG.
As shown in (c), a three-dimensional bus structure is adopted. That is,
This three-dimensional bus structure has a motherboard 10 in the center,
A device 11 composed of a combination of a pair of units (each of the units 2, 4, 6, 7, etc.) and a bus controller 9 as shown in FIG. Are symmetrically arranged so as to stand at an angle of 90 degrees. With such a configuration, data delay can be minimized. As a result, in the prototype device according to the present invention, a data transfer speed of 1.6 to 3.2 GB / sec was realized, and a memory of several tens of GB could be completely non-wait-accessed.

The data bus 8 on the motherboard 10 connects the memory unit 2, the FC-AL I / F units 4 and 6, the CPU 7, etc., which are arranged at right angles to the motherboard 10 in multiple stages and in a highly integrated state. And a high-speed data bus having an internal speed of 1.6 to 3.2 GB / sec. By having such a high-speed bus speed and a large memory of several tens of GB, it is possible to have sufficient capacity for data input / output, and to enable simultaneous multiple access of a plurality of channels.

As described above, in the conventional FC-AL switch HUB, as shown in FIG. 3A, one-to-one or one-to-one connection between computers P1 to P3 and disks D1 to D3 Data retrieval is performed only for those connected in pairs N (see the conceptual diagram shown on the left side by the arrow in FIG. 3A), and data retrieval is performed using all connected data disk devices (Dis
k) was a non-intelligent switch.

In such a conventional FC-AL HUB switch method, a plurality of computers P1 to P3 use a disk D.
Although sharing and multiplexing of 1 to D3 were possible, only about several tens to several hundreds of search capability per second could be realized with respect to the access frequency from the computer side.

Conventionally, a plurality of motherboards having units such as a memory unit and a bus as shown in FIG. 3 (b) are provided in a plane or in multiple stages, and such a plurality of motherboards are provided. In addition, they were connected by multiple buses. Therefore, the physical arrangement of the units is not concentrated, and the length of the bus is long, so that the data transfer speed is low.

However, according to the present invention, due to the structure shown in FIG. 3C, the cache data device itself has a huge shared cache memory unit of several tens of GB and a high-speed data bus, and as described above, has a great search capability. Up is possible.

(Cache Memory) Conventional Cache Memory In FIG. 4A, data is temporarily stored in the cache memory area only when data is read (in the figure, "read" is the same as "read"). A method is adopted in which, if the same data happens to be projected in the next access and exists in the area, a hit is made and data can be obtained quickly.

[0026] In this case, a WWW server or an Internet server which can search a large amount of data at a time cannot cope with it. The reason is that if an image file with a large data amount is entered even once, that data covers all the data areas, and the probability of hitting in subsequent searches decreases.

Therefore, according to the present invention, statistics of the access of data generated during the initially set data sampling time, and in some cases, under the sampling conditions (eg, data type, etc.) are taken as the block number of the disk. By fixing the address data having the largest number of accesses as a fixed memory group on a partial area of the memory unit 2, a silicon disk having the highest data hit rate is generated, Optimize your data. Sampling of this data is continuously performed thereafter, so as to always increase the data search rate. In short, in the present invention, a partial area of the memory unit 2 has a memory structure having a self-learning function corresponding to writing and reading.

As described above, according to the present invention, a sampling condition (eg, type of data, etc.) within a preset sampling time is determined in some cases, and a history of data use status is obtained. Only used data is extracted and resident as a fixed area on the memory consisting of the memory unit 2 (a silicon disk is created)
Then, a high data hit rate is realized in the subsequent search. The data here is managed by a block number when viewed from the computer 3, and the efficiency attained by managing the data at the block number level as one unit.

For example, in response to a request from the computer 3, the history of the block address of the disk where the data is stored is used to store the frequently used block data in the fixed memory in the memory unit 2. It is stored in an area and is made into a silicon disk as described above to realize a high-speed data transaction.

With such a memory structure, FIG.
As shown in (b), the concept of reading data is the same as “read” in the figure.
In addition to writing, 100% cache storage is performed at the same time, and the computer is notified of the completion of data transfer. As a result, it is possible to perform a data search as viewed from the computer as efficiently as possible.

The SAN has a configuration in which data is shared by a plurality of computers as a single unit. In this SAN, an intelligent cache stores only frequently-used data from a plurality of computers in a fixed memory. You can do it.

By optimizing the data in the cache, a system capable of coping with a large number of data searches, such as a web server or a database server via the Internet, can be constructed. It is to be noted that the allocation of the memory area (fixed area) for writing and reading the data can be arbitrarily determined by changing the allocation table of the CPU, thereby improving the efficiency of database search and tuning the database. is there.

(RAID Function) As shown in FIG. 5A, a conventional technology RAID (redundancy disk array) has a general subsystem structure in which disks are connected from a RAID controller as one dedicated system. there were.

In the present invention, as shown in FIG.
Each computer accesses the shared memory area as a C-AL switch, and the storage device 5 on which the computer is based is directly doubled or tripled (connecting a plurality of disk devices) to increase redundancy. I have it. This is a simpler mirroring of the data disk, without a parity-based one like the conventional "RAID5", but it is scalable and easy to integrate multiple host computers because it is directly connected to the FC-AL. I do.

As a result, a network-type redundancy unit can be realized which does not sacrifice the search speed while also securing data security. The principle of this multiplexing is basically that the output from shared memory to disk is D
Just set the transfer destination of MA to multiple, same SCSI
-Assign ID to multiple disks.

In short, if a plurality of disk devices 12 are connected as storage devices 5 to the device side of the data cache device 1 according to the present invention, the data is duplicated or tripled in order to obtain redundancy of the stored data. A mirroring structure for storing data can be constructed, data can be backed up offline, and high-speed data retrieval can be performed by high-speed divisional writing of data.

Although the data cache according to the present invention has been described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications may be made within the technical scope of the claims. It goes without saying that there are embodiments.

[0038]

The data cache device according to the present invention having the above-described configuration is provided with a large-capacity intelligent memory for efficiently transferring and retrieving data.
Peripheral devices such as disks can be sped up, and if a computer and its I / O device are connected by an FC-AL interface and used as an FC-AL switch, data is cached for both reading and writing. Therefore, it is possible to greatly improve the search capability in the WWW server and the data search server.

The present invention basically has the character of an intelligent memory disk device, and develops data extracted under a certain data sampling time or under a certain condition in its memory. There is no need to examine data, and the speed of data input / output and data search ability can be improved.
The external connection interface has multiple channels of FC-AL, and the internal structure has an overwhelming data bus of 1.6 to 3.2 GB / sec.
-FC-A because AL channel port can be connected at the same time
It is also very useful as an L switch.

In the present invention, compared with the data cache memory capacity of about 64 MB to 128 MB in the past,
It has a running capacity from GB to 48GB. Therefore, a disk device of 1000 GB to 10,000 GB can be effectively connected behind. (The actual capacity is the sum of the connected disk devices.) Therefore, large-capacity data can be operated as a high-speed memory.

According to the present invention, in addition to the original data caching, when a plurality of disks are connected, the FC-AL switch performs mirroring (duplication) and striping (distributed writing) when connected to the FC-AL. Disks can protect data with redundancy. This mirroring can have three systems, and the third one can be operated as an offline backup.

In the present invention, a motherboard is arranged in the center,
On both sides of this motherboard, a device consisting of a bus controller and each unit is provided so as to stand up at an angle of, for example, 90 degrees, and a three-dimensional bus structure that connects and connects symmetrically minimizes data delay. As a result, a data transfer speed of 1.6 to 3.2 GB / sec is realized, and tens of GB of memory can be completely non-wait-accessed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an outline of an embodiment of a data cache device according to the present invention.

FIG. 2 is a block diagram of an embodiment of a data cache device according to the present invention.

3A is a diagram showing a conventional FC-AL product, FIG. 3B is a diagram showing a bus structure of a conventional cache memory, and FIGS. 3C and 3D are data diagrams of the present invention. FIG. 2 is a diagram illustrating a three-dimensional bus structure of an embodiment of a cache device.

FIG. 4 is a diagram comparing the concept of a conventional cache memory with the concept of a data cache device of the present invention.

FIG. 5 is a diagram comparing the concept of the conventional RAID function with the concept of using the RAID of the present invention.

[Explanation of symbols]

Reference Signs List 1 data cache device 2 shared cache memory unit (memory unit) 3 computer 4 FC-AL I / F unit (INPUT) 5 storage device 6 FC-AL I / F unit (OUTPUT) 7 CPU 8 data bus 9 bus controller DESCRIPTION OF SYMBOLS 10 Motherboard 11 Device consisting of bus controller and each unit 12 Disk unit

Claims (3)

[Claims] 1. A SAN type intelligent data storage device having a three-dimensional bus structure therein, and one or more shared cache memory units mounted on the three-dimensional bus structure.
A cache device, wherein the three-dimensional bus structure includes a motherboard having a data bus disposed in the center, and a plurality of devices symmetrically arranged on both sides of the motherboard so as to stand upright. The device includes a bus controller and the shared cache memory unit, a bus controller and a CPU,
And a combination of a bus controller and an FC-AL I / F unit, wherein the shared cache / memory unit is made accessible and accessible, and data delay is eliminated. SAN type intelligent data cache device. 2. The SAN-type intelligent data cache device is connected to a disk device for storing data, and a write / read access frequency of a block address of the disk device within a preset sampling time. In the shared cache memory unit, the data of the frequently accessed block address is stored as a fixed memory group in a partial area, and the area has a self-learning function corresponding to writing and reading. The memory structure for each of writing and reading of the data can be arbitrarily determined.
2. The SAN-type intelligent data cache device according to claim 1, wherein the efficiency of database search and the tuning thereof are possible. 3. A plurality of disk units are connected to the device side of the SAN type intelligent data cache unit, and the disk units are doubled or tripled to obtain redundancy of data stored in the disk units. A mirroring structure for storing data is provided, enabling backup of data offline, and a configuration that allows high-speed divisional writing to be configured to support high-speed data retrieval, thereby increasing redundancy and high speed. 3. The structure according to claim 1, wherein the structure is combined.
The SAN-type intelligent data cache device according to claim 1.