JP2001116809A - Delay signal generating device and its delay amount adjusting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delay amount adjusting method capable of adjusting a delay amount based upon delay setting data obtained by a loop method or the like. SOLUTION: In this embodiment, first, n phase difference of delay signals passing two paths including one delay element from delay elements N1 to Nn is measured for calculating a phase difference of delay signals passing both paths. Next, a delay element of only a first path of the two paths is switched and the original delay element is used in a second path for calculating a phase difference between different delay elements in the first path. Then, the delay element of the first path is fixed and the delay element in the second path is switched to that of the first path for calculating a phase difference between different delay elements in the second path. One feature of a calculating method of a phase difference in this device is to switch a delay element of one path of the first or second path for sequentially calculating a phase difference of the first and second path.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay signal generator for generating a delay signal, and more particularly, to a delay signal generator capable of accurately adjusting a delay time of a delay signal.

[0002]

2. Description of the Related Art FIG. 1 shows a conventional delay signal generator 50 used in a semiconductor test apparatus. The delay signal generation device 50 has a delay signal generation function of delaying an input signal at a predetermined timing and a delay time measurement function of measuring a delay time of the delay signal. The delay signal generation device 50 includes a delay unit 10, selection units 12, 14, variable delay units 16, 18, and a signal switching unit 20 as a configuration for generating a delay signal. In addition, the delay signal generating device 50 includes a period measuring unit 22, a loop forming unit 32, AND gates 24 and 28, and OR gates 26 and 30 as a configuration for measuring a delay time. The loop forming section 32 has an AND gate 34 to which a CTRL1 signal for determining whether to form a loop is input.

The delay section 10 has a plurality of delay elements N1 to Nn each having a different delay amount. Further, the variable delay unit 16 or 18 can generate a desired accurate minute delay amount. The selection unit 12 or 14 selects one of the delay signals delayed by the plurality of delay elements based on the input selection signal, and selects one of the variable delay units 16 or 18.
Output to The signal switching unit 20 receives the output of the variable delay unit 16 or 18 and outputs a signal having predetermined rising timing and falling timing.

It is desirable that delay elements N1 to Nn are formed so as to have an expected predetermined design delay amount.
However, in reality, an error may occur between the delay time actually given by the delay element and the designed delay time due to variations in the quality of the delay element.
In order to eliminate this error, it is necessary to actually obtain the optimum combination of the delay elements N1 to Nn and the delay amount of the variable delay unit 16 or 18 for generating a predetermined delay time by measurement. Therefore, conventionally, a delay time of a path including a delay element is measured by using a measurement method called a loop method.

In order to measure the delay time of a path including the delay element N1, a CTRL1 signal having a logical value H is first ANDed.
By inputting to the gate 34, a loop path including the delay element N1 is formed. From one input of the OR gate 36, a pulse is input to the delay element N1. Selector 12
Outputs a pulse delayed through the delay element N1. The pulse passed through the variable delay unit 16 is output to the AND gate 3
4. The signal is again input to the delay element N1 through the OR gate 36. The cycle measuring unit 22 measures the cycle of the loop by counting the pulses for a predetermined time, and measures the delay time of the loop path including the delay element N1. The same measurement is performed for the other delay elements N2 to Nn using the loop method. Although not shown, a loop forming unit 32 is also provided for the path passing through the variable delay unit 18, and the delay time of the path including the delay elements N1 to Nn is measured.

In order to measure the delay time of the variable delay unit 16, a loop path of the variable delay unit 16 is formed by using the CTRL2. The pulse passing through the variable delay unit 16 passes through an AND gate 24 and an OR gate 26,
It is input to the variable delay unit 16 again. The cycle measuring unit 22
The cycle of the loop is measured by counting the pulses for a predetermined time, and the delay time of the variable delay unit 16 is measured. Similarly, the delay time of the variable delay unit 18 is measured using the loop method. As described above, conventionally, the delay time of the path including each of the delay elements N1 to Nn and the delay times of the variable delay units 16 and 18 are measured using the loop method, and the delay time is determined based on the measurement results. The relative phase difference between the delay amounts of the elements N1 to Nn has been determined.

[0007]

The measurement of the loop oscillation cycle by the loop method is performed under a special environment in which an input pulse rotates in a loop for a predetermined period at a constant cycle. This environment is significantly different from the environment at the time of the actual semiconductor test. When the delay elements N1 to Nn are composed of CMOS circuits, an error may occur between the delay time adjusted by the loop method and the delay time in the actual operation due to the period of the signal passing through the delay elements. There is. In addition, since the CMOS circuit changes its output characteristics due to voltage fluctuations and temperature changes, in an actual operation different from the environment of the cycle measurement by the loop method,
An error may occur between the adjusted delay time and the delay time in actual operation. Further, since the signal line is also affected by disturbance, the measurement result measured under a special environment cannot always be applied during actual operation. For these reasons, the delay elements N1 to N1 measured by the loop method
The phase difference of the delay amount of Nn may include an error during the actual operation of the delay signal generation device 50. In order for the delay signal generator 50 to generate an accurate delay signal, the phase error needs to be removed.

The delay signal generator 50 is provided for each pin of the device under test 62. A plurality of delay signal generation devices 5
0 to generate an accurate delay signal with uniform skew, the delay element N1
ＮNn, and the relative phase difference between the plurality of delay signal generators 50 needs to be measured. The relative phase difference between the plurality of delay signal generators can be determined by measuring a deviation from an absolute phase reference. An object of the present invention is to obtain a relative phase error between delay elements N1 to Nn of a delay signal generation device and adjust a delay amount of a delay signal based on the phase error.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a delay signal generating apparatus which calculates a phase error of each delay path and generates an accurate delay time. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous embodiments of the present invention.

[0010]

According to a first aspect of the present invention, a plurality of delay elements for delaying an input reference signal by different times and outputting a plurality of delay signals are provided. Having a delay unit, a first selection unit that selects one of the plurality of delay signals, and a first variable delay that can delay the delay signal selected by the first selection unit by a desired delay time A second selector for selecting one of the plurality of delay signals, and a second variable delay for delaying the delay signal selected by the second selector by a desired delay time. A comparison unit that compares the phases of the output of the first variable delay unit and the output of the second variable delay unit, and the output of the first variable delay unit or the output of the second variable delay unit based on the comparison result in the comparison unit. An error calculator for calculating a phase error; Based on the phase error, to provide a delay signal generating apparatus characterized by comprising a delay amount adjusting unit that adjusts the delay amount of the first variable delay unit or the second variable delay unit.

According to a second aspect of the present invention, there is provided a delay signal generating apparatus including a delay unit having a plurality of delay elements for outputting a plurality of delay signals obtained by delaying an input reference signal by different times, A delay amount adjusting method for adjusting a delay amount based on predetermined delay setting data so as to delay a reference signal by a plurality of predetermined times, wherein the delay amount is output from a first delay element which is one of a plurality of delay elements. A first selecting step of selecting a first delay signal; and a first delaying the first delay signal selected in the first selecting step based on the delay setting data so as to be delayed from the reference signal by a predetermined first time. A delay step; a second selection step of selecting a first delay signal output from the first delay element; As delayed by 1 hour, a second delay step of delaying based on the delay setting data, first
A first comparing step of measuring a first phase difference by comparing a phase of the first delayed signal delayed in the delay step with a phase of the first delayed signal delayed in the second delay step; And adjusting the delay amount based on the delay setting data based on the comparison result in (1).

The delay amount adjusting method includes a third selecting step of selecting a second delay signal output from a second delay element, which is one of the plurality of delay elements, and a second delay selected in the third selecting step. A third delay step of delaying the signal based on the delay setting data so as to delay the signal by a predetermined second time from the reference signal, and a fourth selection step of selecting the first delay signal output from the first delay element The first delay signal selected in the fourth selection step is delayed in the fourth delay step and the third delay step based on the delay setting data so as to be delayed by a predetermined second time from the reference signal. A second comparing step of measuring a second phase difference by comparing a phase of the second delayed signal with a phase of the first delayed signal delayed in the fourth delay step; A first calculation step of calculating a first phase error between the first delay signal delayed in the first delay step and the second delay signal delayed in the third delay step, using the comparison result obtained in the first delay step; Adjusting the delay amount based on the delay setting data based on the first phase error calculated in the calculation step. The first calculating step may include calculating a first phase error based on the first phase difference measured in the first comparing step and the second phase difference measured in the second comparing step. .

Further, the delay amount adjusting method includes a fifth selecting step of selecting a second delayed signal output from the second delay element, and a step of converting the second delayed signal selected in the fifth selecting step from a reference signal to a predetermined value. A fifth delay step of delaying based on the delay setting data so as to be delayed by the third time, a sixth selection step of selecting a second delay signal output from the second delay element, and a sixth selection step. A sixth delay step of delaying the obtained second delay signal based on the delay setting data so as to be delayed from the reference signal by a predetermined third time; and a phase of the second delay signal delayed in the fifth delay step. Comparing the phases of the second delay signals delayed in the sixth delay step to measure a third phase difference, and using the comparison result in the third comparison step. And a second calculation step of calculating a second phase error of the first delay signal delayed in the second delay step, a second phase error of the second delay signal delayed in the sixth delay step, and a second calculation step. Second
Adjusting the delay amount based on the delay setting data based on the phase error. The second calculating step is the third calculating step, which is performed in the third comparing step.
The method may include calculating a second phase error based on the phase difference and the first phase error.

According to a third aspect of the present invention, there is provided a delay unit having a plurality of delay elements for outputting a plurality of delay signals obtained by delaying an input reference signal by different times, and a delay unit for delaying one of the plurality of delay signals. A first selection unit that selects a signal, a first variable delay unit that can delay the delay signal selected by the first selection unit by a desired delay time, and a delay signal that is one of a plurality of delay signals. A second selection unit to be selected;
In the delay signal generation device including a second variable delay unit that can delay the delay signal selected by the selection unit by a desired delay time, the reference signal is predetermined to be delayed by a plurality of predetermined times. A delay amount adjustment method for adjusting a delay amount according to delay setting data of a first variable delay unit or a second variable delay unit, wherein the first selection unit determines a delay amount from a first delay element that is one of a plurality of delay elements. A first selection step of selecting the output first delay signal; and a first variable delay unit, based on the delay setting data, converts the first delay signal selected in the first selection step from a reference signal to a predetermined first delay signal. A first delay step for delaying the delay by one hour, a second selection unit for selecting the first delay signal output from the first delay element, and a second variable delay unit for delay setting data A second delay step of delaying the first delay signal selected in the second selection step from the reference signal by a predetermined first time based on the first delay signal; Comparing the phase with the phase of the first delay signal delayed in the second delay step to measure a first phase difference; and, based on the comparison result in the first comparison step, based on the delay setting data. Adjusting the delay amount.

[0015] In the delay adjusting method, the first selecting unit may output the second delay element output from the second delay element which is one of the plurality of delay elements.
A third selection step of selecting a delay signal, and the first variable delay unit delays the second delay signal selected in the third selection step by a predetermined second time from the reference signal based on the delay setting data. A third delay step in which the first delay signal is output from the first delay element, and a second variable delay section in which the second variable delay section determines, based on the delay setting data, A fourth delay step of delaying the first delay signal selected in the fourth selection step by a predetermined second time from the reference signal, a phase of the second delay signal delayed in the third delay step, Comparing a phase of the first delay signal delayed in the fourth delay step to measure a second phase difference; a first phase difference measured in the first comparison step; The measured in Step 2
A first calculating step of calculating a first phase error between a first delay signal delayed in the first delay step and a second delay signal delayed in the third delay step, based on the phase difference; And adjusting the delay amount based on the delay setting data based on the first phase error calculated by the above.

In the delay adjusting method, the first selecting section may select a second delay signal output from the second delay element in a fifth selecting step, and the first variable delay section may select a second delay signal based on the delay setting data. A fifth delaying step of delaying the second delay signal selected in the fifth selection step so as to be delayed by a predetermined third time from the reference signal; and a second selector configured to output the second delay signal from the second delay element. A sixth selection step of selecting a delay signal, and the second variable delay unit delays the second delay signal selected in the sixth selection step by a predetermined third time from the reference signal based on the delay setting data. And comparing the phase of the second delay signal delayed in the sixth delay step with the phase of the second delay signal delayed in the fifth delay step,
A third comparing step of measuring the phase difference, a third phase difference measured in the third comparing step, a first delay signal delayed in the second delay step based on the first phase error, and a sixth delay A second calculating step of calculating a second phase error of the second delayed signal delayed in the step, and a step of adjusting a delay amount based on the delay setting data based on the second phase error calculated in the second calculating step. It is characterized by having.

According to a fourth aspect of the present invention, there is provided a delay signal generating apparatus including a delay unit having a plurality of delay elements for outputting a plurality of delay signals obtained by delaying an input reference signal by different times. A phase error calculation method for calculating a phase error between two delay signals that pass through different delay elements and that are delayed based on predetermined delay setting data so as to delay the delay signals by a plurality of predetermined times. A first selection step of selecting a first delay signal output from a first delay element, which is one of the elements, and the first delay signal selected in the first selection step is changed from a reference signal by a predetermined first time. A first delay step of delaying based on the delay setting data so as to be delayed, a second selection step of selecting a first delay signal output from the first delay element, and a second selection step. A first delay signal selected have, as delayed from the reference signal by a predetermined first time, a second delay step of delaying based on the delay setting data, first
A first comparing step of comparing a phase of the first delayed signal delayed in the delay step with a phase of the first delayed signal delayed in the second delay step to measure a first phase difference. And

The phase error calculating method includes a third selecting step of selecting a second delayed signal output from a second delay element, which is one of the plurality of delay elements, and a second delay selected in the third selecting step. A third delay step of delaying the signal based on the delay setting data so as to delay the signal by a predetermined second time from the reference signal, and a fourth selection step of selecting the first delay signal output from the first delay element The first delay signal selected in the fourth selection step is delayed in the fourth delay step and the third delay step based on the delay setting data so as to be delayed by a predetermined second time from the reference signal. The phase of the second delay signal and the fourth
A second comparing step of comparing a phase of the first delayed signal delayed in the delay step and measuring a second phase difference;
A first delay signal delayed in the first delay step based on the first phase difference measured in the first comparison step and the second phase difference measured in the second comparison step; And a first calculating step of calculating a first phase error of the obtained second delayed signal.

Further, the phase error calculating method includes a fifth selecting step of selecting a second delayed signal output from the second delay element, and a step of converting the second delayed signal selected in the fifth selecting step from a reference signal to a predetermined value. To be delayed by the third hour of
A fifth delay step for delaying based on the delay setting data, a sixth selection step for selecting the second delay signal output from the second delay element, and a second delay signal selected in the sixth selection step as a reference. A sixth delay step of delaying based on the delay setting data so as to be delayed by a predetermined third time from the signal, a phase of the second delay signal delayed in the fifth delay step, and a delay in the sixth delay step A third comparing step of measuring a third phase difference by comparing the phases of the second delayed signals; a second delaying step based on the third phase difference measured in the third comparing step and the first phase error; And a second calculating step of calculating a second phase error of the second delayed signal delayed in the sixth delay step.

The above summary of the present invention does not list all of the necessary features of the present invention, and a sub-combination of these features may also be an invention.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described through embodiments of the present invention. However, the following embodiments do not limit the invention according to the claims, and are described in the embodiments. Not all combinations of features are essential to the solution of the invention.

FIG. 2 is a block diagram of a semiconductor test apparatus 60 for testing the device under test 62. The semiconductor test apparatus 60 includes a pattern generator 52, a waveform shaper 54, a timing generator 66, a signal input / output unit 56, and an output determination unit 58. The timing generator 66 has a plurality of delay signal generation devices 100.

The pattern generator 52 is connected to the device under test 6.
2 to generate an input pattern and a reference signal. The input pattern is supplied to a waveform shaper 54, and the reference signal is supplied to a timing generator 66. The timing generator 66 includes a plurality of delay signal generation devices 100 for delaying the reference signal. Delay signal generation device 100
Has a memory that stores delay setting data relating to a combination of delay elements that generate a predetermined delay time.
The memory stores delay setting data measured in advance by a loop method or the like. The delay setting data stored in the memory may be, for example, a design delay value expected when designing the delay element. In the present invention, the delay signal generation device 100 adjusts a delay amount according to delay setting data and generates a delay signal having an accurate delay time. The timing generator 66, in accordance with the input characteristics or test item of the device under test 62, and outputs a desired delay signal to ¹ each pin of the device under test 62.

The delay signal output from the timing generator 66 is supplied to the waveform shaper 54. Waveform shaper 54
Delays an input pattern based on a delayed signal, and outputs a delayed input pattern as a delayed input pattern to the signal input / output unit 5.
6 In this embodiment, the delay signal generation device 100 is incorporated in the timing generator 66, but in another embodiment, the delay signal generation device 100
May be incorporated in the waveform shaper 54. In this case, the delay signal generation device 100 outputs a delay pattern obtained by delaying the input pattern by a predetermined time according to the input characteristics of the device under test 62.

The device under test 62 includes a signal input / output unit 56
And outputs an output signal to the output determination unit 58 based on the received delay pattern. For example, if the device under test 62 is a memory device, data stored in the device under test 62 is output as an output signal based on the delay pattern, and if the device under test 62 is an arithmetic unit, the data is output based on the delay pattern. The calculated result is output as an output signal. In the present embodiment, the output signal of the device under test 62 may be supplied to the output determination unit 58 after the timing is measured by the timing generator 66. Device under test 62
When testing the output characteristics of the
And the device under test 6
2 is compared with the output timing, and the timing of the output signal is measured.

The pattern generator 52 outputs an expected value pattern expected as an output response to the normal device under test 62 to the output judging section 58. The output determination unit 58 determines the quality of the device under test 62 by detecting whether the output signal of the device under test 62 matches the expected value pattern.

FIG. 3 shows a configuration of the delay signal generation device 100 in the semiconductor test device 60. Delay signal generator 1
No. 00 has a delay signal generation function for delaying an input signal at a predetermined timing and a delay time measurement function for measuring a delay time of a delay signal. The delay signal generation device 100 has a configuration for generating a delay signal,
Delay unit 10, selection units 12, 14, variable delay units 16, 1
8, signal switching unit 20, and selection signal supply units 70 and 72
Is provided. The delay signal generating apparatus 100 includes a period measuring unit 22, a loop forming unit 32, AND gates 24 and 28, and an OR gate 2 for obtaining delay setting data for delaying a reference signal by a predetermined time by a loop method.
6 and 30. The loop forming unit 24 receives an input of a CTRL1 signal that determines whether or not to form a loop.
It has a gate 34. The configuration given the same reference numerals as those given in the conventional delay signal generation device 50 shown in FIG. 1 can realize the same functions and operations as the corresponding configuration.

The delay signal generator 100 according to the present embodiment
Is a configuration for adjusting the delay amount based on the delay setting data obtained by the loop method.
4, 76, 78, a selection unit 80, a selection signal supply unit 92, a variable delay unit 90, a comparison unit 82, a determination unit 84, and an error calculation unit 86.

The delay section 10 includes a plurality of delay elements N1 to Nn for respectively delaying input delay signals by different times.
Having. Each of the delay elements N1 to Nn is configured by, for example, a CMOS circuit or the like. In FIG. 3, each delay element N
1 to Nn are connected in parallel with each other.
0 may be configured to extract delayed signals having different delay times from each of the delay elements connected in series. The delay unit 10 can output a plurality of delay signals obtained by delaying the reference signal by different times. For example, the delay element N1 has a design delay amount of 0, the delay element N2 has a design delay amount of 4 ns, and the delay element Nn
It may be configured to have a design delay amount of 4 · (n−1) ns.

The variable delay units 16, 18, and 90 can generate a desired accurate delay amount. Variable delay unit 1
Each of 6, 18, and 90 has a function of further delaying the delay signal output from the delay unit 10 and outputting a signal accurately delayed by a desired time from the reference signal. The variable delay units 16, 18, and 90 preferably have a delay resolution on the order of a few picoseconds, for example.

The selector 12, 14, or 80 selects and outputs one of the delay signals delayed by the plurality of delay elements N1 to Nn based on the input selection signal. The selection signal specifies which of the delay signals supplied from the delay unit 10 is to be selected. Selection unit 12,
14 or 80 is configured as a multiplexer, for example. The selection unit 12 is supplied with a selection signal from a selection signal supply unit 70, the selection unit 14 is supplied with a selection signal from a selection signal supply unit 72, and the selection unit 80 is supplied with a selection signal supply unit 92
Supplies a selection signal.

The signal switching section 20 receives the output of the variable delay section 16 or 18 and outputs a signal having predetermined rising timing and falling timing to the output port 9.
Output from 4. In the present embodiment, the signal switching unit 20
Although configured as an RS flip-flop, it may be configured with another flip-flop or the like.

Referring to FIG. 2, delay signal generating apparatus 100
Is used as the timing generator 66, the delay signal output from the output port 94 is supplied to the waveform shaper 54. The waveform shaper 54 delays the input pattern supplied from the pattern generator 52 based on the delay timing based on the delay signal, and outputs the input pattern to the signal input / output unit 56. When the delay signal generator 100 is used as the waveform shaper 54, the waveform shaper 54 delays the input pattern supplied from the pattern generator 52 by the delay unit 10 and the variable delay units 16 and 18, and From the output port 94 to the signal input / output unit 56.

As described above, the delay signal generator 100 measures the delay time of the path passing through each delay element in advance by using the loop method. The measurement result is stored as delay setting data, which is data relating to a combination of any one of the delay elements N1 to Nn that generate a predetermined delay time and the delay amounts of the variable delay units 16, 18, and 90 (see FIG. (Not shown). For example, when it is desired to delay the input reference signal by 5 ns, data on a combination of N1 of the design delay amount of 4 ns and the delay amounts of the variable delay units 16, 18, and 90 is stored in the memory. The delay amount of each of the variable delay units 16, 18, and 90 for generating a predetermined delay time does not always match due to a path, an element, and the like existing between the delay unit 10 and each of the variable delay units 16, 18, and 90. . The memory is a delay amount adjusting unit 7
4, 76, and 78, or may be provided independently of the delay amount adjustment units 74, 76, and 78. When the reference signal is delayed, the delay setting data is transmitted to each of the selection signal supply units 70, 72, and 92 and each of the variable delay units 1
6, 18 and 90 to be selected and selected for delay elements N1 to N
n and the delay amount of the variable delay unit 16, 18 or 90 are determined.

In this embodiment, the delay setting data is
Although it is desirable that the measurement result is a measurement result obtained by a loop method, in another embodiment, the measurement result may be data relating to a design delay value of each of the delay elements N1 to Nn. At this time, 5 ns
Is the data for selecting the delay element N1 having the design delay amount of 4 ns and setting the delay amount of the variable delay unit 16, 18, or 90 to 1 ns. The delay setting data may be any data that is predetermined so as to delay the reference signal by a predetermined time. Further, it is desirable that the delay setting data is data for delaying the reference signal by a plurality of predetermined times. For example, 1 ns, 5 ns, 7 ns, 9
Data for generating a delay time such as ns, 11 ns,... is stored in the memory in advance as delay setting data.

Next, a configuration will be described in which the delay amount based on the predetermined delay setting data is adjusted so as to be adapted to the environment of the delay signal generation device 100 during the actual operation. The delay signal generation device 100 has an adjustment path for supplying the delay signal output from the delay unit 10 to the variable delay unit 90, separately from a path for outputting the delay signal to the outside via the output port 94.

The selection section 80 selects one of the plurality of delay signals output from the delay section 10 based on the selection signal supplied from the selection signal supply section 92. The variable delay unit 90 can delay the delay signal selected by the selection unit 80 so as to be delayed by a desired delay time from the reference signal. The output of the variable delay unit 90 is supplied to the comparison unit 82. The output of the signal switching unit 20 is also supplied to the comparison unit 82. The comparison unit 82 receives the data input D
And a latch circuit having a clock input CLK, an output of the signal switching unit 20 is input to the data input D, and an output of the variable delay unit 90 is input to the clock input CLK.

A method for measuring and calculating the phase error between the delay signal passing through the variable delay circuit 16 and the delay signal passing through the variable delay circuit 90 will be described below.

First, in order to generate a predetermined delay time T1, the selectors 12 and 80 select the delay signal output from the delay element N1 based on the delay setting data of the delay time T1, and 16 and the variable delay unit 90
The delay amount is adjusted independently of each other so that the delay signal is delayed from the reference signal by the time T1, and the delay signal is delayed.

The comparing section 82 outputs the output of the variable delay section 16 and
The phase of the output of the variable delay unit 90 is compared. When the delay setting data is a measurement result obtained by the loop method, under the same environment as the measurement environment by the loop method, the output phases of the variable delay unit 16 and the variable delay unit 90 are in principle coincident. Should have exactly the delay time T1. However, the environment at the time of measuring the phase error substantially equal to the environment at the time of actual operation of the delay signal generation device 100 is different from the measurement environment by the loop method in the point of the power supply voltage value, the temperature, and the like. The output phases of the variable delay unit 16 and the variable delay unit 90 do not always match.

The comparator 82 outputs the signal input to the data input D at the rise of the output of the variable delay unit 90. The determining unit 84 determines whether the output of the variable delay unit 16 and the phase of the output of the variable delay unit 90 match based on the output of the comparing unit 82. If the phases do not match, the determination unit 84 notifies the delay amount adjustment unit 78 that the phases do not match, and the delay amount adjustment unit 78 adjusts the delay amount of the variable delay unit 90, and The output phase of the unit 90 is shifted. The determination unit 84 determines that the output of the comparison unit 82 is a logical value H
Upon detecting that the signal has been switched from (high) to L (low) or from L to H, it is determined that the phases of the output of the variable delay unit 16 and the output of the variable delay unit 90 match. As described above, the comparing unit 82 compares the phase of the output of the variable delay unit 16 with the phase of the output of the variable delay unit 90, and searches for the change point of the output of the variable delay unit 16 at the output timing of the variable delay unit 90. The first phase difference between the two outputs is measured. The first phase difference thus obtained is
This corresponds to a time difference between a path from the delay element N1 to the variable delay unit 16 and a path from the delay element N1 to the variable delay unit 90.

When a delay signal having a delay time T1 is generated in a semiconductor device test, the delay amount adjusting unit 74 or 78 uses the delay setting data of the delay time T1 based on the measured first phase difference. The amount can be adjusted. As described above, in order to adjust the output phase among the plurality of delay signal generators 100 and generate a delay signal with a uniform skew, the deviation (phase difference) between the delay signal generators from the absolute phase reference is used. ) Is obtained in advance. The delay amount adjusting unit 74 or 78 adjusts the delay amount based on the delay setting data of the delay time T1 based on the phase difference from the absolute phase reference and the measured first phase difference.

Subsequently, in order to generate a predetermined delay time T2, the selector 12 selects the delay signal output from the delay element N2 based on the delay setting data of the delay time T2, Delays the delayed signal so as to be delayed from the reference signal by the time T2. On the other hand, the selection section 80 selects the delay signal output from the delay element N1 based on the delay setting data of the delay time T2, and the variable delay section 90 causes the delay signal to be delayed from the reference signal by the time T2. Delay.

The comparing section 82 outputs the output of the variable delay section 16 and
The phase of the output of the variable delay unit 90 is compared. Judgment unit 84
Determines whether the phase of the output of the variable delay unit 16 matches the phase of the output of the variable delay unit 90, based on the output of the comparison unit 82. If the two phases do not match, the delay amount adjusting unit 78 adjusts the delay amount of the variable delay unit 90 and searches for a change point of the output of the variable delay unit 16 so that the two phases match. , The comparator 82 measures the second phase difference between the two.

Based on the second phase difference and the first phase difference, the error calculating section 86 determines, at the output of the variable delay section 16, a first path between the path including the delay element N1 and the path including the delay element N2. Calculate the phase error. When outputting a delay signal having a delay time T2 from the variable delay unit 16 during a semiconductor device test, the delay amount adjustment unit 74 determines a delay based on the delay setting data of the delay time T2 based on the calculated first phase error. The amount can be adjusted. The delay amount adjusting unit 74 calculates the phase difference from the absolute phase reference and the calculated first
The delay amount based on the delay setting data of the delay time T1 is adjusted based on the phase error. If the first phase error is used, the variable delay unit 16 calculates the delay time from the delay time T2 without considering the error factors existing between the delay element N1 and the variable delay unit 16 and between the delay element N2 and the variable delay unit 16. A delay signal having a delay time within the range of the variable delay amount can be accurately generated.

Subsequently, in order to generate a predetermined delay time T3, the selector 12 selects the delay signal output from the delay element N2 based on the delay setting data of the delay time T3, and Delays the delayed signal so as to be delayed from the reference signal by the time T3. Similarly, the selection unit 80 determines, based on the delay setting data of the delay time T3,
The delay signal output from the delay element N2 is selected, and the variable delay unit 90 delays this delay signal from the reference signal by a time T3.

The comparing section 82 outputs the output of the variable delay section 16 and
The phase of the output of the variable delay unit 90 is compared. Judgment unit 84
Determines whether the phase of the output of the variable delay unit 16 matches the phase of the output of the variable delay unit 90, based on the output of the comparison unit 82. If the two phases do not match, the delay amount adjusting unit 78 adjusts the delay amount of the variable delay unit 90 and searches for a change point of the output of the variable delay unit 16 so that the two phases match. , The comparison unit 82 measures the third phase difference between the two.

The error calculating section 86 calculates the output of the variable delay section 90 based on the third phase difference and the first phase error.
A second phase error between a path including the delay element N1 and a path including the delay element N2 is calculated. When outputting a delay signal having a delay time T3 from the variable delay unit 90 during a semiconductor device test, the delay amount adjustment unit 78 determines the delay based on the delay setting data of the delay time T2 based on the calculated second phase error. The amount can be adjusted. Specifically, the delay amount adjusting unit 74 determines the delay time T2 based on the phase difference from the absolute phase reference and the calculated second phase error.
The delay amount is adjusted according to the delay setting data. If the second phase error is used, the variable delay unit 90 calculates the delay time from the delay time T2 without considering the error factors existing between the delay element N1 and the variable delay unit 90 and between the delay element N2 and the variable delay unit 90. A delay signal having a delay time within the range of the variable delay amount can be accurately generated.

In this embodiment, first, the delay element N
The phase difference between the delay signals passing through two paths including one delay element from 1 to Nn is measured, and the phase difference between the delay signals passing through both paths is calculated. Next, the first of the two routes
Switching the delay element only for the path, and for the second path,
The phase error between the different delay elements in the first path is calculated using the original delay element. Then, the delay element in the first path is fixed, the delay element in the second path is switched to that of the first path, and the phase error between different delay elements in the second path is calculated. The calculation method of the phase error according to the present invention,
The delay element in one of the first path and the second path is fixed, the other delay element is switched, and the phase error between the delay elements in the switched path is sequentially determined based on the delay time of the fixed path. Calculation is one feature.

FIG. 4 is a timing chart for specifically explaining the phase error measuring function of the delay signal generator 100 of FIG. Hereinafter, a method of calculating a phase error of a path including different delay elements based on outputs of the variable delay unit 16 and the variable delay unit 90 will be described. It should be noted that the variable delay unit 18 can also calculate the phase error between paths including different delay elements using the method described below.

In FIG. 4, the upper part shows the delay set points of the delay signals to be output by the variable delay units 16 and 90.
The middle part represents the actual output timing of the variable delay unit 16, and the lower part represents the actual output timing of the variable delay unit 90. In the timing chart, the upward arrow indicates the leading edge of the delay signal actually output from the variable delay unit 16 or 90. For convenience of explanation, each delay signal is specified by a number in the figure. The underlined time in the timing chart indicates a delay time obtained by switching delay elements. Hereinafter, with reference to FIG. 3, the delay set points T1 (= 1 ns), T2 (= 5 ns), T3 (=
7 ns), T4 (= 9 ns) and T5 (= 11 ns)
Now, a method of switching one of the two delay elements including the variable delay unit 16 or 90 and calculating a phase error of a path including different delay elements will be described. FIG.
, Each of the delay elements N1 to Nn is 4 · (n−1) n
s design delay amount.

First, the phase difference P0 between the outputs of the variable delay unit 16 and the variable delay unit 90 when the delay time T1 (= 1 ns) is realized based on the delay setting data is measured. The selection units 12 and 80 select the first delay signal output from the delay element N1 having the design delay amount 0. Each of the variable delay units 16 and 90 converts the first delay signal from the reference signal by 1
Delay based on the delay setting data so as to delay by ns. As a result, the delay signal output from the variable delay unit 16 is generated with a delay time of 1 ns, and the delay signal output from the variable delay unit 90 is generated with a delay time of 0.99 ns. . Therefore, the phase difference P0 between the output of the variable delay unit 16 and the output of the variable delay unit 90 is measured as P0 = (1−0.99) = 0.01 ns.

Subsequently, the variable delay unit 16 for realizing the delay time T2 (= 5 ns) based on the delay setting data
The method for calculating the phase error M1 at the output of the above will be described. The selection unit 12 switches the delay element and selects the second delay signal output from the delay element N2 having the design delay amount of 4 ns. The selector 80 selects the first delay signal output from the delay element N1 without switching the delay element. The variable delay unit 16 converts the second delay signal from the reference signal by 5 ns.
Is delayed based on the delay setting data. Further, the variable delay unit 90 delays the first delay signal based on the delay setting data so as to be delayed by 5 ns from the reference signal.

The variable delay unit 90 outputs the delayed signal
ns, and generates a delayed signal having a delay time of 4.99 ns. If the delayed signal maintains an ideal phase difference (4 ns) from the delayed signal, (1 + 4) = 5 ns
Must be generated with a delay of However, actually, the delay elements of the path including the variable delay unit 16 are changed from N1 to N1.
By switching to 2, the delayed signal is 4.85 ns
Is generated with a delay time of This error is mainly due to the difference between the environment when the delay setting data is obtained and the environment when measuring the phase error which is equal to the actual operation of the delay signal generating apparatus 100, and the voltage and temperature fluctuations cause the delay element N1 This is caused by the difference in the operation rate of N2. The comparing unit 82 compares the phase of the output of the variable delay unit 16 with the phase of the output of the variable delay unit 90, and measures the phase difference P1. Phase difference P
1 is measured as P1 = (4.85-4.99) =-0.14 ns.

At this time, in the output of the variable delay unit 16, the phase error M1 between the path including the delay element N1 and the path including the delay element N2 is: M1 = P1-P0 = (-0.14-0.01) ns = -0.15ns Is calculated. As described above, the phase error M1 is calculated based on the measured phase difference P1 and the phase difference P0 that is an offset between the variable delay unit 16 and the variable delay unit 90. The sign of the phase error M (2m-1) of the output of the variable delay unit 16 indicates whether the phase is delayed or advanced with respect to the delayed signal.
In this embodiment, the sign "-" indicates that the phase is advanced, and the sign "+" indicates that the phase is delayed. Therefore, at this time, it is calculated that the phase of the delay signal is ahead of the reference delay signal by 0.15 ns.

Subsequently, the variable delay unit 90 for realizing the delay time T3 (= 7 ns) based on the delay setting data.
The method for calculating the phase error M2 in the output of the above will be described. The selector 12 selects the second delay signal output from the delay element N2 having the design delay amount of 4 ns without switching the delay element. The selector 80 switches the delay element and selects the second delay signal output from the delay element N2. The variable delay unit 16 converts the second delay signal from the reference signal by 7 ns.
Is delayed based on the delay setting data. Further, the variable delay unit 90 delays the second delay signal based on the delay setting data so as to be delayed by 7 ns from the reference signal.

The variable delay section 16 converts the delayed signal into two
ns, and generates a delay signal having a delay time of 6.85 ns. If the delayed signal maintains an ideal phase difference (6 ns) from the delayed signal, (0.99 + 6) = 6.99
It needs to be generated with a delay of ns. However, actually, by switching the delay element of the path including the variable delay unit 90 from N1 to N2, the delay signal becomes 6.75.
ns with a delay time of ns. This error is
Mainly, since the environment when the delay setting data is obtained is different from the environment when measuring the phase error which is equal to the actual operation of the delay signal generating apparatus 100, the operating rates of the delay elements N1 and N2 are changed by the voltage and temperature fluctuations. Are different. The comparing unit 82 compares the phase of the output of the variable delay unit 16 with the phase of the output of the variable delay unit 90, and measures the phase difference P2. The phase difference P2 is measured as P2 = (6.85-6.75) = 0.1 ns.

At this time, in the output of the variable delay unit 90, the phase error M2 between the path including the delay element N1 and the path including the delay element N2 is M2 = P2-M1-P0 = (0.1 − (− 0.15) −0.01 ) Ns =
It is calculated as 0.24 ns. Thus, the phase error M2 is the phase difference P
2 and P0 and the phase error M1. The sign of the phase error M (2m) of the output of the variable delay unit 90 is
Indicates whether the phase is delayed or advanced with respect to the delayed signal. In this embodiment, the sign "+" indicates that the phase is advanced, and the sign "-" indicates that the phase is delayed. Therefore, at this time, it is calculated that the phase of the delay signal is ahead of the reference delay signal by 0.24 ns.

Subsequently, the variable delay unit 16 for realizing the delay time T4 (= 9 ns) based on the delay setting data.
A method for calculating the phase error M3 in the output of the above will be described. The selection unit 12 switches the delay element, and selects the third delay signal output from the delay element N3 having the design delay amount of 8 ns. The selector 80 selects the second delay signal output from the delay element N2 without switching the delay element. The variable delay unit 16 converts the third delay signal from the reference signal by 9 ns.
Is delayed based on the delay setting data. Further, the variable delay unit 90 delays the second delay signal based on the delay setting data so as to be delayed by 9 ns from the reference signal.

The variable delay unit 90 converts the delayed signal into two
ns to generate a delayed signal having a delay time of 8.75 ns. If the ideal phase difference (8 ns) from the delay signal is maintained, (1 + 8) = 9 ns
Must be generated with a delay of However, actually, the delay elements of the path including the variable delay unit 16 are changed from N2 to N
3, the delay signal becomes 9.02 ns.
Is generated with a delay time of This error is mainly caused by the fluctuation of the voltage and temperature, the delay elements N2 and N3
Are caused by different operating rates of The comparison unit 82
The phase of the output of the variable delay unit 16 is compared with the phase of the output of the variable delay unit 90, and the phase difference P3 is measured. The phase difference P3 is measured as P3 = (9.02-8.75) = 0.27 ns.

At this time, in the output of the variable delay unit 16, the phase error M3 between the path including the delay element N1 and the path including the delay element N3 is M3 = P3-M2-P0 = (0.27−0.24−0.01) ns = 0.0
It is calculated as 2 ns. Thus, the phase error M3 is the phase difference P
3 and P0 and the phase error M2. Therefore, at this time, it is calculated that the phase of the delay signal is delayed by 0.02 ns with respect to the delay signal.

Subsequently, the variable delay unit 9 for realizing the delay time T5 (= 11 ns) based on the delay setting data
A method for calculating the phase error M4 at the output of 0 will be described. The selector 12 selects the third delay signal output from the delay element N3 having the design delay amount of 8 ns without switching the delay element. The selector 80 switches the delay element,
The third delay signal output from the delay element N3 is selected.
The variable delay unit 16 converts the third delay signal from the reference signal by 11
Delay based on the delay setting data so as to delay by ns. Further, the variable delay unit 90 delays the third delay signal based on the delay setting data so as to be delayed by 11 ns from the reference signal.

The variable delay section 16 outputs the delayed signal
ns to generate a delay signal having a delay time of 11.02 ns. If the ideal phase difference (10 ns) from the delay signal is maintained, the delay signal 10 becomes (0.99 + 10)
= 10.99 ns delay. In this example, the delayed signal 10 is actually the ideal 10.99 ns
Has a delay time of The comparing unit 82 includes the variable delay unit 1
6 is compared with the output of the variable delay unit 90, and the phase difference P4 is measured. The phase difference P4 is measured as P4 = (11.02-10.99) = 0.03 ns.

At this time, in the output of the variable delay unit 90, the phase error M4 between the path including the delay element N1 and the path including the delay element N3 is M4 = P4-M3-P0 = (0.03-0.02-0.01) ns = 0
ns. Thus, the phase error M4 is equal to the phase difference P
4 and P0 and the phase error M3. From this calculation result, it can be seen that the phase of the path including the delay element N3 matches the phase of the path including the delay element N1.

As is clear from the above, the phase error of the path when the delay element is switched is calculated based on the measured phase difference P. When the phase error M0 at the time T1 is set to 0, the phase error Mn is calculated based on a calculation formula of Mn = Pn−Mn−1−P0.

As described with reference to FIGS. 3 and 4, according to the present invention, the relative phase error between the two delay paths can be obtained in the environment of the actual operation of delay signal generating apparatus 100. . Therefore, inside the delay signal generation device 100, an accurate delay signal can be generated based on the relative phase reference. In the semiconductor test device 60, the plurality of delay signal generation devices 100
The phase difference from the absolute phase reference is measured in advance. The plurality of delay signal generation devices 100 can output delay signals with uniform skew based on the phase difference from the absolute phase reference and the phase error obtained by the present invention.

As is apparent from the above description, according to the present invention, there is provided a delay signal generating apparatus capable of adjusting a delay amount of predetermined delay setting data in an environment at the time of actual operation of the apparatus. be able to. As described above, the present invention has been described using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is apparent to those skilled in the art that various changes or improvements can be made to the above embodiment. It is apparent from the description of the appended claims that embodiments with such modifications or improvements are also included in the technical scope of the present invention.

[0068]

According to the present invention, it is possible to provide a delay signal generating apparatus for generating a delay signal having an accurate delay amount.

[Brief description of the drawings]

FIG. 1 shows a conventional delay signal generation device 50 used in a semiconductor test device 60.

FIG. 2 is a block diagram of a semiconductor test apparatus 60 that tests a device under test 62.

FIG. 3 shows a part of the configuration of a delay signal generation device 100 in the semiconductor test device 60.

FIG. 4 is a timing chart for specifically explaining a phase error measurement function of the delay signal generation device 100.

[Explanation of symbols]

10 delay unit, 12, 14 selection unit, 16, 1
8 ... variable delay unit, 20 ... signal switching unit, 22 ...
.Period measurement unit, 24, 28, 34 ... AND gate,
26, 30, 36: OR gate, 32: Loop forming unit, 50: Delay signal generator, 52: Pattern generator, 54: Waveform shaper, 56: Signal input Output unit, 58 ... Output determination unit, 60 ... Semiconductor test apparatus, 62 ... Device under test, 66 ... Timing generator, 70, 72, 92 ... Selection signal supply unit, 7
4, 76, 78: delay amount adjusting unit, 80: selecting unit, 82: comparing unit, 84: determining unit, 86 ...
Error calculation unit, 90: variable delay unit, 92: selection signal supply unit, 94: output port, 100: delay signal generation device

Claims (12)

[Claims] A delay unit that delays an input reference signal by different times and has a plurality of delay elements that output a plurality of delay signals; and a first unit that selects one delay signal from the plurality of delay signals. A selection unit; a first variable delay unit that can delay the delay signal selected by the first selection unit by a desired delay time; and a second unit that selects one of the plurality of delay signals. A second selection unit; a second variable delay unit that can delay the delay signal selected by the second selection unit by a desired delay time; an output of the first variable delay unit and the second variable delay A comparison unit that compares the phases of the outputs of the units; and an error calculation unit that calculates a phase error of the output of the first variable delay unit or the output of the second variable delay unit based on the comparison result in the comparison unit. To the phase error Zui, the delay signal generating apparatus characterized by comprising a delay amount adjusting unit that adjusts the delay amount of the first variable delay unit and the second variable delay unit. 2. A delay signal generating apparatus comprising: a delay section having a plurality of delay elements for outputting a plurality of delay signals obtained by delaying an input reference signal by different times, wherein the reference signal is output for a plurality of predetermined times. A delay amount adjusting method for adjusting a delay amount based on predetermined delay setting data so as to delay, selecting a first delay signal output from a first delay element that is one of the plurality of delay elements. A first selection step; a first delay step of delaying the first delay signal selected in the first selection step based on the delay setting data so as to be delayed from the reference signal by a predetermined first time; A second selection step of selecting the first delay signal output from the first delay element, and a first delay signal selected in the second selection step, A second delay step of delaying based on the delay setting data so as to be delayed by a predetermined first time from a reference signal; a phase of the first delay signal delayed in the first delay step; Comparing a phase of the first delay signal delayed in the step to measure a first phase difference; and determining a delay amount based on the delay setting data based on a comparison result in the first comparison step. Adjusting the amount of delay. 3. A third selection step of selecting a second delay signal output from a second delay element, which is one of the plurality of delay elements, and the second delay signal selected in the third selection step A third delay step based on the delay setting data so that the first delay signal is delayed from the reference signal by a predetermined second time; and a fourth step of selecting the first delay signal output from the first delay element. A selecting step; a fourth delaying step of delaying the first delay signal selected in the fourth selecting step based on the delay setting data so as to be delayed from the reference signal by a predetermined second time; The phase of the second delay signal delayed in the third delay step is compared with the phase of the first delay signal delayed in the fourth delay step, and a second phase difference is calculated. Using the comparison result in the second comparison step, the first delay signal delayed in the first delay step, and the second delay signal delayed in the third delay step A first calculating step of calculating a first phase error of the signal; and a step of adjusting a delay amount based on the delay setting data based on the first phase error calculated in the first calculating step. 3. The delay amount adjusting method according to claim 2, wherein 4. The method according to claim 1, wherein the first calculating step is performed based on the first phase difference measured in the first comparing step and the second phase difference measured in the second comparing step. The method according to claim 3, further comprising calculating an error. 5. A fifth selection step of selecting the second delay signal output from the second delay element, and a step of: converting the second delay signal selected in the fifth selection step from the reference signal to a predetermined value. A fifth delay step of delaying based on the delay setting data so as to be delayed by a third time, a sixth selection step of selecting the second delay signal output from the second delay element, and a sixth selection step A sixth delay step of delaying the second delay signal selected in the step based on the delay setting data so as to be delayed by a predetermined third time from the reference signal; and a delay in the fifth delay step. A third comparing step of comparing a phase of the second delay signal with a phase of the second delay signal delayed in the sixth delay step to measure a third phase difference; And a second phase error between the first delay signal delayed in the second delay step and the second delay signal delayed in the sixth delay step using the comparison result in the third comparison step. The method according to claim 4, further comprising: a second calculating step of calculating a second phase error; and a step of adjusting a delay amount based on the delay setting data based on the second phase error calculated in the second calculating step. The described delay amount adjustment method. 6. The method according to claim 6, wherein the second calculating step includes a step of calculating the second phase error based on the third phase difference measured in the third comparing step and the first phase error. 6. The delay amount adjusting method according to claim 5, wherein: 7. A delay section having a plurality of delay elements for outputting a plurality of delay signals obtained by delaying an input reference signal by different times, and a first section for selecting one of the plurality of delay signals. A selection unit, a first variable delay unit that can delay the delay signal selected by the first selection unit by a desired delay time, and a second unit that selects one delay signal from the plurality of delay signals. 2 selecting unit, and the second
And a second variable delay unit capable of delaying the delay signal selected by the selection unit by a desired delay time, wherein the reference signal is delayed by a plurality of predetermined times. A delay amount adjusting method for adjusting a delay amount according to delay setting data of the determined first variable delay unit or the second variable delay unit, wherein the first selector is one of the plurality of delay elements. A first for selecting a first delay signal output from a certain first delay element
A selecting step; wherein the first variable delay unit selects the first variable delay unit selected in the first selecting step based on the delay setting data.
A first delay step of delaying the delay signal so as to be delayed by a predetermined first time from the reference signal; and a second step in which the second selector selects the first delay signal output from the first delay element. A second selecting step, wherein the second variable delay unit selects the first variable selected in the second selecting step based on the delay setting data.
A second delay step of delaying the delay signal so as to be delayed by a predetermined first time from the reference signal; a phase of the first delay signal delayed in the first delay step; and a delay in the second delay step A first comparing step of measuring a first phase difference by comparing a phase of the first delayed signal thus obtained, and adjusting a delay amount based on the delay setting data based on a comparison result in the first comparing step. And a delay amount adjusting method. 8. A third selecting step in which the first selecting section selects a second delay signal output from a second delay element, which is one of the plurality of delay elements, and wherein the first variable delay section includes: , The second selected in the third selecting step based on the delay setting data.
A third delay step of delaying the delay signal so as to be delayed by a predetermined second time from the reference signal; and a second step of selecting the first delay signal output from the first delay element by the second selector. A fourth selecting step, wherein the second variable delay unit selects the first variable selected in the fourth selecting step based on the delay setting data.
A fourth delay step of delaying the delay signal so as to be delayed by a predetermined second time from the reference signal, a phase of the second delay signal delayed in the third delay step, and a delay in the fourth delay step A second comparing step of comparing a phase of the obtained first delayed signal to measure a second phase difference; a measuring step of the first phase difference measured in the first comparing step; and a measuring step of the second comparing step. Calculating a first phase error between the first delay signal delayed in the first delay step and the second delay signal delayed in the third delay step, based on the second phase difference thus obtained; 1 calculation step; and adjusting a delay amount based on the delay setting data based on the first phase error calculated in the first calculation step. Delay adjusting method according to claim 7, characterized in. 9. A fifth selection step in which the first selection unit selects the second delay signal output from the second delay element, and wherein the first variable delay unit determines the second delay signal based on the delay setting data. The second selected in the fifth selecting step.
A fifth delay step of delaying the delay signal so as to be delayed by a predetermined third time from the reference signal; and a second step in which the second selector selects the second delay signal output from the second delay element. And the second variable delay unit selects the second variable delay unit selected in the sixth selection step based on the delay setting data.
A sixth delay step of delaying the delay signal so as to be delayed by a predetermined third time from the reference signal; a phase of the second delay signal delayed in the fifth delay step; and a delay in the sixth delay step Comparing the phase of the second delayed signal thus obtained to measure a third phase difference, based on the third phase difference measured in the third comparing step, and the first phase error. The first delay signal delayed in the second delay step;
A second calculation step of calculating a second phase error of the second delay signal delayed in the delay step, and a delay amount based on the delay setting data based on the second phase error calculated in the second calculation step Adjusting the delay time. 9. The method according to claim 8, further comprising the step of: 10. A delay signal generating apparatus including a delay unit having a plurality of delay elements for outputting a plurality of delay signals obtained by delaying an input reference signal by different times, wherein the reference signal is output for a plurality of predetermined times. A phase error calculation method for calculating a phase error between two delayed signals passing through different delay elements, which has been delayed based on delay setting data predetermined to be delayed, wherein one of the plurality of delay elements is used. A first selection step of selecting a first delay signal output from a certain first delay element; and delaying the first delay signal selected in the first selection step by a predetermined first time from the reference signal. A first delay step of delaying based on the delay setting data; a second selecting step of selecting the first delay signal output from the first delay element; A second delay step of delaying the first delay signal selected in the second selection step based on the delay setting data so as to be delayed by a predetermined first time from the reference signal; A first comparing step of measuring a first phase difference by comparing a phase of the delayed first delay signal with a phase of the first delayed signal delayed in the second delay step. Phase error calculation method. 11. The second delay element being one of the plurality of delay elements.
A third selection step of selecting a second delay signal output from the delay element, and the second delay signal selected in the third selection step is delayed from the reference signal by a predetermined second time. A third delay step of delaying based on delay setting data, a fourth selection step of selecting the first delay signal output from the first delay element, and the first delay selected in the fourth selection step A fourth delay step of delaying the signal based on the delay setting data so as to delay the signal by a predetermined second time from the reference signal; and a phase of the second delay signal delayed in the third delay step; A second comparing step of comparing a phase of the first delay signal delayed in the fourth delay step and measuring a second phase difference; and the first comparing step. Based on the first phase difference measured in step (a) and the second phase difference measured in the second comparing step, the first delay signal delayed in the first delay step, and the third delay step 11. The phase error calculation method according to claim 10, further comprising: a first calculation step of calculating a first phase error of the second delay signal delayed in step (a). 12. A fifth selection step of selecting the second delay signal output from the second delay element, and a step of converting the second delay signal selected in the fifth selection step from the reference signal to a predetermined value. A fifth delay step of delaying based on the delay setting data so as to be delayed by a third time, a sixth selection step of selecting the second delay signal output from the second delay element, and a sixth selection step A sixth delay step of delaying the second delay signal selected in the step based on the delay setting data so as to be delayed by a predetermined third time from the reference signal; and a delay in the fifth delay step. A third comparing step of measuring a third phase difference by comparing a phase of the second delay signal with a phase of the second delay signal delayed in the sixth delay step; And flop, and the third phase difference measured in the third comparison step, based on said first phase error, and the first delay signal delayed in the second delay step, the sixth
12. The phase error calculation method according to claim 11, further comprising: a second calculation step of calculating a second phase error of the second delay signal delayed in the delay step.