JP2001102751A - Multilayer printed wiring board and manufacturing method thereof - Google Patents
Multilayer printed wiring board and manufacturing method thereofInfo
- Publication number
- JP2001102751A JP2001102751A JP27677699A JP27677699A JP2001102751A JP 2001102751 A JP2001102751 A JP 2001102751A JP 27677699 A JP27677699 A JP 27677699A JP 27677699 A JP27677699 A JP 27677699A JP 2001102751 A JP2001102751 A JP 2001102751A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- film
- wiring board
- printed wiring
- multilayer printed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 229920005989 resin Polymers 0.000 claims abstract description 182
- 239000011347 resin Substances 0.000 claims abstract description 182
- 239000004020 conductor Substances 0.000 claims abstract description 70
- 239000011810 insulating material Substances 0.000 claims abstract description 45
- 238000010438 heat treatment Methods 0.000 claims abstract description 41
- 238000003825 pressing Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims description 75
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 16
- 229920005672 polyolefin resin Polymers 0.000 claims description 16
- 239000003822 epoxy resin Substances 0.000 claims description 13
- 229920000647 polyepoxide Polymers 0.000 claims description 13
- 229920001187 thermosetting polymer Polymers 0.000 claims description 8
- 239000011342 resin composition Substances 0.000 claims description 5
- 239000004593 Epoxy Substances 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 230000035515 penetration Effects 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 99
- 238000007747 plating Methods 0.000 description 46
- 239000011229 interlayer Substances 0.000 description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 22
- 238000007772 electroless plating Methods 0.000 description 21
- 239000011162 core material Substances 0.000 description 20
- 239000010949 copper Substances 0.000 description 18
- 238000010586 diagram Methods 0.000 description 18
- 229910052802 copper Inorganic materials 0.000 description 17
- 239000007864 aqueous solution Substances 0.000 description 16
- 229910000679 solder Inorganic materials 0.000 description 14
- 239000003054 catalyst Substances 0.000 description 13
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- 239000000243 solution Substances 0.000 description 11
- 230000000052 comparative effect Effects 0.000 description 10
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 9
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 9
- 238000009713 electroplating Methods 0.000 description 9
- 239000000945 filler Substances 0.000 description 9
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 9
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000000203 mixture Substances 0.000 description 8
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 7
- 239000001569 carbon dioxide Substances 0.000 description 6
- 229910002092 carbon dioxide Inorganic materials 0.000 description 6
- 150000001925 cycloalkenes Chemical class 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- RAXXELZNTBOGNW-UHFFFAOYSA-N imidazole Natural products C1=CNC=N1 RAXXELZNTBOGNW-UHFFFAOYSA-N 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- JUWOETZNAMLKMG-UHFFFAOYSA-N [P].[Ni].[Cu] Chemical compound [P].[Ni].[Cu] JUWOETZNAMLKMG-UHFFFAOYSA-N 0.000 description 5
- 239000011889 copper foil Substances 0.000 description 5
- 239000000178 monomer Substances 0.000 description 5
- KWSLGOVYXMQPPX-UHFFFAOYSA-N 5-[3-(trifluoromethyl)phenyl]-2h-tetrazole Chemical compound FC(F)(F)C1=CC=CC(C2=NNN=N2)=C1 KWSLGOVYXMQPPX-UHFFFAOYSA-N 0.000 description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 4
- 229910000365 copper sulfate Inorganic materials 0.000 description 4
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 229910001379 sodium hypophosphite Inorganic materials 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 239000004094 surface-active agent Substances 0.000 description 4
- ZWEHNKRNPOVVGH-UHFFFAOYSA-N 2-Butanone Chemical compound CCC(C)=O ZWEHNKRNPOVVGH-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 description 3
- 239000004327 boric acid Substances 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- LGQLOGILCSXPEA-UHFFFAOYSA-L nickel sulfate Chemical compound [Ni+2].[O-]S([O-])(=O)=O LGQLOGILCSXPEA-UHFFFAOYSA-L 0.000 description 3
- 229910000363 nickel(II) sulfate Inorganic materials 0.000 description 3
- 229920003986 novolac Polymers 0.000 description 3
- 150000007524 organic acids Chemical class 0.000 description 3
- 230000033116 oxidation-reduction process Effects 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 239000011734 sodium Substances 0.000 description 3
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 2
- LCPVQAHEFVXVKT-UHFFFAOYSA-N 2-(2,4-difluorophenoxy)pyridin-3-amine Chemical compound NC1=CC=CN=C1OC1=CC=C(F)C=C1F LCPVQAHEFVXVKT-UHFFFAOYSA-N 0.000 description 2
- QTWJRLJHJPIABL-UHFFFAOYSA-N 2-methylphenol;3-methylphenol;4-methylphenol Chemical compound CC1=CC=C(O)C=C1.CC1=CC=CC(O)=C1.CC1=CC=CC=C1O QTWJRLJHJPIABL-UHFFFAOYSA-N 0.000 description 2
- VVBLNCFGVYUYGU-UHFFFAOYSA-N 4,4'-Bis(dimethylamino)benzophenone Chemical compound C1=CC(N(C)C)=CC=C1C(=O)C1=CC=C(N(C)C)C=C1 VVBLNCFGVYUYGU-UHFFFAOYSA-N 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 2
- NLXLAEXVIDQMFP-UHFFFAOYSA-N Ammonia chloride Chemical compound [NH4+].[Cl-] NLXLAEXVIDQMFP-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- AEMRFAOFKBGASW-UHFFFAOYSA-N Glycolic acid Chemical compound OCC(O)=O AEMRFAOFKBGASW-UHFFFAOYSA-N 0.000 description 2
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 2
- 229910001096 P alloy Inorganic materials 0.000 description 2
- WCUXLLCKKVVCTQ-UHFFFAOYSA-M Potassium chloride Chemical compound [Cl-].[K+] WCUXLLCKKVVCTQ-UHFFFAOYSA-M 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 2
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 2
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical compound C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 description 2
- PXKLMJQFEQBVLD-UHFFFAOYSA-N bisphenol F Chemical compound C1=CC(O)=CC=C1CC1=CC=C(O)C=C1 PXKLMJQFEQBVLD-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229920001577 copolymer Polymers 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- 229930003836 cresol Natural products 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 239000012774 insulation material Substances 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- JFNLZVQOOSMTJK-KNVOCYPGSA-N norbornene Chemical compound C1[C@@H]2CC[C@H]1C=C2 JFNLZVQOOSMTJK-KNVOCYPGSA-N 0.000 description 2
- 239000007800 oxidant agent Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- PIBWKRNGBLPSSY-UHFFFAOYSA-L palladium(II) chloride Chemical compound Cl[Pd]Cl PIBWKRNGBLPSSY-UHFFFAOYSA-L 0.000 description 2
- 239000003504 photosensitizing agent Substances 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229920003192 poly(bis maleimide) Polymers 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- 229910052708 sodium Inorganic materials 0.000 description 2
- 239000001509 sodium citrate Substances 0.000 description 2
- NLJMYIDDQXHKNR-UHFFFAOYSA-K sodium citrate Chemical compound O.O.[Na+].[Na+].[Na+].[O-]C(=O)CC(O)(CC([O-])=O)C([O-])=O NLJMYIDDQXHKNR-UHFFFAOYSA-K 0.000 description 2
- CHQMHPLRPQMAMX-UHFFFAOYSA-L sodium persulfate Substances [Na+].[Na+].[O-]S(=O)(=O)OOS([O-])(=O)=O CHQMHPLRPQMAMX-UHFFFAOYSA-L 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- UMGDCJDMYOKAJW-UHFFFAOYSA-N thiourea Chemical compound NC(N)=S UMGDCJDMYOKAJW-UHFFFAOYSA-N 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- NECRQCBKTGZNMH-UHFFFAOYSA-N 3,5-dimethylhex-1-yn-3-ol Chemical compound CC(C)CC(C)(O)C#C NECRQCBKTGZNMH-UHFFFAOYSA-N 0.000 description 1
- ROFVEXUMMXZLPA-UHFFFAOYSA-N Bipyridyl Chemical group N1=CC=CC=C1C1=CC=CC=N1 ROFVEXUMMXZLPA-UHFFFAOYSA-N 0.000 description 1
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 1
- 229910000570 Cupronickel Inorganic materials 0.000 description 1
- KCXVZYZYPLLWCC-UHFFFAOYSA-N EDTA Chemical compound OC(=O)CN(CC(O)=O)CCN(CC(O)=O)CC(O)=O KCXVZYZYPLLWCC-UHFFFAOYSA-N 0.000 description 1
- 241000196324 Embryophyta Species 0.000 description 1
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 description 1
- 239000005977 Ethylene Substances 0.000 description 1
- WSFSSNUMVMOOMR-UHFFFAOYSA-N Formaldehyde Chemical compound O=C WSFSSNUMVMOOMR-UHFFFAOYSA-N 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 229910018104 Ni-P Inorganic materials 0.000 description 1
- 229910021586 Nickel(II) chloride Inorganic materials 0.000 description 1
- 229910018536 Ni—P Inorganic materials 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- XSQUKJJJFZCRTK-UHFFFAOYSA-N Urea Natural products NC(N)=O XSQUKJJJFZCRTK-UHFFFAOYSA-N 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 125000000539 amino acid group Chemical group 0.000 description 1
- 235000019270 ammonium chloride Nutrition 0.000 description 1
- 239000002518 antifoaming agent Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- RWCCWEUUXYIKHB-UHFFFAOYSA-N benzophenone Chemical compound C=1C=CC=CC=1C(=O)C1=CC=CC=C1 RWCCWEUUXYIKHB-UHFFFAOYSA-N 0.000 description 1
- 239000012965 benzophenone Substances 0.000 description 1
- 125000002915 carbonyl group Chemical group [*:2]C([*:1])=O 0.000 description 1
- KRVSOGSZCMJSLX-UHFFFAOYSA-L chromic acid Substances O[Cr](O)(=O)=O KRVSOGSZCMJSLX-UHFFFAOYSA-L 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 239000008139 complexing agent Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 229910001431 copper ion Inorganic materials 0.000 description 1
- YOCUPQPZWBBYIX-UHFFFAOYSA-N copper nickel Chemical compound [Ni].[Cu] YOCUPQPZWBBYIX-UHFFFAOYSA-N 0.000 description 1
- VFFQCUJVGMRYIF-UHFFFAOYSA-N copper;1h-imidazole Chemical compound [Cu+2].C1=CNC=N1 VFFQCUJVGMRYIF-UHFFFAOYSA-N 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 229960003280 cupric chloride Drugs 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- ISDDBQLTUUCGCZ-UHFFFAOYSA-N dipotassium dicyanide Chemical compound [K+].[K+].N#[C-].N#[C-] ISDDBQLTUUCGCZ-UHFFFAOYSA-N 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004453 electron probe microanalysis Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- AWJWCTOOIBYHON-UHFFFAOYSA-N furo[3,4-b]pyrazine-5,7-dione Chemical compound C1=CN=C2C(=O)OC(=O)C2=N1 AWJWCTOOIBYHON-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229920001519 homopolymer Polymers 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- XEMZLVDIUVCKGL-UHFFFAOYSA-N hydrogen peroxide;sulfuric acid Chemical compound OO.OS(O)(=O)=O XEMZLVDIUVCKGL-UHFFFAOYSA-N 0.000 description 1
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 1
- GQZXNSPRSGFJLY-UHFFFAOYSA-N hydroxyphosphanone Chemical compound OP=O GQZXNSPRSGFJLY-UHFFFAOYSA-N 0.000 description 1
- 229940005631 hypophosphite ion Drugs 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 125000000896 monocarboxylic acid group Chemical group 0.000 description 1
- QMMRZOWCJAIUJA-UHFFFAOYSA-L nickel dichloride Chemical compound Cl[Ni]Cl QMMRZOWCJAIUJA-UHFFFAOYSA-L 0.000 description 1
- 229910001453 nickel ion Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- ZMLDXWLZKKZVSS-UHFFFAOYSA-N palladium tin Chemical compound [Pd].[Sn] ZMLDXWLZKKZVSS-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- JRKICGRDRMAZLK-UHFFFAOYSA-L peroxydisulfate Chemical compound [O-]S(=O)(=O)OOS([O-])(=O)=O JRKICGRDRMAZLK-UHFFFAOYSA-L 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 230000002165 photosensitisation Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- -1 polytetrafluoroethylene Polymers 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 239000001103 potassium chloride Substances 0.000 description 1
- 235000011164 potassium chloride Nutrition 0.000 description 1
- USHAGKDGDHPEEY-UHFFFAOYSA-L potassium persulfate Chemical compound [K+].[K+].[O-]S(=O)(=O)OOS([O-])(=O)=O USHAGKDGDHPEEY-UHFFFAOYSA-L 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- QQONPFPTGQHPMA-UHFFFAOYSA-N propylene Natural products CC=C QQONPFPTGQHPMA-UHFFFAOYSA-N 0.000 description 1
- 125000004805 propylene group Chemical group [H]C([H])([H])C([H])([*:1])C([H])([H])[*:2] 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000005361 soda-lime glass Substances 0.000 description 1
- SUKJFIGYRHOWBL-UHFFFAOYSA-N sodium hypochlorite Chemical compound [Na+].Cl[O-] SUKJFIGYRHOWBL-UHFFFAOYSA-N 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 230000002194 synthesizing effect Effects 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- NCPXQVVMIXIKTN-UHFFFAOYSA-N trisodium;phosphite Chemical compound [Na+].[Na+].[Na+].[O-]P([O-])[O-] NCPXQVVMIXIKTN-UHFFFAOYSA-N 0.000 description 1
- 238000004876 x-ray fluorescence Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、多層プリント配線
板およびその製造方法に関し、特に、耐ヒートサイクル
特性に優れる多層プリント配線板について提案する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board and a method for manufacturing the same, and more particularly, to a multilayer printed wiring board having excellent heat cycle resistance.
【０００２】[0002]
【従来の技術】近年、多層配線基板の高密度化という要
請から、いわゆるビルドアップ多層配線基板が注目され
ている。このビルドアップ多層配線基板は、例えば特公
平４−55555 号公報に開示されているような方法により
製造される。即ち、コア基板上に、感光性の無電解めっ
き用接着剤からなる絶縁材を塗布し、これを乾燥したの
ち露光現像することにより、バイアホール用開口を有す
る層間絶縁材層を形成し、次いで、この層間絶縁材層の
表面を酸化剤等による処理にて粗化したのち、その粗化
面にめっきレジストを設け、その後、レジスト非形成部
分に無電解めっきを施してバイアホール、導体回路を形
成し、このような工程を複数回繰り返すことにより、多
層化したビルドアップ配線基板が得られる。このような
多層プリント配線板では、コア基板にスルーホールを設
けて内層の導体回路どうしを接続することにより、更な
る多層化を図ることができる。コア基板にスルーホール
を有するこの種の多層プリント配線板では、まず、コア
基板にスルーホールを含む内層導体回路を形成し、次い
で、スルーホールの内壁面および内層導体回路表面に酸
化還元処理による粗化層を設けてから、該スルーホール
内に樹脂充填剤を充填するとともに内層導体回路間の凹
部にも樹脂充填材を充填し、研磨により基板表面を平坦
化した後、インタープレート（荏原ユージライト社製の
銅-ニッケル-リンからなる合金めっき）などによる粗化
めっきを施して、その上に、樹脂絶縁剤を塗布またはシ
ート状にして貼付けることによって層間樹脂絶縁層を形
成していた。2. Description of the Related Art In recent years, so-called build-up multilayer wiring boards have been receiving attention due to a demand for higher density of the multilayer wiring boards. This build-up multilayer wiring board is manufactured by a method disclosed in, for example, Japanese Patent Publication No. 4-55555. That is, on the core substrate, an insulating material made of a photosensitive electroless plating adhesive is applied, and dried and then exposed and developed to form an interlayer insulating material layer having a via hole opening, After roughening the surface of the interlayer insulating material layer by treatment with an oxidizing agent or the like, a plating resist is provided on the roughened surface, and then electroless plating is performed on a non-resist forming portion to form a via hole and a conductor circuit. By forming and repeating such steps a plurality of times, a multilayered build-up wiring board can be obtained. In such a multilayer printed wiring board, further multilayering can be achieved by providing through holes in the core substrate and connecting the conductor circuits in the inner layers. In this type of multilayer printed wiring board having a through hole in a core substrate, first, an inner layer conductor circuit including the through hole is formed in the core substrate, and then the inner wall surface of the through hole and the surface of the inner layer conductor circuit are roughened by oxidation-reduction treatment. After the passivation layer is provided, the through holes are filled with a resin filler and the recesses between the inner conductor circuits are also filled with the resin filler, and the surface of the substrate is flattened by polishing. Rough plating such as an alloy plating made of copper-nickel-phosphorus manufactured by Nissan Co., Ltd. is performed, and a resin insulating agent is applied on the roughened plating or bonded in a sheet shape to form an interlayer resin insulating layer.
【発明が解決しようとする課題】しかしながら、このよ
うな方法においては、、スルーホール内への樹脂充填
と、内層導体回路間の凹部への樹脂充填および層間樹脂
絶縁層の形成とを異なる樹脂絶縁材を用いて別々な工程
によって行っていたため、その分だけ製造工程が多くな
るとともに、充填される各樹脂絶縁剤の粘度等の複雑な
管理が必要となり、結局、製造された多層プリント配線
板のコストを押し上げる原因となっていた。また、ヒー
トサイクル試験や熱衝撃などによって、各樹脂充填材と
層間樹脂絶縁層との界面において、各樹脂絶縁材と層間
樹脂絶縁材の熱膨張係数の違いに起因する剥離やクラッ
クが発生するという問題もあった。さらに、このような
方法においては、樹脂充填材を埋め込んだ後に、その樹
脂面の平坦化のために行う研磨処理によって、内層導体
回路の一部が除去されたり、また研磨処理の際の切削応
力の残留によってクラックがより発生し易くなるという
問題もあった。本発明は、従来技術が抱える上述した課
題を解決するためになされたものであり、その目的は、
ヒートサイクルなどの条件下における、樹脂充填材と層
間樹脂絶縁材の熱膨張係数の違いに起因するはがれやク
ラックの発生を阻止した多層プリント配線板およびその
製造方法を提案することにある。However, in such a method, the resin filling in the through-hole, the resin filling in the recess between the inner conductor circuits and the formation of the interlayer resin insulating layer are different from each other. Since it was performed in separate processes using materials, the number of manufacturing processes increased by that much, and complicated management such as the viscosity of each resin insulating material to be filled was necessary, and eventually the manufactured multilayer printed wiring board was This was driving up costs. In addition, due to a heat cycle test or thermal shock, at the interface between each resin filler and the interlayer resin insulation layer, peeling or cracking occurs due to a difference in thermal expansion coefficient between each resin insulation material and the interlayer resin insulation material. There were also problems. Further, in such a method, after embedding the resin filler, a part of the inner conductor circuit is removed by a polishing process performed for flattening the resin surface, or a cutting stress during the polishing process is reduced. There is also a problem that cracks are more likely to be generated due to the residue of the steel. The present invention has been made in order to solve the above-described problems of the prior art, and the object is to
An object of the present invention is to propose a multilayer printed wiring board in which peeling or cracking caused by a difference in thermal expansion coefficient between a resin filler and an interlayer resin insulating material under conditions such as a heat cycle is prevented, and a method of manufacturing the same.
【課題を解決するための手段】発明者らは、上記目的の
実現に向け鋭意研究した結果、スルーホール内へ充填さ
れる樹脂充填材および内層導体回路間の凹部へ充填され
る樹脂充填材を、層間樹脂絶縁層と同一の樹脂材料で形
成すれば、熱膨張係数の違いに起因するはがれやクラッ
クの発生を阻止できることを知見し、以下に示す内容を
要旨構成とする本発明を完成するに至った。 (1)すなわち、本発明は、コア基板の両面にそれぞれ形
成された導体回路上に、樹脂絶縁層を介して外層の導体
回路が形成され、上記コア基板の両側に位置する導体回
路間の電気的接続が、コア基板に形成されたスルーホー
ルによって行なわれるビルドアップ構造を有する多層プ
リント配線板において、上記樹脂絶縁層は、所定の加熱
条件下において軟化するような樹脂フィルムと、その樹
脂フィルムの片面に貼付けられたＢステージ樹脂とを含
むフィルム状絶縁材が加熱プレスによって形成され、ス
ルーホールランドを含む内層導体回路の側面とコア基板
の表面とで規定される凹部およびスルーホールの内壁に
よって規定される貫通穴内に充填された軟化したＢステ
ージ樹脂層と、そのＢステージ樹脂を覆った軟化した樹
脂フィルム層とが硬化されてなることを特徴とする。上
記フィルム状絶縁材を構成する樹脂フィルムとＢステー
ジ樹脂とは、同一の樹脂組成からなることが望ましい。
また、上記フィルム状絶縁材は、熱硬化性のポリオレフ
ィン系樹脂またはエポキシ系樹脂を主成分とした樹脂フ
ィルムと、５０〜８０重量％の樹脂成分からなるＢステ
ージ樹脂とを含んでいることが望ましい。 (2) また、本発明は、コア基板の両面にそれぞれ形成さ
れた導体回路上に、樹脂絶縁層を介して外層の導体回路
が形成され、上記コア基板の両側に配置された導体回路
間の電気的接続が、コア基板に形成されたスルーホール
によって行なわれるビルドアップ構造を有する多層プリ
ント配線板を製造するに当たって、その製造工程中に、
少なくとも下記 (a)〜(ｄ) の工程、すなわち、(a)コア
基板を貫通するスルーホールを形成する工程、(b)その
スルーホールが開口するコア基板の両面に内層導体回路
をそれぞれ形成する工程、(c)上記スルーホールランド
を含んだ内層導体回路の上面および側面と、スルーホー
ル内壁面とに粗化層を形成する工程、(d)その粗化層が
形成されたコア基板の表面に対して、所定の加熱条件下
において軟化するような樹脂フィルムと、その樹脂フィ
ルムの片面に貼付けられたＢステージ樹脂とを含むフィ
ルム状絶縁材を、そのＢステージ樹脂面を向けて貼付
け、上記フィルム状絶縁材を所定の圧力でプレスした
後、所定の温度で加熱し、あるいは所定の圧力でプレス
すると同時に所定の温度で加熱して、上記Ｂステージ樹
脂を軟化せしめて、スルーホールランドを含んだ内層導
体回路の側面と基板表面とで規定される凹部およびスル
ーホールの内壁面によって規定される貫通穴内に、その
軟化したＢステージ樹脂を充填するとともに、その軟化
したＢステージ樹脂を覆う樹脂フィルムを軟化せしめ、
その後、両者を硬化させる工程、を含むことを特徴とす
る。上記工程(ｄ)におけるフィルム状絶縁材を構成する
樹脂フィルムとＢステージ樹脂とは、同一の樹脂組成で
あることが望ましい。また、そのフィルム状絶縁材は、
熱硬化性のポリオレフィン系樹脂またはエポキシ系樹脂
を主成分として形成された樹脂フィルムと、５０〜８０
重量％の樹脂成分からなるＢステージ樹脂とから形成さ
れることが望ましい。上記工程(ｄ)におけるポリオレフ
ィン系樹脂を主成分とする樹脂フィルムおよびそのＢス
テージ樹脂からなるフィルム状絶縁材の加熱プレスは、
圧力１〜５０kgf／cm2、温度５０〜２５０℃、加熱プレ
ス時間１〜１２０分間の条件にて行うことが望ましい。
また、上記工程(ｄ)における、エポキシ系樹脂を主成分
とする樹脂フィルムおよびそのＢステージ樹脂からなる
フィルム状絶縁材の加熱プレスは、圧力１〜５０kgf／c
m2、温度５０〜２００℃、、加熱プレス時間１〜７０分
間の条件にて行うことが望ましい。さらに、上記工程
(ｄ)において、フィルム状絶縁材を加熱しながら金属板
または金属ロールを押圧して行うことが望ましい。Means for Solving the Problems The inventors of the present invention have conducted intensive studies to achieve the above-mentioned object, and as a result, have found that a resin filler filled in the through-hole and a resin filler filled in the recess between the inner conductor circuits are formed. It has been found that if the same resin material is used for the interlayer resin insulating layer, it is possible to prevent the occurrence of peeling and cracks due to the difference in thermal expansion coefficient, and to complete the present invention having the following configuration as a summary configuration. Reached. (1) That is, according to the present invention, a conductor circuit of an outer layer is formed on a conductor circuit formed on both sides of a core substrate via a resin insulating layer, and an electric connection between the conductor circuits located on both sides of the core substrate is provided. In the multilayer printed wiring board having a build-up structure in which the electrical connection is performed by a through hole formed in the core substrate, the resin insulating layer includes a resin film that softens under predetermined heating conditions, A film-like insulating material containing a B-stage resin adhered to one side is formed by a heat press, and is defined by a concave portion defined by a side surface of an inner-layer conductor circuit including a through-hole land and a surface of a core substrate and an inner wall of a through-hole. The softened B-stage resin layer filled in the through-hole to be formed and the softened resin film layer covering the B-stage resin are hardened. It is characterized by comprising. It is desirable that the resin film and the B-stage resin constituting the film-shaped insulating material have the same resin composition.
Further, it is desirable that the film-like insulating material contains a resin film mainly composed of a thermosetting polyolefin resin or an epoxy resin, and a B-stage resin composed of a resin component of 50 to 80% by weight. . (2) Further, according to the present invention, a conductor circuit of an outer layer is formed on a conductor circuit formed on both surfaces of a core substrate via a resin insulating layer, and a conductor circuit disposed on both sides of the core substrate is provided. In manufacturing a multilayer printed wiring board having a build-up structure in which electrical connection is performed by through holes formed in a core substrate, during the manufacturing process,
At least the following steps (a) to (d), i.e., (a) a step of forming a through hole penetrating the core substrate, and (b) forming an inner layer conductor circuit on each side of the core substrate where the through hole opens. (C) forming a roughened layer on the upper and side surfaces of the inner conductor circuit including the through-hole lands and the inner wall surface of the through-hole, and (d) a surface of the core substrate on which the roughened layer is formed. On the other hand, a film-like insulating material including a resin film that softens under predetermined heating conditions and a B-stage resin attached to one surface of the resin film is attached with the B-stage resin surface facing the above, After the film-shaped insulating material is pressed at a predetermined pressure, it is heated at a predetermined temperature, or is pressed at a predetermined pressure and simultaneously heated at a predetermined temperature to soften the B-stage resin, thereby forming a through-hole. The softened B-stage resin is filled into the through-hole defined by the concave portion defined by the side surface of the inner-layer conductor circuit including the land and the substrate surface and the inner wall surface of the through-hole, and the softened B-stage resin is filled. Soften the covering resin film,
Thereafter, a step of curing both is included. It is desirable that the resin film and the B-stage resin constituting the film-like insulating material in the step (d) have the same resin composition. In addition, the film-like insulating material,
A resin film formed mainly of a thermosetting polyolefin resin or an epoxy resin;
It is desirably formed from a B-stage resin composed of a resin component by weight. In the step (d), a resin film containing a polyolefin-based resin as a main component and a hot press of a film-like insulating material made of the B-stage resin,
It is desirable to carry out under the conditions of a pressure of 1 to 50 kgf / cm 2 , a temperature of 50 to 250 ° C., and a heating press time of 1 to 120 minutes.
In the step (d), the heating press of the resin film mainly composed of the epoxy resin and the film-like insulating material composed of the B-stage resin is performed under a pressure of 1 to 50 kgf / c.
It is desirable to carry out under the conditions of m 2 , temperature of 50 to 200 ° C. and heating press time of 1 to 70 minutes. In addition, the above process
In (d), it is preferable to press the metal plate or metal roll while heating the film-shaped insulating material.
【発明の実施形態】本発明の多層プリント配線板は、層
間樹脂絶縁層が、所定の加熱条件下において軟化するよ
うな樹脂フィルムと、その片面に貼付けられたＢステー
ジ樹脂とを含むフィルム状絶縁材の加熱プレスによって
形成され、加熱を受けると流動性が大きく低粘度となる
Ｂステージ樹脂が、内層導体回路間の凹部およびスルー
ホールの貫通穴内の細部にわたって充填され、軟化した
樹脂フィルムはそのＢステージ樹脂層を覆った状態で硬
化されていることを特徴としている。すなわち、Ｂステ
ージ樹脂は、加熱プレスを受けると樹脂フィルムの軟化
に先だって軟化して低粘度の流体となり、内層導体回路
間の凹部およびスルーホールの貫通穴内に細部にわたっ
て充填され得ること、また、樹脂フィルムは、Ｂステー
ジ樹脂が軟化された後に軟化し、Ｂステージ樹脂を覆っ
た状態で、コア基板に設けた内層導体回路を覆う樹脂絶
縁層を形成する点にある。このような構成によれば、従
来技術が抱えている、内層導体回路間の凹部に充填され
た充填材と層間樹脂絶縁層との界面、およびスルーホー
ルの貫通穴に充填した充填材と層間樹脂絶縁層との界面
での剥離やクラックの発生を防止できるとともに、加熱
を受けると流動性が大きくなるＢステージ樹脂を含んで
いるので、スルーホールの貫通穴内への充填が容易とな
り、スルーホールの貫通穴への絶縁材の未充填や充填不
足の発生を阻止できる。さらに、より小さな径のスルー
ホールへの樹脂充填を可能とする。上記フィルム状絶縁
材を構成する樹脂フィルムと、Ｂステージ樹脂とは、同
一の樹脂組成であることが望ましく、とくに、熱硬化性
のポリオレフィン系樹脂またはエポキシ系樹脂を主成分
とした樹脂フィルムと、５０〜８０重量％の樹脂成分か
らなるＢステージ樹脂とから構成されることが好ましい
実施の態様である。上記ポリオレフィン系樹脂は、その
一つとしてのシクロオレフィン系樹脂を用いることがで
きる。このシクロオレフィン系樹脂は、誘電率および誘
電正接が低いので、ＧＨｚ帯域の高周波信号を用いた場
合でも信号の伝播遅延やエラーが起きにくく、さらに
は、剛性等の機械的特性にも優れるからである。シクロ
オレフィン系樹脂としては、２−ノルボルネン、５−エ
チリデン−２−ノボルネンまたはこれらの誘導体からな
る単量体の単独重合または共重合体であることが望まし
い。上記誘導体としては、２−ノルボルネンなどのシク
ロオレフィンに、架橋を形成するためのアミノ酸残基あ
るいはマレイン酸変性したもの等が結合したものが挙げ
られる。上記共重合体を合成する場合の単量体として
は、例えば、エチレン、プロピレンなどがある。その中
でも熱硬化性シクロオレフィン系樹脂であることが望ま
しい。加熱を行って架橋を形成させることにより、より
剛性が高くなり機械的特性が向上するからである。以
下、本発明にかかる多層プリント配線板を製造する方法
について、一例を挙げて具体的に説明する。 （１）スルーホールおよび内層導体回路の形成 まず、両面に金属層が形成された基板を用意し、この基
板にドリルで貫通孔を明け、この貫通孔の壁面および基
板表面に、無電解めっきおよび電解めっきを施すことに
よって、スルーホールを形成する。ここで、上記基板と
しては、ガラスエポキシ基板やポリイミド基板、ビスマ
レイミド−トリアジン樹脂基板、フッ素樹脂基板などの
樹脂基板、あるいはこれらの樹脂基板の銅張積層板など
を用いることができる。特に、誘電率を考慮する場合
は、両面銅張フッ素樹脂基板を用いることが好ましい。
この基板は、片面が粗化された銅箔をポリテトラフルオ
ロエチレン等のフッ素樹脂基板に熱圧着したものであ
る。無電解めっきとしては、銅めっきがよい。フッ素樹
脂基板基板のようにめっきのつきまわりが悪い基板の場
合は、有機金属ナトリウムからなる前処理剤（潤工社
製、商品名：テトラエッチ）、プラズマ処理などの表面
改質を行う。次に、厚付けのために電解めっきを行う。
この電解めっきとしては、銅めっきがよい。このような
無電解めっきおよび電解めっきが形成された基板表面
を、常法に従い、パターン状にエッチングして、内層導
体回路およびスルーホールランドを形成して、コア基板
とする。そのエッチング液としては、硫酸−過酸化水素
の水溶液、過硫酸アンモニウムや過硫酸ナトリウム、過
硫酸カリウムなどの過硫酸塩水溶液、塩化第二鉄や塩化
第二銅の水溶液がよい。 （２）粗化層の形成 上記コア基板のスルーホールの貫通穴の内壁、スルーホ
ールランドの上面および側面、内層導体回路の上面およ
び側面に、同一種類の粗化層を形成する。このような粗
化層としては、酸化−還元処理による粗化層や、メック
社製の「メックエッチボンド」なるエッチング液で処理
形成された粗化層、あるいは銅-ニッケル-リンからなる
合金めっき粗化層（例えば、荏原ユージライト社製のイ
ンタープレート）等がある。上記酸化還元処理による粗
化層は、たとえば、酸化浴として、NaOH（20ｇ／ｌ）、
NaCl02（50ｇ／ｌ）、Na3PO4（15.0ｇ／ｌ）の水溶液、
還元浴として、NaOH（2.7ｇ／ｌ）、NaBH4 （ 1.0ｇ／
ｌ）の水溶液を用いて形成される。また、上記銅−ニッ
ケル−リン針状合金のめっき水溶液の液組成は、銅イオ
ン濃度、ニッケルイオン濃度、次亜リン酸イオン濃度
が、それぞれ 2.2×10-2〜4.1×10-2 mol／ｌ、 2.2×1
0-3〜 4.1×10-3 mol／ｌ、0.20〜0.25 mol／ｌである
ことが望ましい。この範囲で析出する被膜の結晶構造は
針状構造になるため、アンカー効果に優れるからであ
る。なお、この無電解めっき浴には上記化合物に加えて
錯化剤や添加剤を加えてもよい。さらに、上記エッチン
グ処理による粗化層は、第二銅錯体と有機酸の混合水溶
液を用いて形成され、エッチング液の液組成としては、
たとえば、イミダゾール銅(ＩＩ)錯体１０重量部、グリ
コール酸７重量部、塩化カリウム５重量部を混合した水
溶液とする。本発明では、スルーホールランドを含む内
層導体回路の上面および側面、およびスルーホールの貫
通穴の内壁面を同時に粗化処理するため、多層プリント
配線板の製造工程が短縮され、製造コストが低減できる
とともに、粗化形態の違いにより発生するクラックの発
生を防止できる。 （３）層間樹脂絶縁層の形成 上記（２）において粗化処理した基板に対して、樹脂フ
ィルムと、その片面に貼付けられ、樹脂フィルムと同一
樹脂からなるＢステージ樹脂とを含むフィルム状絶縁材
を、そのＢステージ樹脂面を基板に向けた状態で貼付け
る。このフィルム状絶縁材を構成する樹脂フィルムは、
熱硬化性のポリオレフィン系樹脂またはエポキシ系樹脂
を主成分とした樹脂から形成され、Ｂステージ樹脂は、
５０〜８０重量％の樹脂成分から形成されるのが好まし
い。上記樹脂フィルムやＢステージ樹脂の厚みは、内層
導体回路の厚みや、スルーホールのアスペクト比、樹脂
自体の硬化収縮等を考慮して決められ、とくに、Ｂステ
ージ樹脂の厚さは、加熱プレスによって、スルーホール
の貫通穴をほぼ完全に埋めることができるような範囲に
選択されることが望ましい。すなわち、Ｂステージ樹脂
の厚みは本質的であり、基板の表裏両面からスルーホー
ルの貫通穴に充填されたＢステージ樹脂同士が貫通穴内
で流動し結合でき、それによって、スルーホールの貫通
穴内での剥離がなくなり、接続信頼性を大幅に向上させ
ることができる。 次に、基板上に貼付けられたフィルム状絶縁材を、そ
の樹脂フィルム上から金属板や金属ロールを用いて加熱
しながら押圧（加熱プレス）して、軟化させ、充填終了
後に硬化させる。ここで用いる金属板や金属ロールは、
ステンレス製のものがよい。その理由は耐腐食性に優れ
るからである。加熱プレスは、フィルム状絶縁材を貼付
けた基板を金属板または金属ロールにて挟持し、加熱雰
囲気でプレスすることにより行なう。この加熱プレスに
より、まずＢステージ樹脂が軟化して、スルーホールラ
ンドを含む内層導体回路間の凹部およびスルーホールの
貫通穴の細部にわたって充填され、その後、樹脂フィル
ムが軟化して、Ｂステージ樹脂層を覆うとともにスルー
ホールランドを含む内層導体回路の表面を覆った状態
で、その表面が平坦化される。上記加熱プレス工程にお
けるプレス圧力、加熱温度、プレス時間は、フィルム状
絶縁材に含まれる樹脂により異なる。例えば、ポリオレ
フィン系樹脂を主成分とした樹脂フィルムと、そのＢス
テージ樹脂からなるフィルム状絶縁材の場合は、プレス
圧力：１〜５０kgf／cm2、加熱温度：５０〜２５０℃、
加熱プレス時間：１〜１２０分とすることが望ましい。
加熱プレス条件に上記のような限定を加えた理由は、プ
レス圧力が１kgf／cm2未満、加熱温度が５０℃未満、加
熱プレス時間が１分未満である場合には、流動化した樹
脂が、スルーホールの貫通穴に十分に充填されないから
であり、一方、プレス圧力が５０kgf／cm2を超えると、
樹脂の流れ出しが発生するからであり、加熱温度２５０
℃を超えると、コア材にダメージを与えるからであり、
加熱プレス時間が１２０分を超えると、生産性に乏しい
からである。また、エポキシ系樹脂を主成分とする樹脂
フィルムと、そのＢステージ樹脂からなるフィルム状絶
縁材を用いる場合は、プレス圧力を１〜５０ kgf／cm
2 、加熱温度を５０〜２００℃、加熱プレス時間を１〜
７０分とすることが望ましく、このような加熱プレス条
件に制限を設けたのは、ポリオレフィン系樹脂を主成分
とする樹脂フィルムと、そのＢステージ樹脂とからなる
フィルム状絶縁材の場合と同様の理由である。なお、こ
の実施形態においては、フィルム状絶縁材を加熱しなが
らプレスして軟化させたが、始めにフィルム状絶縁材に
所定の圧力を加えて、その後、加熱して軟化させること
もできる。また、上記加熱プレス工程は、減圧下におい
て行うことが好ましい実施の形態である。 （４）ビアホールおよび外層導体回路の形成 上記（３）にて形成した層間樹脂絶縁層内に、内層
導体回路と外層導体回路（後に形成する）との間、ある
いはその外層導体回路とスルーホールランドとの電気的
接続を確保するために、ビアホール形成用の開口を設け
る。このビアホール形成用の開口は、レーザ光照射によ
って行う。このとき、使用されるレーザ光としては、炭
酸ガスレーザ、紫外線レーザ、エキシマレーザなどが使
用されるが、炭酸ガスレーザによる加工が好適である。
上記炭酸ガスレーザの照射条件は、、パルスエネルギー
が０．５〜２００ｍＪ、パルス幅が１０−８〜１０−３
μｓ、パルス間隔が０．１ｍｓ以上、ショット数が１〜
１００であることが望ましい。このようなレーザ光照射
による開口形成の後、デスミア処理を行なう。このデス
ミア処理は、クロム酸、過マンガン酸塩などの水溶液か
らなる酸化剤を使用して行うことができ、また酸素プラ
ズマなどで処理してもよい。 次に、ビアホール形成用の開口内および層間樹脂絶縁
層の表面に、めっきまたはスパッタリング等によって、
薄付け導体層を形成する。めっきにより形成する場合に
は、まず、層間樹脂絶縁層に無電解めっき用の触媒核を
付与する。一般に触媒核は、パラジウム−スズコロイド
であり、この溶液に基板を浸漬、乾燥、加熱処理して樹
脂表面に触媒核を固定する。また、金属核をＣＶＤ、ス
パッタ、プラズマにより樹脂表面に打ち込んで触媒核と
することができる。この場合、樹脂表面に金属核が埋め
込まれることになり、この金属核を中心にめっきが析出
して導体回路が形成されるため、密着性を確保できる。
この金属核としては、パラジウム、銀、金、白金、チタ
ン、銅およびニッケルから選ばれる少なくとも１種以上
がよい。なお、金属核の量は、20μｇ／cm2 以下がよ
い。この量を超えると金属核を除去しなければならない
からである。ついで、無電解めっきまたはスパッタリン
グを施して、ビアホール形成用開口内および層間樹脂絶
縁層の表面に薄膜の無電解めっき膜またはスパッタ膜を
形成する。このとき、無電解めっき膜またはスパッタ膜
の厚みは、 0.1〜5.0μｍ、より望ましくは 0.5〜３.0
μｍとする。 次に、この無電解めっき膜またはスパッタ膜上にめ
っきレジストを形成する。めっきレジスト組成物として
は、特にクレゾールノボラック型エポキシ樹脂やフェノ
ールノボラック型エポキシ樹脂のアクリレートとイミダ
ゾール硬化剤からなる組成物を用いることが望ましい
が、他に市販品のドライフィルムを使用することもでき
る。 次に、無電解めっき膜を形成した基板を、10〜35
℃、望ましくは15〜30℃の水で水洗する。この理由は、
水洗温度が35℃を超えると水が揮発してしまい、無電解
めっき膜の表面が乾燥して、酸化してしまい、電解めっ
き膜が析出しない。そのため、エッチング処理により、
無電解めっき膜が溶解してしまい、導体が存在しない部
分が生じてしまう。一方、10℃未満では水に対する汚染
物質の溶解度が低下し、洗浄力が低下してしまうからで
ある。特に、ビアホールのランドの径が 200μｍ以下に
なると、めっきレジストが水をはじくため、水が揮発し
やすく、電解めっきの未析出という問題が発生しやす
い。なお、洗浄水の中には、各種の界面活性剤、酸、ア
ルカリを添加しておいてもよい。また、洗浄後に硫酸な
どの酸で洗浄してもよい。 次に、めっきレジスト非形成部に電解めっきを施し
て、外層導体回路、ならびにビアホールとなる導体層を
設ける。ここで、上記電解めっきとしては、銅めっきを
用いることが望ましく、その厚みは、10〜20μｍがよ
い。 さらに、めっきレジストを除去した後、硫酸と過酸
化水素の混合液や過硫酸ナトリウム、過硫酸アンモニウ
ムなどの水溶液からなるエッチング液でめっきレジスト
下の無電解めっき膜あるいはスパッタ膜を溶解除去し、
無電解めっき膜あるいはスパッタ膜と電解めっき膜の２
層からなる独立した外層導体回路、ならびにビアホール
を得る。 （５）配線基板の多層化 上記(４)で形成した外層導体回路の表面に粗化層を形成
した後、前記(３)および(４)の工程を繰り返してさらに
外層の導体回路を設けることにより、所定の多層プリン
ト配線板を製造する。BEST MODE FOR CARRYING OUT THE INVENTION A multilayer printed wiring board according to the present invention is a film-like insulating film including a resin film in which an interlayer resin insulating layer is softened under a predetermined heating condition, and a B-stage resin stuck on one surface thereof. B-stage resin, which is formed by a heat press of the material and has a high fluidity and low viscosity when heated, is filled over the concave portions between the inner layer conductor circuits and the details in the through holes of the through holes, and the softened resin film is It is characterized by being cured while covering the stage resin layer. That is, the B-stage resin is softened prior to the softening of the resin film and becomes a low-viscosity fluid when subjected to a heat press, and can be filled into the concave portions between the inner-layer conductor circuits and the through holes of the through-holes in detail. The film is softened after the B-stage resin is softened, and forms a resin insulating layer that covers the inner conductor circuit provided on the core substrate in a state of covering the B-stage resin. According to such a configuration, the interface between the filler filled in the recess between the inner conductor circuits and the interlayer resin insulating layer, and the filler filled in the through hole of the through hole and the interlayer resin, which the conventional technology has, In addition to preventing the occurrence of peeling and cracking at the interface with the insulating layer, it also contains a B-stage resin whose fluidity increases when heated, so that the through-holes can be easily filled into the through-holes. It is possible to prevent the through-hole from being unfilled or insufficiently filled with the insulating material. Further, it is possible to fill the through hole having a smaller diameter with the resin. The resin film constituting the film-shaped insulating material and the B-stage resin preferably have the same resin composition, particularly, a resin film containing a thermosetting polyolefin-based resin or an epoxy-based resin as a main component, In a preferred embodiment, the B-stage resin is composed of 50 to 80% by weight of a resin component. As the polyolefin resin, a cycloolefin resin as one of them can be used. Since the cycloolefin resin has a low dielectric constant and a low dielectric loss tangent, signal propagation delay and error hardly occur even when a high frequency signal in a GHz band is used, and furthermore, it is excellent in mechanical properties such as rigidity. is there. The cycloolefin resin is preferably a homopolymer or copolymer of a monomer composed of 2-norbornene, 5-ethylidene-2-nobornene or a derivative thereof. Examples of the derivative include a derivative in which an amino acid residue for forming a crosslink or a maleic acid-modified derivative is bonded to a cycloolefin such as 2-norbornene. Examples of monomers for synthesizing the copolymer include ethylene and propylene. Among them, a thermosetting cycloolefin resin is preferable. This is because, by performing the heating to form the crosslinks, the rigidity is increased and the mechanical properties are improved. Hereinafter, a method for manufacturing a multilayer printed wiring board according to the present invention will be specifically described with reference to an example. (1) Formation of Through Hole and Inner Layer Conductor Circuit First, a substrate having a metal layer formed on both surfaces is prepared, and a through hole is drilled in the substrate. Through-holes are formed by performing electrolytic plating. Here, as the substrate, a resin substrate such as a glass epoxy substrate, a polyimide substrate, a bismaleimide-triazine resin substrate, a fluororesin substrate, or a copper-clad laminate of these resin substrates can be used. In particular, when the dielectric constant is considered, it is preferable to use a double-sided copper-clad fluororesin substrate.
This substrate is obtained by thermocompression bonding a copper foil having one surface roughened to a fluororesin substrate such as polytetrafluoroethylene. Copper plating is preferable as the electroless plating. In the case of a substrate such as a fluororesin substrate, which has poor plating coverage, a surface treatment such as a pretreatment agent (manufactured by Junko Co., trade name: Tetra etch) made of organometallic sodium or plasma treatment is performed. Next, electrolytic plating is performed for thickening.
As this electrolytic plating, copper plating is preferable. The surface of the substrate on which the electroless plating and the electrolytic plating are formed is etched in a pattern according to a conventional method to form an inner conductor circuit and a through-hole land, thereby obtaining a core substrate. As the etchant, an aqueous solution of sulfuric acid-hydrogen peroxide, an aqueous solution of persulfate such as ammonium persulfate, sodium persulfate, or potassium persulfate, or an aqueous solution of ferric chloride or cupric chloride is preferable. (2) Formation of Roughened Layer The same type of roughened layer is formed on the inner wall of the through hole of the through hole of the core substrate, the upper surface and the side surface of the through hole land, and the upper surface and the side surface of the inner conductor circuit. Examples of such a roughened layer include a roughened layer formed by an oxidation-reduction treatment, a roughened layer formed by processing with an etching solution called “MEC etch bond” manufactured by MEC, or an alloy plating made of copper-nickel-phosphorus. There is a roughened layer (for example, an Interplate manufactured by EBARA Uzilite). The roughened layer formed by the oxidation-reduction treatment may be, for example, NaOH (20 g / l) as an oxidation bath,
NaClO 2 (50 g / l), aqueous solution of Na 3 PO 4 (15.0 g / l),
NaOH (2.7 g / l), NaBH 4 (1.0 g /
It is formed using the aqueous solution of 1). The solution composition of the aqueous plating solution of the copper-nickel-phosphorus needle-shaped alloy has a copper ion concentration, a nickel ion concentration, and a hypophosphite ion concentration of 2.2 × 10 −2 to 4.1 × 10 −2 mol / l, respectively. , 2.2 × 1
Desirably, it is 0 -3 to 4.1 × 10 -3 mol / l, and 0.20 to 0.25 mol / l. This is because the crystalline structure of the film deposited in this range has a needle-like structure, and thus has an excellent anchor effect. In addition, a complexing agent or an additive may be added to the electroless plating bath in addition to the above compounds. Further, the roughened layer by the etching treatment is formed using a mixed aqueous solution of a cupric complex and an organic acid.
For example, an aqueous solution is prepared by mixing 10 parts by weight of an imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride. In the present invention, since the upper and side surfaces of the inner conductor circuit including the through hole land and the inner wall surface of the through hole of the through hole are simultaneously roughened, the manufacturing process of the multilayer printed wiring board can be shortened, and the manufacturing cost can be reduced. At the same time, it is possible to prevent the occurrence of cracks caused by the difference in the roughening mode. (3) Formation of interlayer resin insulating layer A film-like insulating material including a resin film and a B-stage resin made of the same resin as the resin film, which is affixed to one surface of the substrate roughened in the above (2). Is attached with its B-stage resin surface facing the substrate. The resin film constituting this film-shaped insulating material is
The thermosetting polyolefin resin or epoxy resin is used as the main component.
It is preferably formed from 50 to 80% by weight of the resin component. The thickness of the resin film or the B-stage resin is determined in consideration of the thickness of the inner-layer conductor circuit, the aspect ratio of the through-hole, the curing shrinkage of the resin itself, and the like. It is desirable to select the through hole so that the through hole can be almost completely filled. In other words, the thickness of the B-stage resin is essential, and the B-stage resins filled in the through-holes of the through-holes can flow and combine in the through-holes from both the front and back surfaces of the substrate. Peeling does not occur, and connection reliability can be greatly improved. Next, the film-shaped insulating material stuck on the substrate is pressed (heat-pressed) while being heated from above the resin film using a metal plate or a metal roll, and is softened. The metal plate and metal roll used here are
Stainless steel is preferred. The reason is that it has excellent corrosion resistance. The heating press is performed by sandwiching the substrate on which the film-shaped insulating material is attached with a metal plate or a metal roll and pressing the substrate in a heating atmosphere. By this heating press, the B-stage resin is first softened and filled over the recesses between the inner layer conductor circuits including the through-hole lands and the details of the through-holes of the through-holes. While covering the surface of the inner layer conductor circuit including the through-hole lands, the surface is flattened. The pressing pressure, the heating temperature, and the pressing time in the above-mentioned hot pressing step differ depending on the resin contained in the film-shaped insulating material. For example, in the case of a resin film containing a polyolefin-based resin as a main component and a film-like insulating material made of the B-stage resin, a pressing pressure: 1 to 50 kgf / cm 2 , a heating temperature: 50 to 250 ° C.
Heat press time: desirably 1 to 120 minutes.
The reason for adding the above-mentioned limitation to the heating press conditions is that when the pressing pressure is less than 1 kgf / cm 2 , the heating temperature is less than 50 ° C., and the heating press time is less than 1 minute, the fluidized resin is This is because the through holes are not sufficiently filled in the through holes. On the other hand, when the pressing pressure exceeds 50 kgf / cm 2 ,
This is because the resin flows out, and the heating temperature is 250
If the temperature exceeds ℃, the core material will be damaged,
If the heating press time exceeds 120 minutes, productivity is poor. When a resin film mainly composed of an epoxy resin and a film-like insulating material made of the B-stage resin are used, the pressing pressure is 1 to 50 kgf / cm.
2 , the heating temperature is 50 ~ 200 ℃, the heating press time is 1 ~
It is preferable to set the heating press conditions to 70 minutes. The same reason as in the case of the film-like insulating material composed of the resin film mainly composed of the polyolefin resin and the B-stage resin is used to limit the heating press conditions. That is the reason. In this embodiment, the film-shaped insulating material is pressed and softened while being heated. However, it is also possible to first apply a predetermined pressure to the film-shaped insulating material and then heat it to soften it. Moreover, in the preferred embodiment, the heating press step is preferably performed under reduced pressure. (4) Formation of Via Hole and Outer Layer Conductor Circuit In the interlayer resin insulating layer formed in the above (3), between the inner layer conductor circuit and the outer layer conductor circuit (to be formed later) or the outer layer conductor circuit and the through hole land An opening for forming a via hole is provided in order to secure electrical connection with the substrate. The opening for forming the via hole is formed by laser beam irradiation. At this time, as a laser beam to be used, a carbon dioxide gas laser, an ultraviolet laser, an excimer laser, or the like is used, but processing by a carbon dioxide gas laser is preferable.
The irradiation condition of the carbon dioxide laser is such that the pulse energy is 0.5 to 200 mJ and the pulse width is 10 −8 to 10 −3.
μs, pulse interval 0.1 ms or more, shot number 1
Desirably, it is 100. After the opening is formed by such laser beam irradiation, a desmear process is performed. This desmear treatment can be performed using an oxidizing agent composed of an aqueous solution such as chromic acid or permanganate, or may be performed using oxygen plasma or the like. Next, in the opening for via hole formation and on the surface of the interlayer resin insulation layer, by plating or sputtering, etc.
A thin conductor layer is formed. In the case of forming by plating, first, a catalyst nucleus for electroless plating is applied to the interlayer resin insulating layer. Generally, the catalyst core is a palladium-tin colloid, and the substrate is immersed in this solution, dried, and heat-treated to fix the catalyst core on the resin surface. Further, a metal nucleus can be used as a catalyst nucleus by being driven into the resin surface by CVD, sputtering, or plasma. In this case, a metal nucleus is embedded in the resin surface, and plating is deposited around the metal nucleus to form a conductor circuit, so that adhesion can be ensured.
The metal nucleus is preferably at least one selected from palladium, silver, gold, platinum, titanium, copper and nickel. The amount of metal nuclei is preferably 20 μg / cm 2 or less. If the amount exceeds this amount, metal nuclei must be removed. Then, electroless plating or sputtering is performed to form a thin electroless plating film or sputtered film in the via hole forming opening and on the surface of the interlayer resin insulating layer. At this time, the thickness of the electroless plating film or the sputtered film is 0.1 to 5.0 μm, more preferably 0.5 to 3.0 μm.
μm. Next, a plating resist is formed on the electroless plating film or the sputtered film. As the plating resist composition, it is particularly desirable to use a composition comprising an acrylate of a cresol novolak type epoxy resin or an acrylate of a phenol novolak type epoxy resin and an imidazole curing agent. Alternatively, a commercially available dry film may be used. Next, the substrate on which the electroless plating film was formed was
C., preferably 15-30.degree. C. with water. The reason for this is
When the washing temperature exceeds 35 ° C., water evaporates, the surface of the electroless plating film is dried and oxidized, and the electrolytic plating film does not deposit. Therefore, by the etching process,
The electroless plating film dissolves, resulting in a portion where no conductor exists. On the other hand, if the temperature is lower than 10 ° C., the solubility of the contaminant in water decreases, and the cleaning power decreases. In particular, when the diameter of the land of the via hole is 200 μm or less, the plating resist repels water, so that the water is liable to volatilize, and the problem of non-precipitation of electrolytic plating is likely to occur. In addition, various surfactants, acids, and alkalis may be added to the washing water. After the cleaning, the substrate may be washed with an acid such as sulfuric acid. Next, electrolytic plating is performed on the non-formed portions of the plating resist to provide an outer conductor circuit and a conductor layer serving as a via hole. Here, it is desirable to use copper plating as the electrolytic plating, and its thickness is preferably 10 to 20 μm. Furthermore, after removing the plating resist, an electroless plating film or a sputtered film under the plating resist is dissolved and removed with an etching solution comprising a mixed solution of sulfuric acid and hydrogen peroxide or an aqueous solution of sodium persulfate, ammonium persulfate, etc.
Electroless plating film or sputtering film and electrolytic plating film 2
An independent outer conductor circuit composed of layers and via holes are obtained. (5) Multilayering of Wiring Board After forming a roughened layer on the surface of the outer conductor circuit formed in the above (4), the above steps (3) and (4) are repeated to further provide an outer conductor circuit. Thus, a predetermined multilayer printed wiring board is manufactured.
【実施例】（実施例１） (１)厚さ 0.8ｍｍのＢＴ樹脂（ビスマレイミドトリアジ
ン）からなる基板１の両面に、18μｍの銅箔８がラミネ
ートされている銅張積層板を出発材料として用いた（図
１参照）。まず、この銅貼積層板をドリル削孔し、続い
てめっきレジストを形成した後、この基板に無電解銅め
っき処理を施して、直径が３００μｍのスルーホール９
を形成し（図２参照）、さらに、常法にしたがって、銅
箔を回路パターン形状にエッチングすることにより、基
板の両面に内層導体回路４およびスルーホールランド１
０を形成した（図３参照）。 （２）次に、内層導体回路４の側面を含む全表面、スル
ーホールランド１０の側面を含む全表面、およびスルー
ホール９の内壁面に、厚さ ２．５μｍの銅-ニッケル-
リン合金からなる粗化層（凹凸層）１１を形成する（図
４参照）。その形成方法は以下のようである。即ち、基
板を酸性脱脂してソフトエッチングし、次いで、塩化パ
ラジウムと有機酸からなる触媒溶液で処理して、Pd触媒
を付与し、この触媒を活性化した後、硫酸銅８ｇ／ｌ、
硫酸ニッケル 0.6ｇ／ｌ、クエン酸15ｇ／ｌ、次亜リン
酸ナトリウム29ｇ／ｌ、ホウ酸31ｇ／ｌ、界面活性剤
（日信化学工業製、サーフィノール465） 0.1ｇ／ｌの
水溶液からなるｐＨ＝９の無電解めっき浴にてめっきを
施して、銅-ニッケル-リン合金からなる粗化層１１を設
けた。 (３） 前記(２)で粗化層１１を形成した基板表面に、ポ
リオレフィン系樹脂を８０重量％含んだ樹脂絶縁材から
なる厚さ２５μｍの樹脂フィルム２ａと、その片面に、
同一の樹脂成分８０重量％含んだ厚さ３０μｍのＢステ
ージ樹脂２ｂを貼付けたフィルム状絶縁材２を、Ｂステ
ージ樹脂２ｂを基板表面に向けて配置させた後、ステン
レス板１９で挟み、７kgf/cm2で加圧し、加熱炉内にお
いて１００℃で加熱しながら、３分間加熱プレスした
（図５参照）。この加熱プレスにより、まず、Ｂステー
ジ樹脂２ｂが軟化して、スルーホールランド１０を含む
内層導体回路間の凹部およびスルーホールの貫通穴の細
部にわたって充填され、その後、樹脂フィルム２ａが軟
化してＢステージ樹脂層および内層導体回路の表面を覆
った状態で、その表面が平坦化される（図６参照）。な
お、樹脂フィルム２ａを構成するポリオレフィン系樹脂
としては、シクロオレフィン系樹脂を用いてもよい。 (４) 前記(３)で平坦化した層間樹脂絶縁層２の両面
に、波長が10.4μｍの炭酸ガスレーザを用いて、パルス
エネルギーが１００ｍＪ、パルス幅が１０−６μｓ、パ
ルス間隔が１．０ｍｓ以上、ショット数が５の照射条件
で、直径が８０μｍのバイアホール形成用の開口６を形
成した。（図７参照）。さらに、ＣＦ４および酸素混合
気体のプラズマ処理により、デスミアおよびポリオレフ
ィン系樹脂絶縁層表面の改質を行った。この改質によ
り、表面には、ＯＨ基やカルボニル基、ＣＯＯＨ基など
の親水性基が確認された。なお、酸素プラズマ処理条件
は、電力800Ｗ、0.1 Torr、2分間である。 (５)さらに、パラジウム触媒（アトテック製）を付与す
ることにより、層間樹脂絶縁層の表面およびバイアホー
ル用開口の内壁面に触媒核を付与した後（図８参照）、
以下の組成の無電解銅めっき水溶液中に基板を浸漬し
て、厚さ0.9μｍの無電解銅めっき膜１２を形成した
（図９参照）。 〔無電解めっき水溶液〕 ＥＤＴＡ 150 ｇ／ｌ 硫酸銅 20 ｇ／ｌ ＨＣＨＯ 30 ml／ｌ ＮａＯＨ 40 ｇ／ｌ α、α’−ビピリジル 80 mg／ｌ ＰＥＧ 0.1 ｇ／ｌ 〔無電解めっき条件〕70℃の液温度で30分 (６)前記(５) で形成した無電解めっき膜１２上に市販
の感光性ドライフィルムを張り付け、マスクを載置し
て、100 mJ／cm2 で露光、0.8 ％炭酸ナトリウムで現像
処理し、厚さ15μｍのめっきレジスト３を設けた（図１
０参照）。 (７)ついで、基板を50℃の水で洗浄して脱脂し、25℃の
水で水洗後、さらに硫酸で洗浄してから、以下の条件で
電解銅めっきを施し、厚さ２０μｍの電解銅めっき膜１
３を形成した（図１１参照）。 (７)めっきレジスト３を５％ＫＯＨ水溶液で剥離除去し
た後、そのめっきレジスト下の無電解銅めっき膜１２を
硫酸と過酸化水素の混合液でエッチング処理して溶解除
去し、無電解銅めっき膜１２と電解銅めっき膜１３から
なる厚さ18μｍの外層導体回路（バイアホールを含む）
５を形成した（図１２参照）。 (８)外層導体回路５を形成した基板を、硫酸銅８ｇ／
ｌ、硫酸ニッケル 0.6ｇ／ｌ、クエン酸15ｇ／ｌ、次亜
リン酸ナトリウム29ｇ／ｌ、ホウ酸31ｇ／ｌ、界面活性
剤（日信化学工業製、サーフィノール465 ） 0.1ｇ／ｌ
の水溶液からなるｐＨ＝９の無電解めっき液に浸漬し、
該導体回路の表面に厚さ３μｍの銅−ニッケル−リンか
らなる粗化層１１を形成した（図１３参照）。このと
き、形成した粗化層をＥＰＭＡ（蛍光Ｘ線分析装置）で
分析したところ、Cu：98 mol％、Ni： 1.5 mol％、Ｐ：
0.5 mol％の組成比であった。 (９)前記 (３)〜(８)の工程を繰り返すことにより、さ
らに外層の導体回路を形成し、多層配線板を得た。（図
１４〜図１９参照）。 (１０)一方、DMDGに溶解させた60wt％のクレゾールノボ
ラック型エポキシ樹脂（日本化薬製）のエポキシ基50％
をアクリル化した感光性付与のオリゴマー（分子量400
0）を 46.67重量部、メチルエチルケトンに溶解させた8
0wt％のビスフェノールＡ型エポキシ樹脂（油化シェル
製、エピコート1001）15.0重量部、イミダゾール硬化剤
（四国化成製、2E4MZ-CN）1.6 重量部、感光性モノマー
である多価アクリルモノマー（日本化薬製、Ｒ604 ）３
重量部、同じく多価アクリルモノマー（共栄社化学製、
DPE6A ） 1.5重量部、分散系消泡剤（サンノプコ社製、
Ｓ−65）0.71重量部を混合し、さらにこの混合物に対し
て光開始剤としてのベンゾフェノン（関東化学製）を２
重量部、光増感剤としてのミヒラーケトン（関東化学
製）0.2 重量部を加えて、ソルダーレジスト組成物を得
た。 (１１)前記(９)で得た多層配線基板の両面に、上記ソル
ダーレジスト組成物を20μｍの厚さで塗布した。次い
で、70℃で20分間、70℃で30分間の乾燥処理を行った
後、クロム層によってソルダーレジスト開口部の円パタ
ーン（マスクパターン）が描画された厚さ５mmのソーダ
ライムガラス基板を、クロム層が形成された側をソルダ
ーレジスト層に密着させて1000mJ／cm2 の紫外線で露光
し、DMTG現像処理した。さらに、80℃で１時間、 100℃
で１時間、 120℃で１時間、 150℃で３時間の条件で加
熱処理し、はんだパッドの上面、ビアホールおよびラン
ド部分を開口した（開口径 200μｍ）ソルダーレジスト
パターン層（厚み20μｍ）１４を形成した。 (１２)次に、ソルダーレジストパターン層を形成した基
板を、塩化ニッケル30ｇ／ｌ、次亜リン酸ナトリウム10
ｇ／ｌ、クエン酸ナトリウム10ｇ／ｌの水溶液からなる
ｐＨ＝５の無電解ニッケルめっき液に20分間浸漬して、
開口部に厚さ５μｍのニッケルめっき層１５を形成し
た。さらに、その基板を、シアン化金カリウム２ｇ／
ｌ、塩化アンモニウム75ｇ／ｌ、クエン酸ナトリウム50
ｇ／ｌ、次亜リン酸ナトリウム10ｇ／ｌの水溶液からな
る無電解金めっき液に93℃の条件で23秒間浸漬して、ニ
ッケルめっき層上に厚さ0.03μｍの金めっき層１６を形
成した。 (１３)そして、ソルダーレジストパターン層の開口部
に、はんだペーストを印刷して 200℃でリフローするこ
とによりはんだバンプ（はんだ体）を形成し、はんだバ
ンプ１７を有する多層プリント配線板を製造した（図２
０参照）。 （実施例２）層間樹脂絶縁層の形成に際して、エポキシ
系樹脂を８０重量％含んだ樹脂絶縁材からなる厚さ２５
μｍの樹脂フィルムと、それと同一の樹脂を８０重量％
含んだ、厚さ３０μｍのＢステージ樹脂とからなるフィ
ルム状絶縁材を貼着した後、ステンレス板で挟み、７kg
f/cm2で加圧し、加熱炉内で１００℃で加熱しながら、
３分間加熱プレスしたこと以外は、実施例１と同様にし
て４層配線板を製造した。 （比較例１） （１）厚さ 0.８mmのＢＴ（ビスマレイミドトリアジ
ン）樹脂からなる基板１の両面に18μｍの銅箔８がラミ
ネートされてなる銅張積層板を出発材料とした（図２１
参照）。まず、この銅張積層板をドリル削孔し、無電解
銅めっきおよび電解銅めっきを施し、パターン状にエッ
チングすることにより、基板１の両面に内層導体回路４
とスルーホール９を形成した。この内層導体回路４とス
ルーホール９の表面を酸化（黒化）−還元処理して粗化
し（図２２参照）、導体回路間とスルーホール内に、充
填樹脂２０としてビスフェノールＦ型エポキシ樹脂を充
填した後（図２３参照）、その基板表面を、導体回路表
面およびスルーホールのランド表面が露出するまで研磨
して平坦化した（図２４参照）。 （２） 前記(1) の処理を施した基板を水洗いし、乾燥
した後、その基板を酸性脱脂してソフトエッチングし、
次いで、塩化パラジウムと有機酸からなる触媒溶液で処
理して、パラジウム触媒を付与し、この触媒を活性化し
た後、硫酸銅８ｇ／ｌ、硫酸ニッケル 0.6ｇ／ｌ、クエ
ン酸15ｇ／ｌ、次亜リン酸ナトリウム29ｇ／ｌ、ホウ酸
31ｇ／ｌ、界面活性剤 0.1ｇ／ｌ、ｐＨ＝９からなる無
電解めっき浴にてめっきを施し、銅導体回路の露出した
表面にCu−Ni−Ｐ合金からなる厚さ2.5μｍの粗化層1１
１（凹凸層）を形成した。さらに，その基板を、0.1mol
／ｌホウふっ化スズ−1.0mol／ｌチオ尿素液からなる無
電解スズ置換めっき浴に50℃で１時間浸漬し、前記粗化
層11の表面に厚さ 0.3μｍのスズ置換めっき層を設けた
（図２５参照、但しスズ層については図示しない）。 （３）基板の両面に、厚さ５０μｍの熱硬化型ポリオレ
フィン系樹脂シートを温度５０〜８０ ℃まで昇温しな
がら、圧力７ｋg／cm２で加熱プレスして積層し、ポリ
オレフィン系樹脂からなる層間樹脂絶縁層２２を設けた
(図２６参照)。 （４）波長10.4μｍの炭酸ガスレーザを用いて、パルス
エネルギーが１００ｍＪ、パルス幅が１０−６μｓ、パ
ルス間隔が１．０ｍｓ以上、ショット数が５の照射条件
のもとで、ポリオレフィン系樹脂からなる樹脂絶縁層２
２に直径８０μｍのバイアホール用開口６を設けた（図
２７参照）。その後、実施例１の上記（５）〜（１３）
と同様の処理を行って、4層配線板を製造した。このよ
うに実施例１、実施例２および比較例１にしたがって製
造した多層プリント配線板について、−55〜125 ℃で10
00回のヒートサイクル試験を実施し、光学顕微鏡により
層間樹脂絶縁層中のクラックの有無およびスルーホール
内での剥離の有無を確認した。その結果、実施例１およ
び実施例２については、層間樹脂絶縁層中のクラックの
発生およびスルーホール内での剥離が観察されず、比較
例１については、層間樹脂絶縁層中のクラックの発生お
よびスルーホール内での剥離が観察された。EXAMPLES (Example 1) (1) Starting from a copper-clad laminate in which 18 μm copper foil 8 is laminated on both sides of a substrate 1 made of a BT resin (bismaleimide triazine) having a thickness of 0.8 mm. Used (see FIG. 1). First, this copper-clad laminate is drilled, and then a plating resist is formed. Then, the substrate is subjected to an electroless copper plating treatment to form a through-hole 9 having a diameter of 300 μm.
(See FIG. 2), and furthermore, the copper foil is etched into a circuit pattern according to a conventional method, so that the inner layer conductor circuit 4 and the through-hole land 1 are formed on both sides of the substrate.
0 was formed (see FIG. 3). (2) Next, the entire surface including the side surface of the inner layer conductor circuit 4, the entire surface including the side surface of the through-hole land 10, and the inner wall surface of the through-hole 9 are coated with a copper-nickel having a thickness of 2.5 μm.
A roughened layer (uneven layer) 11 made of a phosphorus alloy is formed (see FIG. 4). The formation method is as follows. That is, the substrate was acid-degreased and soft-etched, then treated with a catalyst solution comprising palladium chloride and an organic acid to provide a Pd catalyst, and after activating this catalyst, copper sulfate 8 g / l,
It consists of an aqueous solution of nickel sulfate 0.6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l, boric acid 31 g / l, and surfactant (Nissin Chemical Industries, Surfynol 465) 0.1 g / l. Plating was performed in an electroless plating bath having a pH of 9 to provide a roughened layer 11 made of a copper-nickel-phosphorus alloy. (3) A 25 μm-thick resin film 2a made of a resin insulating material containing 80% by weight of a polyolefin resin, and
A film-like insulating material 2 having a thickness of 30 μm and containing the same resin component and having a thickness of 30 μm and having a thickness of 30 μm is disposed with the B-stage resin 2 b facing the substrate surface. While pressurizing at 2 cm 2 and heating at 100 ° C. in a heating furnace, heat press was performed for 3 minutes (see FIG. 5). By this heating press, first, the B-stage resin 2b is softened and filled over the recesses between the inner conductor circuits including the through-hole lands 10 and the details of the through holes of the through-holes. The surface is flattened while covering the surfaces of the stage resin layer and the inner conductor circuit (see FIG. 6). In addition, as the polyolefin resin constituting the resin film 2a, a cycloolefin resin may be used. (4) On both surfaces of the interlayer resin insulating layer 2 planarized in the above (3), using a carbon dioxide laser having a wavelength of 10.4 μm, a pulse energy of 100 mJ, a pulse width of 10 −6 μs, and a pulse interval of 1.0 ms. As described above, under the irradiation conditions of 5 shots, the opening 6 for forming a via hole having a diameter of 80 μm was formed. (See FIG. 7). Further, the surface of the desmear and polyolefin-based resin insulating layer was modified by plasma treatment with a mixed gas of CF 4 and oxygen. By this modification, hydrophilic groups such as OH groups, carbonyl groups, and COOH groups were confirmed on the surface. The oxygen plasma processing conditions are power of 800 W, 0.1 Torr and 2 minutes. (5) Further, by applying a palladium catalyst (manufactured by Atotech), a catalyst nucleus is applied to the surface of the interlayer resin insulating layer and the inner wall surface of the via hole opening (see FIG. 8).
The substrate was immersed in an electroless copper plating aqueous solution having the following composition to form a 0.9 μm-thick electroless copper plating film 12 (see FIG. 9). [Electroless plating aqueous solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions] 70 ° C. (6) A commercially available photosensitive dry film is stuck on the electroless plating film 12 formed in the above (5), a mask is placed thereon, and exposure is performed at 100 mJ / cm 2 , and 0.8% carbon dioxide is applied. Developed with sodium, and provided a plating resist 3 having a thickness of 15 μm (FIG. 1).
0). (7) Then, the substrate is washed with 50 ° C. water and degreased, washed with 25 ° C. water, further washed with sulfuric acid, and then subjected to electrolytic copper plating under the following conditions to obtain a 20 μm thick electrolytic copper. Plating film 1
No. 3 was formed (see FIG. 11). (7) After the plating resist 3 is peeled off with a 5% KOH aqueous solution, the electroless copper plating film 12 under the plating resist is dissolved and removed by etching treatment with a mixed solution of sulfuric acid and hydrogen peroxide, and the electroless copper plating is performed. 18 μm-thick outer conductor circuit (including via holes) consisting of film 12 and electrolytic copper plating film 13
5 was formed (see FIG. 12). (8) The substrate on which the outer conductor circuit 5 is formed is made of copper sulfate 8 g /
1, 0.6 g / l of nickel sulfate, 15 g / l of citric acid, 29 g / l of sodium hypophosphite, 31 g / l of boric acid, 0.1 g / l of surfactant (Sufinol 465, manufactured by Nissin Chemical Industry Co., Ltd.)
Immersed in an electroless plating solution of pH = 9 consisting of an aqueous solution of
A roughened layer 11 made of copper-nickel-phosphorus having a thickness of 3 μm was formed on the surface of the conductor circuit (see FIG. 13). At this time, when the formed roughened layer was analyzed by EPMA (X-ray fluorescence spectrometer), Cu: 98 mol%, Ni: 1.5 mol%, P:
The composition ratio was 0.5 mol%. (9) By repeating the above steps (3) to (8), a conductor circuit of an outer layer was further formed to obtain a multilayer wiring board. (See FIGS. 14 to 19). (10) On the other hand, 60% by weight of cresol novolac type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG, 50% of epoxy groups
Of photosensitizing oligomers (molecular weight 400
0) was dissolved in 46.67 parts by weight of methyl ethyl ketone
15.0 parts by weight of 0 wt% bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001), 1.6 parts by weight of imidazole curing agent (manufactured by Shikoku Chemicals, 2E4MZ-CN), polyacrylic monomer which is a photosensitive monomer (Nippon Kayaku) Made, R604) 3
Parts by weight, similarly polyvalent acrylic monomer (manufactured by Kyoeisha Chemical,
DPE6A) 1.5 parts by weight, dispersion antifoaming agent (manufactured by San Nopco,
S-65) 0.71 part by weight was mixed, and benzophenone (manufactured by Kanto Chemical Co., Ltd.) as a photoinitiator was added to the mixture.
By adding 0.2 parts by weight of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer, a solder resist composition was obtained. (11) The solder resist composition was applied to both sides of the multilayer wiring board obtained in (9) in a thickness of 20 μm. Next, after performing a drying process at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a 5 mm-thick soda lime glass substrate on which a circular pattern (mask pattern) of a solder resist opening is drawn by a chromium layer is placed on a chrome layer. The side on which the layer was formed was brought into close contact with the solder resist layer, exposed to ultraviolet light of 1000 mJ / cm 2 , and subjected to a DMTG development treatment. In addition, at 80 ° C for 1 hour, 100 ° C
For 1 hour, 120 ° C for 1 hour, and 150 ° C for 3 hours to form a solder resist pattern layer (thickness: 20 μm) 14 with openings (opening diameter: 200 μm) on the upper surface of the solder pad, via holes and lands. did. (12) Next, the substrate having the solder resist pattern layer formed thereon was treated with 30 g / l of nickel chloride and 10 g of sodium hypophosphite.
g / l, and immersed in an electroless nickel plating solution of pH 5 consisting of an aqueous solution of sodium citrate 10 g / l for 20 minutes,
A nickel plating layer 15 having a thickness of 5 μm was formed in the opening. Further, the substrate was treated with 2 g of potassium potassium cyanide /
l, ammonium chloride 75 g / l, sodium citrate 50
A gold plating layer 16 having a thickness of 0.03 μm was formed on the nickel plating layer by immersing it in an electroless gold plating solution composed of an aqueous solution of g / l and sodium hypophosphite 10 g / l at 93 ° C. for 23 seconds. . (13) Then, a solder paste is printed on the opening of the solder resist pattern layer and reflowed at 200 ° C. to form a solder bump (solder body), thereby manufacturing a multilayer printed wiring board having the solder bump 17 ( FIG.
0). (Example 2) When forming an interlayer resin insulating layer, a thickness 25 made of a resin insulating material containing 80% by weight of an epoxy resin.
80% by weight of μm resin film and the same resin
After attaching a film-like insulating material consisting of a 30-μm-thick B-stage resin and sandwiching it between stainless steel plates,
While pressurizing at f / cm 2 and heating at 100 ° C in a heating furnace,
A four-layer wiring board was manufactured in the same manner as in Example 1 except that the heating and pressing were performed for 3 minutes. (Comparative Example 1) (1) A copper-clad laminate obtained by laminating 18 μm copper foils 8 on both sides of a substrate 1 made of a 0.8 mm thick BT (bismaleimide triazine) resin was used as a starting material (FIG. 21).
reference). First, the copper-clad laminate is drilled, subjected to electroless copper plating and electrolytic copper plating, and etched in a pattern to form an inner conductor circuit 4 on both surfaces of the substrate 1.
And a through hole 9 were formed. The surfaces of the inner conductor circuit 4 and the through hole 9 are roughened by oxidation (blackening) -reduction treatment (see FIG. 22), and a bisphenol F type epoxy resin is filled between the conductor circuits and in the through hole as the filling resin 20. After that (see FIG. 23), the substrate surface was polished and flattened until the conductor circuit surface and the land surface of the through hole were exposed (see FIG. 24). (2) After the substrate subjected to the treatment of (1) is washed with water and dried, the substrate is acid-degreased and soft-etched,
Then, the catalyst is treated with a catalyst solution comprising palladium chloride and an organic acid to give a palladium catalyst, and after activating the catalyst, copper sulfate 8 g / l, nickel sulfate 0.6 g / l, citric acid 15 g / l, and Sodium phosphite 29g / l, boric acid
Plating is performed in an electroless plating bath consisting of 31 g / l, surfactant 0.1 g / l, and pH = 9, and the exposed surface of the copper conductor circuit is made of a Cu-Ni-P alloy and roughened to a thickness of 2.5 μm. Layer 11
1 (uneven layer) was formed. In addition, the substrate is
/ L tin borofluoride-1.0 mol / l immersion in an electroless tin displacement plating bath composed of a thiourea solution at 50 ° C for 1 hour to provide a 0.3 μm thick tin displacement plating layer on the surface of the roughened layer 11. (See FIG. 25, but the tin layer is not shown). (3) A thermosetting polyolefin resin sheet having a thickness of 50 μm is laminated on both surfaces of the substrate by heating and pressing at a pressure of 7 kg / cm 2 while the temperature is raised to a temperature of 50 to 80 ° C. The resin insulating layer 22 is provided
(See FIG. 26). (4) Using a carbon dioxide gas laser having a wavelength of 10.4 μm, under the irradiation conditions of a pulse energy of 100 mJ, a pulse width of 10 −6 μs, a pulse interval of 1.0 ms or more, and a number of shots of 5, a polyolefin resin is used. Resin insulation layer 2
2, a via hole opening 6 having a diameter of 80 μm was provided (see FIG. 27). Then, the above (5) to (13) of Example 1
By performing the same processing as described above, a four-layer wiring board was manufactured. Thus, the multilayer printed wiring boards manufactured according to Example 1, Example 2 and Comparative Example 1 were heated at -55 to 125 ° C. for 10 seconds.
A heat cycle test was performed 00 times, and the presence or absence of cracks in the interlayer resin insulating layer and the presence or absence of peeling in the through holes were confirmed by an optical microscope. As a result, in Examples 1 and 2, generation of cracks in the interlayer resin insulating layer and no peeling in the through holes were not observed, and in Comparative Example 1, generation of cracks in the interlayer resin insulating layer and Peeling in the through hole was observed.
【発明の効果】以上説明したように本発明によれば、層
間樹脂絶縁層を形成するフィルム状絶縁材が、所定の加
熱条件下で軟化する樹脂フィルムと、加熱を受けると流
動性が大きくなるＢステージ樹脂とを含んでいるので、
樹脂フィルム側からの加熱プレスによって軟化し低粘度
となったＢステージ樹脂が、導体回路間の凹部やスルー
ホールの貫通穴内へ入り込んで容易に充填される。した
がって、スルーホールの貫通穴への樹脂絶縁材の未充填
や充填不足の発生を阻止できる。また、樹脂フィルムと
Ｂステージ樹脂とが同一樹脂から形成されるので、従来
のようなスルーホールランドを含む導体回路と層間樹脂
絶縁層との界面における、樹脂材料の熱膨張係数の違い
に起因するクラックの発生を効果的に阻止することがで
きる。As described above, according to the present invention, the film-like insulating material forming the interlayer resin insulating layer is softened under predetermined heating conditions, and the fluidity increases when heated. Since it contains B-stage resin,
The B-stage resin softened and reduced in viscosity by the heat press from the resin film side enters into the recesses between the conductor circuits and the through holes of the through holes, and is easily filled. Therefore, it is possible to prevent the resin insulating material from being unfilled or insufficiently filled in the through hole. Further, since the resin film and the B-stage resin are formed from the same resin, the difference is caused by the difference in the thermal expansion coefficient of the resin material at the interface between the conductive circuit including the through-hole lands and the interlayer resin insulating layer as in the related art. Cracks can be effectively prevented.
【図１】本発明にかかる多層プリント配線板の実施例１
の製造工程の一部を示す図である。FIG. 1 is a first embodiment of a multilayer printed wiring board according to the present invention.
FIG. 7 is a view showing a part of the manufacturing process.
【図２】本発明にかかる多層プリント配線板の実施例１
の製造工程の一部を示す図である。FIG. 2 is a first embodiment of a multilayer printed wiring board according to the present invention;
FIG. 7 is a view showing a part of the manufacturing process.
【図３】本発明にかかる多層プリント配線板の実施例１
の製造工程の一部を示す図である。FIG. 3 is a first embodiment of a multilayer printed wiring board according to the present invention;
FIG. 7 is a view showing a part of the manufacturing process.
【図４】本発明にかかる多層プリント配線板の実施例１
の製造工程の一部を示す図である。FIG. 4 is a first embodiment of a multilayer printed wiring board according to the present invention;
FIG. 7 is a view showing a part of the manufacturing process.
【図５】本発明にかかる多層プリント配線板の実施例１
の製造工程の一部を示す図である。FIG. 5 is a first embodiment of a multilayer printed wiring board according to the present invention;
FIG. 7 is a view showing a part of the manufacturing process.
【図６】本発明にかかる多層プリント配線板の実施例１
の製造工程の一部を示す図である。FIG. 6 is a first embodiment of a multilayer printed wiring board according to the present invention;
FIG. 7 is a view showing a part of the manufacturing process.
【図７】本発明にかかる多層プリント配線板の実施例１
の製造工程の一部を示す図である。FIG. 7 is a first embodiment of a multilayer printed wiring board according to the present invention.
FIG. 7 is a view showing a part of the manufacturing process.
【図８】本発明にかかる多層プリント配線板の実施例１
の製造工程の一部を示す図である。FIG. 8 is a first embodiment of a multilayer printed wiring board according to the present invention.
FIG. 7 is a view showing a part of the manufacturing process.
【図９】本発明にかかる多層プリント配線板の実施例１
の製造工程の一部を示す図である。FIG. 9 is a first embodiment of a multilayer printed wiring board according to the present invention.
FIG. 7 is a view showing a part of the manufacturing process.
【図１０】本発明にかかる多層プリント配線板の実施例
１の製造工程の一部を示す図である。FIG. 10 is a diagram showing a part of the manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.
【図１１】本発明にかかる多層プリント配線板の実施例
１の製造工程の一部を示す図である。FIG. 11 is a diagram showing a part of the manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.
【図１２】本発明にかかる多層プリント配線板の実施例
１の製造工程の一部を示す図である。FIG. 12 is a diagram showing a part of the manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.
【図１３】本発明にかかる多層プリント配線板の実施例
１の製造工程の一部を示す図である。FIG. 13 is a diagram showing a part of the manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.
【図１４】本発明にかかる多層プリント配線板の実施例
１の製造工程の一部を示す図である。FIG. 14 is a diagram illustrating a part of the manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention;
【図１５】本発明にかかる多層プリント配線板の実施例
１の製造工程の一部を示す図である。FIG. 15 is a diagram showing a part of the manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.
【図１６】本発明にかかる多層プリント配線板の実施例
１の製造工程の一部を示す図である。FIG. 16 is a diagram showing a part of the manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.
【図１７】本発明にかかる多層プリント配線板の実施例
１の製造工程の一部を示す図である。FIG. 17 is a diagram showing a part of the manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.
【図１８】本発明にかかる多層プリント配線板の実施例
１の製造工程の一部を示す図である。FIG. 18 is a diagram illustrating a part of the manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention;
【図１９】本発明にかかる多層プリント配線板の実施例
１の製造工程の一部を示す図である。FIG. 19 is a diagram showing a part of the manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.
【図２０】本発明にかかる多層プリント配線板の実施例
１の製造工程の一部を示す図である。FIG. 20 is a diagram showing a part of the manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.
【図２１】本発明にかかる多層プリント配線板の比較例
１の製造工程の一部を示す図である。FIG. 21 is a diagram illustrating a part of the manufacturing process of Comparative Example 1 of the multilayer printed wiring board according to the present invention.
【図２２】本発明にかかる多層プリント配線板の比較例
１の製造工程の一部を示す図である。FIG. 22 is a diagram showing a part of the manufacturing process of Comparative Example 1 of the multilayer printed wiring board according to the present invention.
【図２３】本発明にかかる多層プリント配線板の比較例
１の製造工程の一部を示す図である。FIG. 23 is a diagram showing a part of the manufacturing process of Comparative Example 1 of the multilayer printed wiring board according to the present invention.
【図２４】本発明にかかる多層プリント配線板の比較例
１の製造工程の一部を示す図である。FIG. 24 is a diagram showing a part of the manufacturing process of Comparative Example 1 of the multilayer printed wiring board according to the present invention.
【図２５】本発明にかかる多層プリント配線板の比較例
１の製造工程の一部を示す図である。FIG. 25 is a diagram showing a part of the manufacturing process of Comparative Example 1 of the multilayer printed wiring board according to the present invention.
【図２６】本発明にかかる多層プリント配線板の比較例
１の製造工程の一部を示す図である。FIG. 26 is a diagram showing a part of the manufacturing process of Comparative Example 1 of the multilayer printed wiring board according to the present invention.
【図２７】本発明にかかる多層プリント配線板の比較例
１の製造工程の一部を示す図である。FIG. 27 is a diagram showing a part of the manufacturing process of Comparative Example 1 of the multilayer printed wiring board according to the present invention.
１ 基板 ２ 層間樹脂絶縁層 ２ａ 樹脂フィルム ２ｂ Ｂステージ樹脂 ３ エッチングレジスト ４ 内層導体回路 ５ 外層導体回路 ６ ビアホール形成用開口 ７ ビアホール ８ 銅箔 ９ スルーホール １０ スルーホールランド １１ 粗化層 １２ 無電解銅めっき膜 １３ 電解銅めっき膜 １４ ソルダーレジスト層 １５ ニッケルめっき層 １６ 金めっき層 １７ はんだバンプ １９ プレス板 Reference Signs List 1 substrate 2 interlayer resin insulating layer 2a resin film 2b B stage resin 3 etching resist 4 inner layer conductor circuit 5 outer layer conductor circuit 6 opening for via hole formation 7 via hole 8 copper foil 9 through hole 10 through hole land 11 roughened layer 12 electroless copper Plating film 13 Electrolytic copper plating film 14 Solder resist layer 15 Nickel plating layer 16 Gold plating layer 17 Solder bump 19 Press plate
───────────────────────────────────────────────────── フロントページの続き (72)発明者 関根 浩司 岐阜県揖斐郡揖斐川町北方１−１ イビデ ン株式会社大垣北工場内 Ｆターム(参考） 5E346 AA06 AA12 AA15 AA25 AA26 AA32 AA38 AA43 BB01 CC08 CC09 CC31 CC32 CC37 DD02 DD22 DD33 DD47 EE33 EE35 EE38 FF12 GG15 GG17 GG23 GG27 GG28 HH11 HH18 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Koji Sekine 1-1, Ibagawa-cho, Ibi-gun, Ibi-gun, Gifu F-term in the Ogaki-kita Plant (reference) 5E346 AA06 AA12 AA15 AA25 AA26 AA32 AA38 AA43 BB01 CC08 CC09 CC31 CC32 CC37 DD02 DD22 DD33 DD47 EE33 EE35 EE38 FF12 GG15 GG17 GG23 GG27 GG28 HH11 HH18
Claims (9)
に、樹脂絶縁層を介して外層の導体回路が形成され、上
記コア基板の両側にそれぞれ配置された導体回路間の電
気的接続が、コア基板に形成されたスルーホールによっ
て行なわれるようなビルドアップ構造を有する多層プリ
ント配線板において、 上記樹脂絶縁層は、所定の加熱条件下において軟化する
ような樹脂フィルムと、その樹脂フィルムの片面に貼付
けられたＢステージ樹脂とを含むフィルム状絶縁材から
形成され、上記スルーホールランドを含む内層導体回路
の側面とコア基板の表面とで規定される凹部およびスル
ーホールの内壁によって規定される貫通穴内に、加熱プ
レスによって充填されていることを特徴とする多層プリ
ント配線板。An outer conductor circuit is formed on a conductor circuit formed on both sides of a core substrate via a resin insulating layer, and electrical connection between the conductor circuits disposed on both sides of the core substrate is established. In a multilayer printed wiring board having a build-up structure such as that performed by a through hole formed in a core substrate, the resin insulating layer includes a resin film that softens under predetermined heating conditions, and one side of the resin film. Formed from a film-like insulating material containing a B-stage resin adhered to the inner surface of the inner-layer conductor circuit including the through-hole land and the surface of the core substrate, and a penetration defined by an inner wall of the through-hole. A multilayer printed wiring board, wherein the holes are filled by a hot press.
ィルムとＢステージ樹脂は、同一の樹脂組成からなるこ
とを特徴とする請求項１に記載の多層プリント配線板。2. The multilayer printed wiring board according to claim 1, wherein the resin film and the B-stage resin constituting the film-shaped insulating material have the same resin composition.
リオレフィン系樹脂またはエポキシ系樹脂を主成分とし
た樹脂フィルムと、５０〜８０重量％の樹脂成分からな
るＢステージ樹脂とを含むことを特徴とする請求項２に
記載の多層プリント配線板。3. The method according to claim 1, wherein the film-like insulating material includes a resin film containing a thermosetting polyolefin resin or an epoxy resin as a main component and a B-stage resin composed of 50 to 80% by weight of a resin component. The multilayer printed wiring board according to claim 2, wherein:
体回路上に、樹脂絶縁層を介して外層の導体回路が形成
され、上記コア基板の両側に配置された導体回路間の電
気的接続が、コア基板に形成されたスルーホールによっ
て行なわれるビルドアップ構造を有する多層プリント配
線板を製造するに当たって、その製造工程中に、少なく
とも下記 (a)〜(ｄ) の工程、すなわち、(a)コア基板を
貫通するスルーホールを形成する工程、(b)そのスルー
ホールが開口するコア基板の両面に内層導体回路をそれ
ぞれ形成する工程、(c)上記スルーホールランドを含ん
だ内層導体回路の上面および側面と、スルーホール内壁
面とに粗化層を形成する工程、(d)その粗化層が形成さ
れたコア基板の表面に、所定の加熱条件下において軟化
するような樹脂フィルムと、その樹脂フィルムの片面に
貼付けられたＢステージ樹脂とを含むフィルム状絶縁材
を、そのＢステージ樹脂面を基板表面に向けて貼付け、
前記フィルム状絶縁材を所定の圧力でプレスした後、所
定の温度で加熱し、あるいは所定の圧力でプレスすると
同時に所定の温度で加熱して、上記Ｂステージ樹脂を軟
化せしめて、スルーホールランドを含んだ内層導体回路
の側面と基板表面とで規定される凹部およびスルーホー
ルの内壁面によって規定される貫通穴内に、その軟化し
たＢステージ樹脂を充填するとともに、そのＢステージ
樹脂上の樹脂フィルムを軟化せしめ、その後、両者を硬
化させる工程、を含むことを特徴とする多層プリント配
線板の製造方法。4. An outer layer conductor circuit is formed on a conductor circuit formed on both surfaces of the core substrate via a resin insulating layer, and electrical connection between the conductor circuits disposed on both sides of the core substrate is established. In manufacturing a multilayer printed wiring board having a build-up structure formed by through holes formed in a core substrate, at least the following steps (a) to (d) during the manufacturing process, that is, (a) core A step of forming a through hole penetrating the substrate, (b) a step of forming an inner layer conductor circuit on each side of the core substrate where the through hole is opened, and (c) an upper surface of the inner layer conductor circuit including the through hole land and Side, and the step of forming a roughened layer on the inner wall surface of the through hole, (d) on the surface of the core substrate on which the roughened layer is formed, a resin film that softens under predetermined heating conditions, Of a film-shaped insulating material and a sticking was B-stage resin on one surface of the resin film, sticking toward the B-stage resin surface on the substrate surface,
After pressing the film-shaped insulating material at a predetermined pressure, heating at a predetermined temperature, or pressing at a predetermined pressure and simultaneously heating at a predetermined temperature to soften the B-stage resin, thereby forming a through-hole land. The softened B-stage resin is filled in the through-hole defined by the concave portion defined by the side surface of the inner conductor circuit and the substrate surface, and the inner wall surface of the through-hole, and the resin film on the B-stage resin is filled. A method for softening and then hardening the two. A method for manufacturing a multilayer printed wiring board.
ィルムとＢステージ樹脂は、同一の樹脂組成からなるこ
とを特徴とする請求項４に記載の多層プリント配線板。5. The multilayer printed wiring board according to claim 4, wherein the resin film and the B-stage resin constituting the film-like insulating material have the same resin composition.
は、熱硬化性のポリオレフィン系樹脂またはエポキシ系
樹脂を主成分として形成された樹脂フィルムと、５０〜
８０重量％の樹脂成分からなるＢステージ樹脂とからな
ることを特徴とする請求項５に記載の多層プリント配線
板の製造方法。6. The film-like insulating material in the step (d) comprises a resin film formed mainly of a thermosetting polyolefin-based resin or an epoxy-based resin;
6. The method for producing a multilayer printed wiring board according to claim 5, comprising a B-stage resin comprising 80% by weight of a resin component.
脂を主成分とする樹脂フィルムおよびそのＢステージ樹
脂からなるフィルム状絶縁材の加熱プレスは、圧力１〜
５０kgf／cm2 、温度５０〜２５０℃、加熱プレス時間
１〜１２０分間の条件にて行うことを特徴とする請求項
６に記載の多層プリント配線板の製造方法。7. The heating press of the resin film containing a polyolefin resin as a main component and the film-like insulating material comprising the B-stage resin in the step (d) is performed under a pressure of 1 to 3.
7. The method for producing a multilayer printed wiring board according to claim 6, wherein the method is performed under the conditions of 50 kgf / cm < 2 >, a temperature of 50 to 250 [deg.] C., and a heating press time of 1 to 120 minutes.
主成分とする樹脂フィルムおよびそのＢステージ樹脂か
らなるフィルム状絶縁材の加熱プレスは、圧力１〜５０
kgf／cm2 、温度５０〜２００℃、加熱プレス時間１〜
７０分間の条件にて行うことを特徴とする請求項６に記
載の多層プリント配線板の製造方法。8. In the step (d), the heating press of the resin film containing an epoxy resin as a main component and the film-like insulating material made of the B-stage resin is performed under a pressure of 1 to 50.
kgf / cm 2 , temperature 50-200 ° C, hot press time 1 ~
The method according to claim 6, wherein the method is performed under a condition of 70 minutes.
を加熱しながら金属板または金属ロールを押圧して行う
ことを特徴とする請求項４ないし８のいずれかに記載の
多層プリント配線板の製造方法。9. The multilayer printed wiring board according to claim 4, wherein the step (d) is performed by pressing a metal plate or a metal roll while heating the film-shaped insulating material. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27677699A JP4291469B2 (en) | 1999-09-29 | 1999-09-29 | Multilayer printed wiring board and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27677699A JP4291469B2 (en) | 1999-09-29 | 1999-09-29 | Multilayer printed wiring board and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001102751A true JP2001102751A (en) | 2001-04-13 |
| JP4291469B2 JP4291469B2 (en) | 2009-07-08 |
Family
ID=17574209
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27677699A Expired - Fee Related JP4291469B2 (en) | 1999-09-29 | 1999-09-29 | Multilayer printed wiring board and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4291469B2 (en) |
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| JP2008153580A (en) * | 2006-12-20 | 2008-07-03 | Shinko Electric Ind Co Ltd | Method for manufacturing multilayer wiring board |
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|---|---|---|---|---|
| JP2004214586A (en) * | 2002-11-14 | 2004-07-29 | Kyocera Corp | Multilayer wiring board |
| JP2008153580A (en) * | 2006-12-20 | 2008-07-03 | Shinko Electric Ind Co Ltd | Method for manufacturing multilayer wiring board |
| JP2009206250A (en) * | 2008-02-27 | 2009-09-10 | Kyocera Corp | Wiring board and mounting structure |
| JP2010129725A (en) * | 2008-11-27 | 2010-06-10 | Kyocera Corp | Wiring substrate, mounting structure, and electronic apparatus |
| JP2014090079A (en) * | 2012-10-30 | 2014-05-15 | Ibiden Co Ltd | Printed wiring board |
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