JP2001093820A - Mark, alignment mark, alignment discrepnacy measurement mark and semiconductor wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mark which can be recognized by the detector of an optical system, even if the manufacturing process, etc., of a semiconductor device are varied end hence even if interference conditions of a light are changed. SOLUTION: A mark 3 is composed of a plurality of 1st patterns which have pairs of parallel sides with spacings W1 which are smaller than the resolution of a mark detector therebetween and a plurality of 2nd patterns 2 which have pairs of parallel sides with spacings W2 which are smaller than the resolution of the mark detector and different from the spacings W1 therebetween and are arranged, so as to have one of each pair of sides close to one of each pair of sides of the 1st pattern 1 with a spacing Ws smaller than the resolution of the mark detector therebetween. With this constitution, at least one of the patterns between the 1st patterns and the 2nd patterns satisfy the interference conditions of a light which can be recognized by the mark detector.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mark which can be well recognized over a wide visible light band, and more particularly, to alignment of a plurality of patterns used for manufacturing a semiconductor device and confirmation of misalignment between the patterns. The present invention relates to an alignment mark and a misalignment measurement mark used in the method, and a photomask and a semiconductor wafer having these marks.

[0002]

2. Description of the Related Art FIG. 20 is a configuration diagram of a conventional alignment mark used for aligning a plurality of patterns in manufacturing a semiconductor device. FIG. 20A shows the whole view of the alignment mark 65, and FIG.
FIG. 5 is an enlarged view of a mark 63 constituting 5. The alignment mark 65 is composed of nine marks 63 inside the mark area 4 as shown in FIG. These nine marks 63 are rectangular and arranged such that their long sides are parallel and equidistant, and the short sides are arranged in a straight line. The length of the short side of the mark 63 is about 2 μm to 6 μm. The mark 63 is 5 marks as shown in FIG.
It is composed of three rectangular patterns 61. These 5
The two patterns 61 are arranged so that the long sides are parallel and at equal intervals, and the short sides are arranged in a straight line. The length W1 of the short side of the pattern 61 is the interval Ws of the pattern 61.
, The length W1 of the short side is 0.2 μm.
The size is about m to 0.6 μm.

The size of about 0.2 μm to about 0.6 μm cannot be recognized by an optical mark detector.
Although 1 is not recognized as an individual pattern, it is recognized as one mark 63. Thus, the mark 63
Is constituted by the pattern 61, when the miniaturization of the semiconductor device advances and the filling of a groove having a width about the length of the short side of the pattern 61 or a flattening technique represented by CMP is applied, If the groove having the size of the mark 63 is used as a mark as it is, the groove of the mark is too large for embedding and flattening, so that a dent is formed above the mark and particles are prevented from accumulating in the dent.

However, a mark 63 having a pattern 61
In the above, particles can be reduced, but sometimes cannot be recognized by an optical mark detector.

[0005]

SUMMARY OF THE INVENTION The present inventors have compared in detail the cases where recognition is possible with the mark detector of this optical system and the cases where recognition is not possible, and have clarified the following reasons why recognition is not possible.

FIG. 21 shows a mark 6 having a pattern 61.
FIG. 3 is a diagram illustrating the reason why the mark cannot be recognized by the optical mark detector. FIG. 21 is a cross-sectional view of a mark 63 of an alignment mark 65 provided on a semiconductor wafer on which a semiconductor device is formed. The mark 63 includes a semiconductor substrate 8 which is a semiconductor wafer, a silicon nitride film 9 formed on the semiconductor substrate 8, and five groove-shaped patterns 6 formed on the semiconductor substrate 8 through the silicon nitride film 9.
1.

FIG. 21A shows a case where a mark 63 having a pattern 61 can be recognized by a mark detector of an optical system. Recognition by the optical recognition device means that the wavefront 11 of the standing wave 10 of light having a detectable wavelength does not coincide with the pattern 61 portion and the other portions, and weakens due to interference of light with each other, That is, it becomes identifiable as compared to other parts of the light that do not weaken.

FIG. 21B shows a case where a mark 63 having a pattern 61 cannot be recognized by a mark detector of an optical system. In the shape of the mark 63, only the thickness of the silicon nitride film 9 is different from that of FIG. As a result, the wavefront 1 of the standing wave 10 of light having a detectable wavelength
1 coincides with the pattern 61 portion and the other portions, and is strengthened by mutual interference of light, which makes identification more difficult than other portions that similarly enhance light.

FIG. 21C also shows a case where a mark 63 having a pattern 61 cannot be recognized by an optical mark detector. In the shape of the mark 63, only the depth Dc of the groove in the semiconductor substrate 8 of the pattern 61 is different from the depth Da of the groove in FIG. As a result, the wavefront 11 of the standing wave 10 of light having a detectable wavelength is
The part and the other part coincide with each other, and the light interferes with each other, thereby increasing the intensity. This makes it more difficult to identify as compared with other parts that also enhance the light.

As described above, the mark 63 having the pattern 61
However, it is considered that the reason why the mark detector of the optical system cannot recognize the light is that the thickness of the silicon nitride film 9 and the depth of the groove change due to a change in the manufacturing process of the semiconductor device, and the light interference condition changes. .

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device, which can be performed even when the manufacturing process of a semiconductor device changes and the light interference condition changes. It is to provide a mark recognizable by a detector.

Another object of the present invention is to provide an alignment mark that can be recognized by a mark detector of an optical system even when the manufacturing process of a semiconductor device or the like changes and the light interference condition changes. .

Another object of the present invention is to provide a misalignment measuring mark recognizable by a mark detector of an optical system even when a manufacturing process of a semiconductor device or the like fluctuates and light interference conditions change. It is in.

Another object of the present invention is to provide a photomask that can be recognized by a mark detector of an optical system even when a manufacturing process of a semiconductor device or the like changes and interference conditions of light change. .

[0015] Finally, another object of the present invention is to provide a semiconductor device, which can be manufactured even when the manufacturing process of the semiconductor device fluctuates and the light interference condition changes.
An object of the present invention is to provide a semiconductor wafer recognizable by an optical mark detector.

[0016]

Further, the present inventors have conducted a detailed study on fluctuations in the manufacturing process of a semiconductor device and the like and light interference conditions. FIG. 22 is a graph showing the relationship between the pattern width W1 and the pattern depth, and the relationship between the pattern width W1 and the mark detection signal intensity. From this, it was found that the larger the pattern width W1 was, the deeper the pattern tended to be. This tendency was considered to be due to the microloading effect of dry etching for forming the pattern grooves. From this tendency, it has been found that when dry etching is performed under a certain condition, the pattern depth changes according to the pattern width W1, the light interference condition changes, and the mark detection signal intensity changes.

In order to achieve the above object, the first aspect of the present invention is described.
The feature of the first pattern is a rectangle having a pair of parallel sides having a width equal to or less than the resolution of the mark detector, and a plurality of first patterns arranged so that the sides face each other. A rectangular shape having a pair of parallel sides having a width different from the width of the pair of parallel sides of the first pattern, wherein one side of the pair of sides corresponds to one side of the pair of sides of the first pattern and the mark detector; Is a mark composed of a first pattern and a plurality of second patterns that are alternately arranged so as to be adjacent to each other. Here, the “resolution of the mark detector” is λ /
(NA (1 + s)) (where λ is the wavelength of the detection light, NA is the numerical aperture of the detector, and s is the partial coherence factor of the detector). Specifically, the resolution of a mark detector used for manufacturing a semiconductor device is on the order of submicron. As a result, even if the thickness of the silicon nitride film or the like or the depth of the groove changes due to a change in the manufacturing process of the semiconductor device, either the first pattern or the second pattern detects the mark of the optical system. Is detected by the
The minimum value of the mark detection signal strength is unlikely to be small.

A first feature of the present invention is that the pair of sides of the first pattern is divided into segments each having a length equal to or less than the resolution of the mark detector with an interval equal to or less than the resolution of the mark detector. It is a target. Further, the first feature of the present invention is effective because a pair of sides of the second pattern are divided into lengths equal to or less than the resolution of the mark detector at intervals equal to or less than the resolution of the mark detector. It is. This allows
When a resist or spin-on-glass is applied to a semiconductor wafer, the resist or spin-on-glass flows over the divided intervals, and the applied film thickness can be made uniform.

A first feature of the present invention is a rectangle having a pair of parallel sides having a width equal to or less than the resolution of the mark detector,
A first pattern in which a plurality of sides are arranged so as to face each other is divided by a width equal to or less than the resolution of the mark detector and a length equal to or less than the resolution of the mark detector with an interval equal to or less than the resolution of the mark detector. And a first side of the pair of sides of the first pattern which is arranged at an interval less than or equal to the resolution of the mark detector. A similar effect can be obtained by being configured with a plurality of second patterns that are alternately arranged so as to be adjacent to each other. As a result, since either the first pattern or the second pattern is detected by the mark detector of the optical system, the minimum value of the mark detection signal intensity is not easily reduced.

The first feature of the present invention is effective when the lengths of both sides of the pair of first patterns are equal to the lengths of both sides of the pair of sides of the second pattern. As a result, a line passing through the center of both sides of both patterns and perpendicular to both sides becomes a common center line, so that the mark can be recognized only by the first pattern or only the second pattern by the mark detection device. However, if alignment is performed using the center line, the alignment can be performed at the same position regardless of which is recognized.

The first feature of the present invention is effective because the entire center of the plurality of first patterns and the entire center of the plurality of second patterns are arranged so as to coincide with each other. . As a result, the mark can be recognized only by the first pattern or only the second pattern by the mark detecting device. However, the mark is located between the center of the first pattern and the center of the second pattern. Are the same, so if alignment is performed using the center, the alignment can be performed at the same position regardless of which is recognized.

A second feature of the present invention is that a plurality of marks according to the first feature of the present invention are alignment marks arranged in parallel at equal intervals. As a result, even if the film thickness of the silicon nitride film or the like or the depth of the groove fluctuates due to fluctuations in the manufacturing process of the semiconductor device or the like, either the first pattern or the second pattern becomes the mark of the optical system. Since the detection is performed by the detector, it is possible to provide an alignment mark in which the minimum value of the mark detection signal intensity is not easily reduced.

A third feature of the present invention is that four marks, which are the first features of the present invention, are misalignment measuring marks arranged along four sides of a square. As a result, similarly to the second feature of the present invention, it is possible to provide a misalignment measurement mark in which the minimum value of the mark detection signal intensity is unlikely to be small.

A fourth feature of the present invention resides in a photo substrate composed of a glass substrate and two alignment marks of the second feature of the present invention provided on the glass substrate and rotated by 90 degrees. It is a mask. Also,
A fourth feature of the present invention is that a similar effect can be obtained by comprising a glass substrate and four misalignment measurement marks which are the third features of the present invention provided on the glass substrate. Can be. Further, a fourth feature of the present invention is that a glass substrate, two alignment marks of the second feature of the present invention provided on the glass substrate and rotated by 90 degrees, and provided on the glass substrate. 4
A similar effect can also be obtained by being configured with the misalignment measurement mark which is the third feature of the present invention. For these reasons, even if the film thickness of the silicon nitride film or the like or the depth of the groove fluctuates due to fluctuations in the manufacturing process of the semiconductor device or the like, either the first pattern or the second pattern does not affect the optical system. Since the mark is detected by the mark detector, it is possible to provide a photomask having an alignment mark and a misalignment measurement mark in which the minimum value of the mark detection signal intensity is not easily reduced.

A fifth feature of the present invention resides in a semiconductor comprising a semiconductor substrate and a plurality of alignment marks according to the second feature of the present invention provided on the semiconductor substrate and rotated by 90 degrees. It is a wafer. The fifth feature of the present invention is also the same when the semiconductor substrate is provided with four or more misalignment measuring marks which are the third features of the present invention provided on the semiconductor substrate. The effect can be obtained. Further, a fifth feature of the present invention is that a semiconductor substrate, a plurality of alignment marks provided on the semiconductor substrate and rotated by 90 degrees, which are second features of the present invention, and provided on the semiconductor substrate. A similar effect can also be obtained by comprising four or more of the three or more misalignment measurement marks which are the third feature of the present invention. For these reasons, even if the film thickness of the silicon nitride film or the like or the depth of the groove fluctuates due to fluctuations in the manufacturing process of the semiconductor device or the like, either the first pattern or the second pattern does not affect the optical system. Since the detection is performed by the mark detector, it is possible to provide a semiconductor wafer having an alignment mark and a misalignment measurement mark in which the minimum value of the mark detection signal intensity is not easily reduced.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimension, the ratio of the thickness of each layer, and the like are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. In addition, it goes without saying that parts having different dimensional relationships and ratios are included between the drawings.

(Embodiment 1) FIG. 1 is a configuration diagram of a mark according to Embodiment 1 of the present invention. The mark 3 according to the first embodiment of the present invention has a rectangular first pattern 1 having a pair of parallel sides with an interval W1 equal to or less than the resolution of the mark detector.
And a pair of parallel sides having a distance W2 different from the distance W1 below the resolution of the mark detector, and one side of the pair of sides corresponds to one side of a pair of sides of the first pattern. And four rectangular second patterns 2 arranged close to an interval Ws smaller than the resolution of the mark detector. Further, the first patterns 1 and the second patterns 2 are alternately arranged so as to be adjacent to each other, and the centers of the five first patterns 1 and the centers of the four second patterns 2 are arranged so as to coincide with each other. Have been. The first pattern 1 and the second pattern 2 are not limited to rectangles, but may be parallelograms. Note that, in the alignment mark 5 described with reference to FIG.
Was set to 0.5 μm, the interval W2 was set to 0.3 μm, and the interval Ws was set to 0.3 μm.

FIG. 2 is a configuration diagram of the alignment mark according to the first embodiment of the present invention. The alignment mark 5 according to the first embodiment of the present invention has nine marks 3 described in FIG. 1, and the nine marks 3 are arranged in parallel at equal intervals.

FIG. 3 is a top view of the photomask according to the first embodiment of the present invention. The photomask according to the first embodiment of the present invention is provided on a glass substrate 6, a circuit pattern 7 such as a semiconductor device provided on the glass substrate 6, and a circuit pattern 7 provided on the glass substrate 6 and rotated by 90 degrees. It is composed of two alignment marks 5. The alignment mark 5 is the same as the alignment mark described with reference to FIG.

FIG. 4 is a top view of the semiconductor wafer according to the first embodiment of the present invention. The semiconductor wafer according to the first embodiment of the present invention includes a semiconductor substrate 8, a circuit pattern 7 such as a semiconductor device provided on the semiconductor substrate 8, and a positional relationship provided on the semiconductor substrate 8 and rotated by 90 degrees. And a plurality of alignment marks 5 to be formed. The alignment mark 5 is the same as the alignment mark described with reference to FIG.

In manufacturing a semiconductor device, the circuit pattern 7 is transferred onto a semiconductor substrate 8 by a photolithography method using a photomask shown in FIG. At this time, the alignment mark 5 is also transferred onto the semiconductor substrate 8. Next, another circuit pattern 7 is superimposed on the circuit pattern 7 on the semiconductor substrate 8 and transferred. At this time, the position of the alignment mark 5 on the semiconductor substrate 8 is detected and the position of the photomask is measured in advance or simultaneously to superimpose the pattern 7 of the other circuit and the pattern 7 on the wafer. Thus, the amount of movement required for the superposition is obtained, and the semiconductor substrate 8 is moved to a desired position and exposed, whereby different circuit patterns 7 can be superposed in a predetermined positional relationship.

FIG. 5 is a part of a cross-sectional view of the mark 3 of the alignment mark 5 provided on the semiconductor substrate according to the first embodiment of the present invention in the II direction of FIG. The mark 3 includes a semiconductor substrate 8, a silicon nitride film 9 formed on the semiconductor substrate 8, and a first pattern having a wide and deep groove shape formed in the semiconductor substrate 8 through the silicon nitride film 9. 1
And a second pattern 2 having a small width and a small width.
Such a cross-sectional structure is formed in a process of manufacturing a trench capacitor in manufacturing a DRAM having a trench capacitor or the like. The reason why the depth of the first pattern 1 is deeper than that of the second pattern 2 is considered to be due to the microloading effect of dry etching for forming a groove in the pattern.

FIG. 6 is a graph showing the relationship between the thickness of the silicon nitride film and the mark detection signal intensity. A mark indicates the mark detection signal strength of the mark 3 according to the first embodiment of the present invention, a mark indicates the mark detection signal strength when the mark is formed only by the first pattern, and a mark indicates the mark detection signal strength. , The mark detection signal intensity when a mark is formed only with the second pattern. From this, the mark detection signal intensity (marked by ○) of the mark 3 according to the first embodiment of the present invention takes an intermediate value between the marks △ and □ regardless of the vertical relationship between the marks △ and □. I understood. For example, when the thickness of the silicon nitride film is 100 nm as the center condition of the manufacturing, the mark ○ indicating the effect of the present invention is slightly smaller than the mark □, but the change in the strength is small with respect to the change in the film thickness. Stable alignment was achieved. Further, for the film thickness shown in FIG. 6, the mark 表 す representing the effect of the present invention is larger than the mark □ and almost the same size as the mark に お い て at the minimum value, and the minimum value is hardly reduced. Was thought to be.

FIG. 7 shows that the mark detection signal strength of the mark 3 having the first pattern 1 and the second pattern 2 is the mark of the mark having only the first pattern 1 and the mark having only the second pattern 2. It is a figure explaining the reason which becomes an intermediate value of detection signal intensity.

FIG. 7A shows a case where the mark detection signal strength of the first pattern 1 is stronger than the mark detection signal strength of the second pattern 2. Wavefront 11 of standing wave 10 of light having a wavelength that can be detected by an optical mark detection device
However, the light does not coincide with the first pattern 1 and the other parts, and is weakened by interference of the light of each other, and can be distinguished from other parts where the light is not weakened. In addition, standing wave 1
In the second pattern 2 in which the zero wavefront 11 coincides with other portions, the second pattern cannot be identified. Therefore,
Only the first pattern contributes to the mark detection signal strength, but the mark 3 has a smaller number of first patterns due to the arrangement of the second patterns compared to the case where only the first patterns are spread. The mark detection signal intensity decreases accordingly.

FIG. 7B shows a case where the mark detection signal strength of the second pattern 2 is stronger than the mark detection signal strength of the first pattern 1. In the shape of the mark 3, only the thickness of the silicon nitride film 9 is different from that of FIG. As a result, the conditions of the interference between the first pattern 1 and the second pattern are opposite to those in FIG.

FIG. 7C also shows a case where the mark detection signal strength of the second pattern 2 is stronger than the mark detection signal strength of the first pattern 1. In the shape of the mark 3, only the groove depths D1c and D2c in the semiconductor substrate 8 of the patterns 1 and 2 are different from the groove depths D1a and D2a in FIG. As a result, the conditions of the interference between the first pattern 1 and the second pattern are opposite to those in FIG.

As described above, even if the thickness of the silicon nitride film 9 and the depth of the groove change due to the change in the manufacturing process of the semiconductor device, either the first pattern 1 or the second pattern 2
It is considered that the minimum value of the mark detection signal intensity is unlikely to be small because it is detected by the mark detector of the optical system. In addition, the mark 3 shown in FIG. 1 can be recognized only by the five first patterns 1 or only the four second patterns 2 by the mark detection device. 1 pattern 1 center line and 4 second patterns 2
Since the alignment is performed using the center line, the alignment can be performed at the same position regardless of which is recognized.

(First Modification of First Embodiment) FIG. 8 is a configuration diagram of a mark according to a first modification of the first embodiment of the present invention. The mark 23 according to the first modification of the first embodiment of the present invention includes three rectangular first patterns 21 having a pair of parallel sides having an interval W1 equal to or less than the resolution of the mark detector, and the mark detector. It has a pair of parallel sides divided at a distance W2 equal to or less than the resolution and a length L2 equal to or less than the resolution of the mark detector, and one side of the pair of sides corresponds to a pair of sides of the first pattern. It has one second side and two second patterns 22 arranged close to an interval Ws smaller than the resolution of the mark detector. Further, the first patterns 21 and the second patterns 22 are alternately arranged so as to be adjacent to each other, and the centers of the three first patterns 21 and the centers of the two second patterns 2 are arranged so as to coincide with each other. Have been. Interval L5 of division of second pattern 22
Is preferably as small as possible in order to increase the number of second patterns 22.

By using the mark 23 as the alignment mark 5 in FIG. 2, the same effect as in FIG. 6 can be obtained. This is considered to be due to the fact that the micro-loading effect is small and large due to the dry etching in the groove formation even between the first pattern 21 and the second pattern 22.

(Modification 2 of Embodiment 1) FIG. 9 is a configuration diagram of a mark according to Modification 2 of Embodiment 1 of the present invention. The mark 33 according to the second modification of the first embodiment of the present invention has a pair of parallel sides divided by a distance W1 equal to or less than the resolution of the mark detector and a length L1 equal to or less than the resolution of the mark detector. 1 pattern 31 and an interval W2 less than the resolution of the mark detector and a length L less than the resolution of the mark detector.
It has a pair of parallel sides divided into two, and one side of the pair approaches one side of the pair of sides of the first pattern and an interval Ws smaller than the resolution of the mark detector. And four second patterns 32 to be arranged. Further, the first patterns 31 and the second patterns 32 are alternately arranged so as to be adjacent to each other, and the centers of the five first patterns 31 and the centers of the four second patterns 2 are arranged so as to coincide with each other. Have been. Interval Ls of division of first and second patterns 31 and 32
It is desirable that 1 and Ls2 be as small as possible in order to increase the number of patterns 31 and 32. FIG.
0 in the alignment mark 35 described with reference to FIG.
The interval W1 to 0.5 μm, the interval W2 to 0.3 μm,
The interval Ws is 0.3 μm, and the lengths L1 and L2 are 1.0 μm.
Then, the division intervals Ls1 and Ls2 were set to 0.4 μm. FIG. 10 is a configuration diagram of an alignment mark 35 according to a second modification of the first embodiment of the present invention. Embodiment 1 of the present invention
The alignment mark 3 according to the modified example 2 has nine marks 33 described in FIG. 9, and the nine marks 33 are arranged in parallel at equal intervals.

By using the alignment mark 35, an effect equivalent to that of FIG. 6 could be obtained. This is considered to be due to the fact that the micro-loading effect is small and large due to the dry etching in the groove formation even between the first pattern 31 and the second pattern 32 in FIG.

(Embodiment 2) FIG. 11 shows Embodiment 2 of the present invention.
3 is a configuration diagram of a mark according to FIG. The mark 4 according to the second embodiment of the present invention includes three rectangular first patterns 4 each having a pair of parallel sides with an interval W1 equal to or less than the resolution of the mark detector and an interval equal to or less than the resolution of the mark detector. W1 has a pair of parallel sides having an interval W2 different from W1, and one side of the pair of sides is equal to one side of the pair of sides of the first pattern and an interval Ws smaller than the resolution of the mark detector. And two rectangular second patterns 4 arranged close to each other. The first patterns 41 and the second patterns 42 are alternately arranged so as to be adjacent to each other, and the center of the three first patterns 4 and 2
The centers of the two second patterns 4 are arranged so as to coincide with each other. In the misalignment measurement mark 45 described with reference to FIG. 12, the interval W1 in FIG.
The interval W2 was set to 0.3 μm, and the interval Ws was set to 0.3 μm.

FIG. 12 is a configuration diagram of the misalignment measurement mark 45 according to the second embodiment of the present invention. The misalignment measurement mark 45 according to the second embodiment of the present invention has the four marks 43 described in FIG. 11, and the four marks 43 are arranged along four sides of the square. The misalignment measurement mark 45 is a misalignment measurement mark 45 formed on a semiconductor wafer before and after to measure misalignment.
Of these, it is a misalignment measurement mark formed first, which is a so-called main scale.

FIG. 13 is a top view of a photomask according to the second embodiment of the present invention. The photomask according to the second embodiment of the present invention includes a glass substrate 6, a circuit pattern 7 such as a semiconductor device provided on the glass substrate 6, and a glass substrate 6.
It is provided with four misalignment measurement marks 45 provided on the top and outside the circuit pattern 7. The misalignment measurement mark 45 is the same as the misalignment measurement mark 45 described with reference to FIG.

FIG. 14 is a top view of a semiconductor wafer according to the second embodiment of the present invention. The semiconductor wafer according to the second embodiment of the present invention includes a semiconductor substrate 8, a circuit pattern 7 such as a semiconductor device provided on the semiconductor substrate 8, and a plurality of integrated circuits provided between the circuit patterns 7 on the semiconductor substrate 8. And a displacement measurement mark 45. The misalignment measurement mark 45 is the same as the misalignment measurement mark 45 described with reference to FIG.

In the manufacture of the semiconductor device, the circuit pattern 7 is transferred onto the semiconductor substrate 8 by a photolithography method using a photomask shown in FIG. At this time, the misalignment measurement mark 45 to be the main scale is also transferred onto the semiconductor substrate 8. Next, another circuit pattern 7 is superimposed on the circuit pattern 7 on the semiconductor substrate 8 and transferred. At this time,
Using a photomask on which a misalignment measurement mark 46 to be vernier with the pattern 7 of this other circuit is used, FIG.
As shown in FIG. 5, a misalignment measurement mark 46 serving as a sub-scale on the photomask is transferred inside the misalignment measurement mark 45 serving as the main scale on the semiconductor substrate 8. By measuring the positional relationship between these main and sub misalignment measuring marks 45 and 46 by using a misalignment measuring device equipped with a mark detecting device, it becomes possible to correct the photolithography method at the time of transfer.

The same effect as that of FIG. 6 can be obtained by using the mark 45 for measuring misalignment. This corresponds to the first pattern 41 and the second pattern 42 in FIG.
It is considered that the magnitude of the microloading effect is caused by the dry etching in the groove formation even during the period between the steps.
Also, the mark 43 has three first
Can be recognized, or only the two second patterns 42 can be recognized. However, the center line of the three first patterns 41 and the two second patterns 4
Since the center line coincides with the center line of No. 2, if the misalignment is measured using the center line, the net misalignment amount can be measured regardless of which is recognized.

(Modification of Second Embodiment) FIG. 16 is a view showing the configuration of a mark according to a modification of the second embodiment of the present invention. The mark 53 according to the modified example of the second embodiment of the present invention has a rectangular first shape having a pair of parallel sides having an interval W1 equal to or less than the resolution of the mark detector and a length L equal to or greater than the resolution of the mark detector.
And a pair of parallel sides having a length W and an interval W2 smaller than or equal to the resolution of the mark detector, and one side of the pair of sides is a pair of the first pattern 51. Side 1
It has a large number of second patterns 52 arranged close to the side and an interval Ws smaller than the resolution of the mark detector. Further, the first patterns 51 and the second patterns 52 are alternately arranged so as to be adjacent to each other, and a large number of first patterns 5 are provided.
Both end points on both sides of one pair of parallel sides and both end points on both sides of a pair of parallel sides of many second patterns 52 are arranged on a straight line. In the misalignment measurement mark 55 described with reference to FIG. 17, the interval W1 in FIG.
5 μm, interval W2 to 0.3 μm, interval Ws to 0.3
μm, the length L was set to 2.0 μm, the number of the first patterns 51 was set to 15, and the number of the second patterns 52 was set to 14. FIG. 17 is a configuration diagram of a misalignment measurement mark 55 according to a modification of the second embodiment of the present invention. Misalignment measurement mark 55 according to a modification of the second embodiment of the present invention
Has four marks 53 described in FIG. 16, and the four marks 53 are arranged along four sides of a square.

The same effect as that of FIG. 6 can be obtained by using the misalignment measurement mark 55. This corresponds to the first pattern 51 and the second pattern 52 in FIG.
It is considered that the magnitude of the microloading effect is caused by the dry etching in the groove formation even during the period between the steps.
In addition, the mark detection device can recognize only the fifteen first patterns 51 or the fourteen second patterns 52 in the mark detection device.
Since the center lines of the five first patterns 51 coincide with the center lines of the fourteen second patterns 52, if the misalignment is measured using the center lines, whichever is recognized. The net misalignment can be measured.

(Embodiment 3) FIG. 18 shows Embodiment 3 of the present invention.
3 is a top view of the photomask according to FIG. Embodiment 3 of the present invention
The photomask according to (1) includes a glass substrate 6, a circuit pattern 7 such as a semiconductor device provided on the glass substrate 6,
Consisting of two alignment marks 5 provided on the glass substrate 6 and rotated by 90 degrees and four alignment measurement marks 45 provided on the glass substrate 6 and provided outside the circuit pattern 7. Is done. The alignment mark 5 is the same as the alignment mark described with reference to FIG. The misalignment measurement mark 45 is the same as the misalignment measurement mark 45 described with reference to FIG.

FIG. 19 is a top view of a semiconductor wafer according to the third embodiment of the present invention. The semiconductor wafer according to the third embodiment of the present invention includes a semiconductor substrate 8, a circuit pattern 7 such as a semiconductor device provided on the semiconductor substrate 8, and a positional relationship provided on the semiconductor substrate 8 and rotated by 90 degrees. And a plurality of misalignment measurement marks 45 provided between the circuit patterns 7 on the semiconductor substrate 8. The alignment mark 5 is the same as the alignment mark described with reference to FIG. The misalignment measurement mark 45 is the same as the misalignment measurement mark 45 described with reference to FIG.

In the manufacture of the semiconductor device, the circuit pattern 7 is transferred onto the semiconductor substrate 8 by a photolithography method using the photomask shown in FIG. At this time, the alignment mark 5 and the misalignment measurement mark 45 are also transferred onto the semiconductor substrate 8. Next, another circuit pattern 7 is superimposed on the circuit pattern 7 on the semiconductor substrate 8 and transferred.
Also at this time, a photomask on which the pattern 7 of the other circuit, the alignment mark 5, and the misalignment measurement mark 45 are arranged is used. By optically aligning the alignment mark 5 on the semiconductor substrate 8 and the alignment mark 5 on the photomask with an alignment device equipped with a mark detection device, different circuit patterns 7 are placed on the semiconductor substrate 8. They can be overlapped in a predetermined positional relationship. Further, the misalignment of the superimposed misalignment measurement marks 45 is measured by the misalignment measurement device equipped with the mark detection device, so that the photolithography method can be corrected at the time of transfer.

By using the alignment mark 5 and the misalignment measurement mark 45, the same effect as in FIG. 6 can be obtained. In addition, the mark 3 and the mark 43 can be recognized by the mark detection device only in the first pattern 1 and 41, or only in the second pattern 2 and 42. 1 and the center lines of the second pattern 2 coincide with each other.
Since the center line of the total number of the patterns 41 and the center line of the total number of the second patterns 42 coincide with each other, if the position of the mark is detected using the center line, the net position is determined regardless of which is recognized. Can be measured.

(Other Embodiments) As described above, the embodiments of the present invention have been described. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. . From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

In the description of the embodiment described above,
Although the groove-shaped pattern has been described, it is also effective when the pattern is formed by recesses on the plug.

Thus, it should be understood that the present invention covers various embodiments not described herein. Accordingly, the present invention is limited only by the matters specifying the invention according to the claims that are reasonable from this disclosure.

[0058]

As described above, according to the present invention, a mark which can be recognized by a mark detector of an optical system is provided even if the interference condition of light changes due to a change in a manufacturing process of a semiconductor device or the like. it can.

According to the present invention, it is possible to provide an alignment mark that can be recognized by a mark detector of an optical system even if the manufacturing process of a semiconductor device or the like changes and the light interference condition changes.

According to the present invention, it is possible to provide a misalignment measurement mark recognizable by a mark detector of an optical system even when the light interference condition changes due to a change in a manufacturing process of a semiconductor device or the like.

According to the present invention, it is possible to provide a photomask that can be recognized by a mark detector of an optical system even if the manufacturing process of a semiconductor device or the like changes and the light interference condition changes.

Finally, according to the present invention, it is possible to provide a semiconductor wafer that can be recognized by a mark detector of an optical system even when the manufacturing process of a semiconductor device or the like changes and the light interference condition changes.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a mark according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an alignment mark according to the first embodiment of the present invention.

FIG. 3 is a top view of the photomask according to the first embodiment of the present invention.

FIG. 4 is a top view of the semiconductor wafer according to the first embodiment of the present invention.

FIG. 5 is a partial cross-sectional view of an alignment mark provided on a semiconductor substrate according to the first embodiment of the present invention.

FIG. 6 is a graph showing the relationship between the thickness of a silicon nitride film and the strength of a mark detection signal.

FIG. 7 shows that the mark detection signal strength of a mark having a first pattern and a second pattern is an intermediate value between the mark detection signal strengths of a mark having only a first pattern and a mark having only a second pattern. It is a figure explaining the reason.

FIG. 8 is a configuration diagram of a mark according to a first modification of the first embodiment of the present invention.

FIG. 9 is a configuration diagram of a mark according to a second modification of the first embodiment of the present invention.

FIG. 10 is a configuration diagram of an alignment mark according to a second modification of the first embodiment of the present invention.

FIG. 11 is a configuration diagram of a mark according to a second embodiment of the present invention.

FIG. 12 is a configuration diagram of a misalignment measurement mark according to Embodiment 2 of the present invention.

FIG. 13 is a top view of the photomask according to the second embodiment of the present invention.

FIG. 14 is a top view (part 1) of a semiconductor wafer according to a second embodiment of the present invention.

FIG. 15 is a top view (part 2) of the semiconductor wafer according to Embodiment 2 of the present invention.

FIG. 16 is a configuration diagram of a mark according to a modification of the second embodiment of the present invention.

FIG. 17 is a configuration diagram of a misalignment measurement mark 55 according to a modification of the second embodiment of the present invention.

FIG. 18 is a top view of a photomask according to Embodiment 3 of the present invention.

FIG. 19 is a top view of a semiconductor wafer according to Embodiment 3 of the present invention.

FIG. 20 is a configuration diagram of a conventional alignment mark.

FIG. 21 is a diagram for explaining the reason why a mark having a pattern cannot be recognized by an optical mark detector.

FIG. 22 is a graph showing a relationship between a pattern width and a pattern depth and a relationship between a pattern width and a mark detection signal intensity.

[Explanation of symbols]

 1, 21, 31, 41, 51 First pattern 2, 22, 32, 42, 52 Second pattern 3, 23, 33, 43, 53, 63 Mark 4 Mark area 5, 35, 65 Alignment mark 6 Glass Substrate 7 Circuit pattern 8 Semiconductor substrate 9 Silicon nitride film 10 Standing wave 11 Wavefront 45, 46, 55 Misalignment measurement mark 61 Pattern

Claims (14)

[Claims] A first pattern having a pair of parallel sides having a width equal to or less than the resolution of the mark detector, wherein a plurality of the first patterns are arranged so that the sides are opposed to each other; A rectangular shape having a pair of parallel sides having different widths from each other, wherein one side of the pair of sides is arranged at an interval equal to or less than the resolution of the one side of the pair of sides of the first pattern, A mark comprising a first pattern and a plurality of second patterns arranged alternately so as to be adjacent to each other. 2. The pair of sides of the first pattern,
The mark according to claim 1, wherein the mark is divided into a length equal to or less than the resolution and at intervals equal to or less than the resolution. 3. The pair of sides of the second pattern,
3. The image processing apparatus according to claim 1, wherein the image data is divided into a length equal to or less than the resolution at an interval equal to or less than the resolution.
Mark described in. 4. A first pattern which is a quadrangle having a pair of parallel sides having a width equal to or less than the resolution of the mark detector, wherein a plurality of first patterns are arranged so that the sides face each other. A quadrangle having a pair of parallel sides divided at a length equal to or less than the resolution and at intervals equal to or less than the resolution, wherein one side of the pair of sides is one of the pair of sides of the first pattern. A mark comprising: a plurality of second patterns arranged side by side with an interval equal to or less than the resolution and alternately arranged adjacent to the first pattern. 5. The method according to claim 1, wherein the length of both sides of the pair of sides of the first pattern is equal to the length of both sides of the pair of sides of the second pattern. The mark described in one. 6. The apparatus according to claim 1, wherein a center of the plurality of first patterns and a center of the plurality of second patterns coincide with each other. Mark described in. 7. An alignment mark, wherein a plurality of marks according to claim 1 are arranged in parallel at equal intervals. 8. A misalignment measurement mark, wherein four marks according to claim 1 are arranged along four sides of a square. 9. A photomask, comprising: a glass substrate; and two alignment marks according to claim 7, provided on the glass substrate and rotated by 90 degrees. 10. A photomask comprising: a glass substrate; and four misalignment measurement marks according to claim 8, provided on the glass substrate. 11. A glass substrate, two alignment marks provided on the glass substrate and rotated by 90 degrees, and four alignment marks provided on the glass substrate. A photomask comprising a misalignment measurement mark. 12. A semiconductor wafer, comprising: a semiconductor substrate; and a plurality of the alignment marks according to claim 7, provided on the semiconductor substrate and rotated by 90 degrees. 13. A semiconductor wafer, comprising: a semiconductor substrate; and four or more misalignment measuring marks according to claim 8 provided on the semiconductor substrate. 14. A semiconductor substrate, a plurality of alignment marks provided on the semiconductor substrate and rotated by 90 degrees, and four or more alignment marks provided on the semiconductor substrate. A semiconductor wafer comprising: a misalignment measurement mark according to the description.