JP2001091595A - LSI semiconductor inspection device and semiconductor device - Google Patents

Abstract

(57) Abstract: The frequency of a PLL circuit incorporated in a semiconductor chip can be efficiently increased without preparing a separate test program for each change in the type of the PLL circuit and the frequency value of a frequency output signal to be measured. An object of the present invention is to provide an inspection device capable of inspection. SOLUTION: At a timing of a first state in which a selector (14) outputs an input signal of a PLL circuit (2), a storage register (18) updates the storage, and the selector (14) outputs a P signal.
A frequency comparison circuit (17) compares the output signal of the PLL frequency measurement circuit (3) and the output signal of the storage register (18) at the timing of the second state in which the output signal of the LL circuit (2) is selected and output. And a frequency comparison circuit (17)
Let the comparison result be the inspection result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection apparatus for a semiconductor device having a PLL circuit.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication No. 11-23662 discloses that the frequency of a PLL circuit 2 built in a semiconductor chip 1 is counted by a PLL frequency measuring circuit 3 built in the same semiconductor chip 1 as shown in FIG. , PLL frequency measurement circuit 3
A technique for calculating a frequency by calculating an n-bit digital value output by an LSI tester 4 external to the semiconductor chip 1 is disclosed. 5 is a logic circuit and 6 is a result output.

Specifically, the logic circuit 5 outputs n [MH
z] is input to the PLL circuit 2 and i
The frequency output signal 7 to be measured multiplied (i is an integer) is n ·
By being output at the frequency of 2i [MHz] and input to the PLL frequency measuring circuit 3, the frequency of n · 2i [MHz] can be measured and output as a digital value of fbit.

For example, if it is 10 bits, (01010
A digital value like 10111) is output. LSI
The digital value is calculated by the tester 4 and the result is output as a measured frequency value 7. For example, X [S] = 8
If [S], (0101010111) /8=42.9
[MHz], and the result output 6 is 42.9 MHz.

The PLL frequency measurement circuit 3 is configured as shown in FIG. 9 is a variable control signal, 10 is a reset, and 11 is an f-bit counter. 5 are as shown in FIG. The PLL frequency measurement circuit 3 resets the counter 11 after setting the initial state of the signal of the reset 10 to the L level and latching it at the falling edge of the signal of the frequency signal 7 to be measured. The output 12 of the PLL frequency measurement circuit 3 is initially set to 0 in hexadecimal. The initial state of the variable control signal 9 is set to the H level, latched at the fall of the signal of the measured frequency signal 7, and then transmitted to the inside.

The variable control signal 9 changes from the H level to the L level from the state in which the reset 10 goes to the H level and is latched by the signal of the measured frequency signal 7, and changes to the state of being latched by the signal of the measured frequency signal 7. Period X until
[Second], the signal of the frequency signal under measurement 7 propagates inside, is counted up by the counter 11, and is output 12. The signal output from the output 12 is calculated by the frequency [Hz] = n bit count value / X [sec] to be measured by the LSI tester 4.

For example, when the number of bits of the counter 11 is 9 and X [seconds] is 12 [μs], the frequency is expressed by the following equation:
If there is a one-bit error in the count value obtained by (12 · 10 ⁻⁶ ), the error is ± 0.08 MHz.

[0008]

However, a plurality of P
When the LL circuit is built in, the conventional PLL frequency measurement circuit uses the type of the PLL circuit 2 and n · 2i [MH
z] by changing the frequency value of the measured frequency output signal
Since the measured frequency signal 7 changes, it is necessary to change the standard value for judging the result output 6 in the shipment inspection of the semiconductor chip 1. Therefore, the type of the PLL and the frequency of the measured frequency output signal of n · 2i [MHz] are required. A separate test program must be prepared for each change in value. In addition, the provision of the standard value increases the inspection time and the inspection cost.

The present invention has been made in view of such a problem, and
When the LL is built in, the type of PLL and n · 2i
The output result 7 resulting from the change in the frequency value of the output signal under measurement of [MHz] is determined to match or not match the standard within the semiconductor chip without having to set a standard to be determined, and a 1-bit output is performed. It is an object of the present invention to provide a hardware capable of measuring the frequency of a plurality of PLLs simply by monitoring the "H" and "L" level states of the terminals.

[0010]

According to a first aspect of the present invention, there is provided an LSI semiconductor inspection apparatus for inspecting a frequency of a PLL circuit built in a semiconductor chip, wherein the frequency of the PLL circuit is measured. A PLL frequency measurement circuit required for measurement, and a first state in which an output is connected to a measurement input of the PLL frequency measurement circuit to output an input signal of the PLL circuit, or a first state in which an output signal of the PLL circuit is selected and output. And a selector capable of switching to the state 2 and multiplying the output signal of the PLL frequency measuring circuit by 2i times (i is an integer)
2i multiplier, a C1 · 2i storage register for storing the output C1 (0 to n) of the 2i multiplier, and a C1 · 2i storage register that updates the storage when the selector is in the first state. At the timing of the second state, the output signal of the PLL frequency measurement circuit and the C1 · 2i
A frequency comparison circuit that compares the output signal of the storage register with the output signal of the storage register, and a comparison result of the frequency comparison circuit is used as an inspection result.

According to this configuration, the inspection can be performed only by determining the logic level of the output of the frequency comparison circuit. According to a second aspect of the present invention, in the semiconductor device, the semiconductor chip includes the PLL frequency measuring circuit, the selector, the 2i-times circuit,
Since the 1.2i storage register and the frequency comparison circuit are built in, inspection can be performed outside the semiconductor chip only by determining the logic level of the output of the frequency comparison circuit.

[0012]

FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIG. It is to be noted that components having the same functions as those in FIG. (First Embodiment) FIGS. 1 to 3 show a semiconductor device according to a (first embodiment) of the present invention.

As shown in FIGS. 1 and 2, the semiconductor device has a 2i-multiplier circuit 16 composed of a shift register and a frequency comparison circuit 17 for comparing the output frequency signal of the PLL circuit 2.
Is provided. Reference numeral 14 denotes a selector, 15 denotes a PLL test control circuit, and 18 denotes a C1x2i storage register built in the semiconductor chip 1. 19 is a comparison result. FIG. 3 shows a waveform diagram of each part.

First, the PL built in the semiconductor chip 1
A signal is input to the L circuit 2 at n [MHz] by an LSI tester. Next, the B port is selected by the selector 14, and the output C of the selector 14 is passed through the PLL frequency measuring circuit 3 to measure the frequency. The result is input to the 2i multiplying circuit 16, and the value of i is received from the PLL test control circuit 15 and multiplied by 2i, and stored in the C1 · 2i storage register 18, where the data is once held.

Next, n · 2 output from the PLL circuit 2
The selector 14 selects the A port of the frequency signal of i [MHz], passes the output C of the selector 14 to the PLL frequency measuring circuit 3, and measures the frequency. Then, the frequency comparison circuit 17 compares the measurement result with the data already stored in the C1 · 2i storage register 18.

If they match, the frequency comparison circuit 17
Outputs an H level as logical data as a result output 19, and conversely outputs an L level when they do not match. For example, when the input frequency is n [MHz], A is input to C1- (0 to n), and the data becomes 2A by the 2i multiplication circuit 16. This 2A is stored in the storage register 18. next,
The selector 14 switches the data of B (0 to n),
2A is output. This B (0 to n) and the storage register 1
When the output value of No. 8 is compared by the frequency comparing circuit 17, the "H" level is output as a result, and the judgment value is "H", which is coincident, so that it can be judged that the operating frequency of the PLL is correct.

In the above embodiment, the PLL frequency measuring circuit 3 and the selector 14
And a 2i multiplying circuit 16, a C1 · 2i storage register 18, a frequency comparing circuit 17, and a PLL test control circuit 15. However, this is a case where an inspection apparatus is configured to provide these outside the semiconductor chip for inspection. Even PL
There is no need to prepare a separate test program every time the type of L and the frequency value of the frequency output signal under measurement of n · 2i [MHz] are changed, and the test can be performed more efficiently than in the past.

[0018]

As described above, according to the LSI semiconductor inspection apparatus of the present invention, the selector C1 · 2
The i storage register updates the storage, and the selector compares the output signal of the PLL frequency measurement circuit and the output signal of the C1 · 2i storage register by the frequency comparison circuit at the timing of the second state, and checks the comparison result. To get the result,
The inspection can be performed only by determining the logic level of the output of the frequency comparison circuit.

Further, in the semiconductor device of the present invention, since the above-mentioned PLL frequency measuring circuit, selector, 2i multiplier, C1.2i storage register and frequency comparing circuit are built in the semiconductor chip, the type of PLL and n. It is also possible to set the standard to be determined by the tester for the output result due to the change of the frequency value of the frequency output signal under measurement of 2iMHz without changing the standard.
It is possible to realize a semiconductor device having an excellent effect that the frequency can be measured only by monitoring the “H” and “L” level states of the bit output terminal.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of an LSI semiconductor inspection apparatus according to the present invention;

FIG. 2 is a configuration diagram of a main part of the embodiment.

FIG. 3 is a waveform chart of a main part of the embodiment.

FIG. 4 is a configuration diagram of a conventional LSI semiconductor inspection apparatus.

FIG. 5 is a configuration diagram of a main part of the conventional example.

FIG. 6 is a waveform diagram of a main part of the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 PLL circuit 3 PLL frequency measurement circuit 5 Logic 14 Selector 15 PLL test control circuit 16 2i multiplier circuit 18 C1 / 2i storage register 17 Frequency comparison circuit 19 Result

Claims (2)

[Claims] 1. An LSI semiconductor inspection apparatus for inspecting the frequency of a PLL circuit built in a semiconductor chip, comprising: a PLL frequency measurement circuit required for measuring the frequency of the PLL circuit; and a measurement input of the PLL frequency measurement circuit. And a selector which is switched to a first state for outputting an input signal of the PLL circuit or a second state for selecting and outputting an output signal of the PLL circuit, and an output signal of the PLL frequency measurement circuit. 2i multiplying circuit for multiplying by 2i (i is an integer), and C1 · 2i for storing the output C1 (0 to n) of the 2i multiplying circuit
A storage register;
a frequency comparison circuit for comparing the output signal of the PLL frequency measurement circuit with the output signal of the C1 · 2i storage register at the timing of the second state, wherein the frequency comparison circuit is provided. An LSI semiconductor inspection device that uses a circuit comparison result as an inspection result. 2. A semiconductor device incorporating the circuit according to claim 1.