JP2001083942A - Scanning electrode driving ic for liquid crystal panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a scanning electrode driving IC for liquid crystal panel resistance to internal noise while utilizing the characteristic of an IC operated by an oscillating power source by converting a selection signal outputted from a circuit operated at low voltage by DC by a level shifter, and inputting the resulting signal to an output block. SOLUTION: The output signal group 111 of a control circuit 110 is inputted to a selection signal generating circuit 112, a selection signal 113 that is each output signal of the selection signal generating circuit 112 is inputted to each level shifter 114, and the output signal of each level shifter 114 is inputted to each output block 115. On the other hand, a signal DB 108 is inputted to a level shifter 117, the output of the level shifter 117 is inputted to a level shifter 118, and the output signal of the level shifter 118 is inputted to a total output block 115. The ground VM for driving a liquid crystal panel is inputted to the total output block 115, and each output block 115 outputs each scanning electrode drive signal 116.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit board, a scan electrode swing drive IC for a liquid crystal panel characterized by a circuit configuration utilizing the characteristics of the board and a power supply system.

[0002]

2. Description of the Related Art A passive type liquid crystal panel has a structure in which a signal electrode and a scanning electrode are formed on two transparent substrates opposed to each other with a liquid crystal layer interposed therebetween, and an intersection portion is defined as a pixel. Responds to the effective value to perform matrix display. In particular, a display method in which the effective value of each pixel in the liquid crystal panel in the non-selection period is equal and a difference in the effective value of each pixel appears only during the selection period is called a voltage averaging method. While various waveforms have been devised based on the voltage averaging method, a method of applying a low-voltage data signal waveform to the signal electrode and applying a high-voltage selection pulse to the scan electrode is also used in many products. I have.

FIG. 5 illustrates this method. (A)
FIG. 2 is a schematic diagram enlarging a part of a conventional example of a passive type liquid crystal panel, and FIG. 2 (B) is a driving waveform diagram thereof.
(A), the vertically long rectangular signal electrodes S1, S2, S
3 are arranged in the horizontal direction, and the rectangular scanning electrodes T which are long in the horizontal direction.
1, T2, T3 are arranged in the vertical direction. In addition, between the signal electrodes S1, S2, and S3 and the scanning electrodes T1, T2, and T3, an alignment film, an insulating layer, and the like are stacked in addition to the liquid crystal layer, but are not shown. The intersection of the signal electrodes S1, S2, S3 and the scanning electrodes T1, T2, T3 is a pixel. Of these, the pixels G22, G23 formed at the intersection of the signal electrodes S2, S3 and the scanning electrode T2 are shown by oblique lines. Is shown.
(B) shows the state around the selection pulse.
The drive waveform applied to the scan electrode T1 was initially at the ground level (hereinafter referred to as VM level) for driving the liquid layer panel because it was in the non-selection period. In this case, a selection pulse having a voltage greatly deviating from the VM level regardless of the sign is referred to as a high voltage), and returns to the VM level in the non-selection period. Similarly, the drive waveforms of the scan electrodes T2 and T3 also have positive and negative selection pulses in each selection period, and are at the VM level in other non-selection periods.
The drive waveform of the signal electrodes S2 and S3 is a binary (± VD) low voltage data signal waveform centered on the VM level.
For the sake of explanation, the waveforms of the signal electrodes S2 and S3 have opposite polarities, and the polarities are switched every selection period. Pixels G22, G2
The driving waveform of the scanning electrode T2 and the driving waveform of the scanning electrode T2 and the signal electrode S
2 and S3. Pixel G22,
Comparing the driving waveform of G23, it can be seen that the polarities are reversed in the non-selection period, but the absolute values | ± VD | are constant values. Therefore, the effective values applied to the pixels G22 and G23 during the non-selection period become equal. On the other hand, in the selection period, the pixel G22 has a high peak value (VT + V
While the pulse of D) is applied, a pulse having a low peak value (VT-VD) is applied to the pixel G23, and thus the effective value of the pixel G22 is larger than that of the pixel G23 during this period. In other words, the difference in the transmittance between the pixels G22 and G23 is created by using the difference in the effective value only during the selection period.

The above-described method of applying a low-voltage, constant-amplitude data signal waveform to a signal electrode and applying a high-voltage selection pulse to a scanning electrode at the time of selection is a method for driving a signal electrode (hereinafter referred to as a signal). (Referred to as an electrode driving IC) can be reduced in voltage, which is advantageous for miniaturization and low power consumption of the signal electrode driving IC. However, a circuit for driving the scan electrodes (hereinafter, referred to as a scan electrode drive IC) outputs a positive / negative high-voltage pulse, so that an ordinary circuit requires a power supply having a voltage of + VT or more and a voltage of -VT or less. Even in a method of generating a selection pulse by switching a C-MOS analog switch as a case of minimizing the power supply, a voltage difference (2 VT) between the power supplies is applied to the scan electrode drive IC, which is remarkable for the scan electrode drive IC. A high breakdown voltage structure is required. This high withstand voltage structure causes an increase in IC size, and further increase in size causes various cost increases. Therefore, we have developed a swing power supply that can obtain a desired waveform with half the withstand voltage and adopted it in various products. .

Referring to FIG. 6, a swing power supply will be described. (A)
FIG. 3 is a waveform diagram of the oscillating power supply, and FIG. 3B is a circuit diagram for creating the oscillating power supply. In (A), the upper swing power supply VDD has a maximum value of voltage + VT and a minimum value of voltage + VDD.
Is a square wave that switches as
Is a square wave that switches between the highest value as the voltage -VD and the lowest value as the voltage -VT, and includes upper and lower swing power supplies VDD and VSS.
Are synchronized. This switching is called swinging. The scanning electrode driving IC includes upper and lower swing power supplies VDD, V
SS and the voltage VM are supplied as power supplies. Although not shown, a start signal FLM (FIRST) indicating the start of selection is provided.
The scan electrode driving IC is controlled by a line marker (LINE MARKER), a signal LP (LATCH PULSE) indicating switching of a selection period, a signal DB indicating a polarity of liquid crystal panel driving such as a selection pulse, and the like. In the swing power supply system, the polarity of the selection pulse is given by inversion of the logical value of the VM level during the selection period.
For example, an output circuit for applying a drive waveform to the scan electrode T1 connects the lower swing power supply VSS and the output terminal during the selection period of the scan electrode T1, and connects to the VM level during the non-selection period. Is obtained. In this case, the VM level is at the high level during the selection period. Similarly, a circuit for outputting a drive waveform to the scan electrode T2 may connect the output terminal to the upper swing power supply VDD during the selection period of the scan electrode T2 (the VM level in the selection period is low). In this manner, positive and negative high voltage selection pulses can be output. However, the voltage (VDD-VSS =
Since only VT + 2VD) is applied, the use of an oscillating power supply makes it possible to reduce the IC withstand voltage to almost half the selection pulse amplitude.

Some of our products are shown in FIG.
The circuit shown in (B) is assembled on a printed circuit board to create the above-mentioned swing power supply waveforms VDD and VSS. Resistance R1, R
2. The signal DB is input to the capacitors C1 and C2, and the other ends of the resistor R1 and the capacitor C1, and the other ends of the resistor R2 and the capacitor C2 are connected to the base of the PNP transistor Q1 and the base of the NPN transistor Q2, respectively. I have. The emitters of the PNP transistor Q1 and the NPN transistor Q2 are high voltage HV and 0, respectively.
V (circuit ground), the collector is common. One ends of the capacitors C3 and C4 are connected to the collectors of the transistors Q1 and Q2, and the other ends are connected to the anode of the diode D1 and the cathode of the diode D2, respectively. The cathode of the diode D1 and the anode of the diode D2 are at voltages + VD and -VD, respectively.

The resistors R1 and R2 and the capacitors C1 and C2
And the transistors Q1 and Q2 are inverted level shifters, which convert the high level voltage of the signal DB to 0V and the low level voltage to the voltage HV. Since the level-shifted signal is clamped to the minimum voltage + VDD by the capacitor C3 and the diode D1, the clamped signal becomes the upper power supply VDD of the swing power supply. Similarly, the level-shifted signal is supplied to the capacitor C4 and the diode D2.
, The maximum voltage is clamped to the voltage −VD, and the clamped signal becomes the lower power supply VSS of the swing power supply. (The voltage drop in the transistors Q1 and Q2 and the diodes D1 and D2 was ignored. The same applies hereinafter.)

FIG. 7 shows a block diagram of a scan electrode drive IC designed by our company as an example of operating with a swing power supply system (A).
And a power supply system (B). 3A, an IC chip 700 made of a silicon substrate has an upper swing power supply VDD701, a lower swing power supply VSS702, an upper swing power supply VCC703 for low-voltage logic, an upper low-voltage DC power supply VDL704 as power supplies. Lower low-voltage DC power supply VS
L705, a ground VM706 for driving the liquid crystal panel is input. As the main control signals, a start signal FLM707 indicating the start of selection, a signal LP708 indicating switching of the selection period, and a signal DB indicating the polarity of the selection pulse are input to the IC chip 700. The start signal FML 707 and the signal LP 708 are converted by the level shifter 710 into low-voltage logic that operates in the voltage range between the swing power supply VCC 702 and the swing power supply VSS 703, and then the low-level logic operates with the swing power supply VCC 702 and VSS 703. It is input to the control circuit 711 of the voltage logic circuit. Control circuit 712
Is a selection signal generation circuit 713, which is also a low-voltage logic circuit, based on the signal FLM707, the lock signal LP708, and various operation mode setting inputs (not shown).
The control signal group 712 is output to the control circuit 712. This control signal group 712
And the selection signal generation circuit 713 outputs the selection signal 714 at a predetermined timing. The level shifter 715 converts the selection signal 714, which is a low-voltage logic signal, into the voltage of the upper swing power supply VDD 701 and the lower swing power supply VSS 702, and converts this signal by the upper swing power supply VDD 701 and the lower swing power supply VSS 702. Output to the operating output block 716. On the other hand, the signal DB 709 is once converted into low-voltage logic by the level shifter 718, and is then changed by the level shifter 719 to the swing power supply VDD 701 and the swing power supply VS.
The voltage is converted to the voltage of S702 and input to all output blocks 716. The ground VM 706 for driving the liquid crystal panel is also input to the entire output block 716. The scan electrode drive output 717 of the output block 716 is used for the period during which the selection signal 714 is not input (non-selection period).
706, and when the signal DB 709 is at a high level during a period in which the selection pulse 714 is input (selection period), it is connected to the lower swing power supply VSS 702, and the signal DB 709 in the selection period.
When 709 is at a low level, the upper swing power supply VDD7
Connect with 01.

Referring to FIG. 7B, the power supply relation of FIG. The lower side of the upper swing power supply VDD 701 is the voltage V
The voltage VSL 705 is at the top of the DL 704 and the lower swing power supply VSS 702. Voltage VDL704, VSL
Reference numeral 705 denotes a voltage equivalent to the voltages + VD and -VD in FIG. 6, which is the upper and lower voltages of the data signal waveform applied to the signal electrode. A ground VM706 for driving the liquid crystal panel is provided between the voltage VDL704 and the voltage VSL705. Oscillating power supply VCC70
3 has a voltage VDL 704 at the top and a voltage (V
CC-VSS) is equal to the voltage (VDL-VSL), and the control circuit 711 and the selection signal generation circuit 713 of FIG. In the drawing, a gap is provided for explanation, but actually, the swing power supply VDD is used.
701, VCC 703 and VSS 702 are synchronized,
There is no gap related to the voltages VDL704 and VSL705.

FIG. 8 shows the level shifters 710 and 7 of FIG.
15 is a circuit diagram of an output block 716. Until now, we have made various contrivances to pass signals from the normal fixed power supply system to the swing power supply system. The level shifter of FIG. 8A is characteristic of the level shifter 710 used for the first input of FIG. 7A. P-channel transistor 801 and N-channel transistor 80
2, 803 and P-channel transistor 804
And N-channel transistors 805 and 806 are respectively arranged in series. Transistors 801, 80
4 and the source of the transistor 801 and the gates of the transistors 802 and 805 are connected to the power supply VDL7.
04. Transistors 802, 80
3, 804, 805 and the sources of transistors 803, 806 are connected to the lower swing power supply VSS 702.
Connected to. The gate of the transistor 801 and the source of the transistor 804 are connected to the input terminal IN813, and the gate of the transistor 804 is connected to the power supply VSL70.
5 is connected. The gate of the transistor 806 is connected to the drains of the transistors 801 and 802, and the inverted output is input to the gate of the transistor 808. Similarly, the gate of the transistor 803 is connected to the drains of the transistors 804 and 805, and is output as a non-inverting input to the gate of the transistor 810. Note that the source of the transistor 802 is connected to the drain of the transistor 803, and the source of the transistor 805 is connected to the drain of the transistor 806.
The common drain of the P-channel transistor 807 and the N-channel transistor 808 is connected to the gate of the P-channel transistor 809, and the common drain of the P-channel transistor 809 and the N-channel transistor 810 is connected to the P-channel transistors 807 and 8
11 and the gate of the N-channel transistor 812. Transistors 807, 809, 81
1 is connected to the swing power supply VCC 703, and the sources and substrates of the transistors 808, 810, 812 are connected to the swing power supply VSS 702. The common drain of the transistors 811 and 812 becomes the output terminal OUT814.

The level shifter shown in FIG. 8A has a two-stage configuration. Transistors 801, 802, 803,
The first-stage level shifter composed of 804, 805, and 806 is a high-level and low-level power supply VDL 704,
The input signal which is the voltage of the VSL 705 is converted into the voltage of the power supply VDL at a high level and the voltage of the swing power supply VSS 702 at a low level. The reason for adopting a circuit different from a normal level shifter as shown in the transistor 804 is that the lower power supply is the swing power supply VSS702 and
This is because an inverted signal of the signal input to the input terminal IN813 could not be created due to the restriction of the C process rule.
The next-stage level shifter including the transistors 807, 808, 809, and 810 has a high-level power supply VD.
L704, a signal whose low level is the voltage of the swing power supply VSS702 is converted into a voltage of the high level of the swing power supply VCC703 and a low level is the voltage of the swing power supply VSS702. The transistors 811 and 812 are inverters for signal inversion and waveform shaping.

FIG. 8B is a circuit diagram of the level shifter 715 of FIG. 7A. The P-channel transistors 821 and 822 and the N-channel transistor 823 are arranged in series. Similarly, P-channel transistors 824 and 825 and N-channel transistor 82
6 are also arranged in series. The signal 714 indicating the selection timing is supplied to the normal input terminal IN (the transistors 821 and 8
23 gate). Generally, an inverted signal is also input to a level shifter as a signal pair and used.
Although omitted in FIG. 7, in an actual circuit, an inverted signal 828 of the selection signal 714 indicating the selection timing is also supplied to the inverted input terminal I.
NB (gates of transistors 824 and 826). The common drain of the transistors 822 and 823 is connected to the gate of the transistor 825, and the common drain of the transistors 825 and 826 is connected to the transistor 82.
The output OUT827 is connected to the second gate. The upper and lower power supplies are swing power supplies VDD701 and VSS702, and transistors 821, 822, 824,
825 substrate and transistors 821 and 82
4 and the substrate and the source of the transistors 823 and 826 are connected. The level shifter converts the selection signal 714 whose high level is the voltage of the swing power supply VCC 703 and whose low level is the voltage of the swing power supply VSS 702 into the voltage of the swing power supply VDD 701 and the low level swing power supply VSS 702.

FIG. 8C shows the output block 7 shown in FIG.
FIG. 16 is a circuit diagram of FIG. In the non-selection period, since the signal 827 (the output OUT 827 of (B)) indicating the selection timing is at a low level, the P-channel transistor 834 and the N-channel transistor 8 by ANDs 831 and 833.
36 is non-conductive. On the other hand, at this time, the signal 827
The transmission gate 835 is turned on by itself and the inverter 832, and the voltage of the ground VM 706 of the liquid crystal panel appears at the output terminal 717. A signal 837 indicating the polarity of the selection pulse during the selection period (the signal DB7 in FIG.
09 is low level, the output of the AND 831 becomes low level, the transistor 834 is turned on, and the swing power supply VDD7 is connected to the output terminal 717.
A voltage of 01 appears. Similarly, when the signal 837 is at the high level during the selection period, the transistor 836 is turned on and the voltage of the swing power supply VSS 702 appears at the output terminal 717.
Note that the transmission gate 835 is off during the selection period.

[0014]

As shown in FIG. 6 (B), since the swing power supply VSS is generated via a capacitor, it is used as the ground of the scan electrode drive IC (when the silicon wafer is a P substrate). It will be weak. On the other hand, in order to prevent display quality deterioration (such as crosstalk), the resistance of the ground VM for driving the liquid crystal panel must be as low as possible from the voltage source outside the IC chip to the scanning electrode of the liquid crystal panel via the IC chip. is there. For this reason, in the IC chip, the wiring is thickened and the area of the transmission gate 835 in FIG. 8C is increased. As a result of this countermeasure, the ground (V
SS) and a large capacitive coupling between the ground VM for driving the liquid crystal panel. When viewed from the ground (VSS) of the scan electrode drive IC, the ground VM for driving the liquid crystal panel fluctuates with a large amplitude, so that a large noise is added to the ground (VSS) of the scan electrode drive IC due to capacitive coupling. There is a problem that a logic circuit operating at a low voltage (such as the selection signal generation circuit 713) malfunctions due to the noise. Accordingly, a first object of the present invention is to provide an IC which operates on a swing power supply and is effective for miniaturization.
Another object of the present invention is to provide a scan electrode driving IC for a liquid crystal panel that is resistant to internal noise while making the most of the above characteristics.

As shown in FIG. 6B, there is a problem that it is necessary to mount a large number of components including a relatively large-capacity capacitor on a circuit board in order to create an oscillating power supply. . Accordingly, a second object of the present invention is to provide a scan electrode driving IC for a liquid crystal panel in which components relating to the oscillating power supply are reduced while utilizing the characteristics of an IC that operates with the oscillating power supply that requires a low withstand voltage. .

The method of driving a liquid crystal panel with a high selection pulse and a low-voltage data signal requires a high-voltage power supply and a power supply for data voltage for generating the selection pulse. Even if an oscillating power supply is used, the situation is the same, so that there is a problem that a large number of power supplies are required to drive the scanning electrodes of the liquid crystal panel. Accordingly, a third object of the present invention is to provide a scanning electrode driving IC for a liquid crystal panel in which components necessary for driving the scanning electrodes of the liquid crystal panel are minimized.

[0017]

In order to achieve the first object, the present invention forms a circuit operating at a low DC voltage, a level shifter, and an output block on an insulator, and swings the output block. The circuit is operated by a dynamic power supply, and a selection signal output by a circuit operating at a low voltage with direct current is converted into a logic value of an oscillating power supply system by a level shifter, and this signal is input to an output block.

In order to achieve the above-mentioned second object, the present invention provides, in addition to the above-described structure, an upper swing power supply circuit and a lower swing power supply circuit for creating a swing power supply on an insulator substrate. The upper and lower power supply voltages of the upper swing power supply circuit are a high voltage near the maximum value of the selection pulse and a low voltage near the ground level of the liquid crystal panel drive, respectively. Each is characterized by a low voltage near the ground level for driving the liquid crystal panel and a high voltage near the lowest value of the selection pulse.

In order to achieve the third object, the present invention has an oscillator, a switching transistor, a diode, and voltage detecting means on an insulator substrate in addition to the above-mentioned structure.
A booster circuit is formed by connecting a coil and a capacitor.

[0020]

FIG. 1 shows a block diagram (A) and a waveform diagram (B) of a power supply according to a first embodiment of the present invention. In FIG. 1A, an IC chip 100 is an integrated circuit in which an insulating layer is formed on a silicon substrate, a plurality of P or N type silicon regions are formed thereon, and elements are formed in this region. Technology (SILICON ON IN
SULATOR, hereinafter referred to as SOI). As the power supply, an IC chip 100 includes an upper low-voltage DC power supply VDL101, a lower low-voltage DC power supply VSL102, an upper swing power supply VDD103, a lower swing power supply VSS104, and a liquid crystal panel driving ground VM105. input. As the main control signals, a start signal FLM106 indicating selection start, a signal LP107 indicating switching of a selection period and shifting a scanning electrode to be selected, a selection pulse and a signal DB108 indicating the polarity of liquid crystal panel driving are input to the IC chip 100. I do. The signal FML106 and the signal LP107 are input to the level shifter 109, and the output signal of the level shifter 109 is input to the control circuit 110,
An output signal group 111 of the control circuit 110 is input to a selection signal generation circuit 112, and a selection signal 113, which is an output signal of each of the selection signal generation circuits, is output to a respective level shifter 114.
, And the output signal of each level shifter 114 is input to each output block 115. On the other hand, signal D
B108 is input to the level shifter 117, the output signal of the level shifter 117 is input to the level shifter 118, and the output signal of the level shifter 118 is input to all the output blocks 115. The ground VM for driving the liquid crystal panel is input to all output blocks 115, and each output block 115 outputs a scan electrode drive signal 116, respectively.

FIG. 1B is a waveform diagram for explaining the power supply relation of FIG. 1A. Upper swing power supply VDD103
Are lower than the power supply VDL101 and the upper voltage of the lower swing power supply VSS104, respectively.
It is equal to the voltage of 02. The power supply VDL101 and the power supply VS
The voltage of L102 is equal to the high-level and low-level voltages of the data signal waveform for driving the signal electrodes, respectively. The voltage of the ground VM105 for driving the liquid crystal panel is intermediate between the voltages of the power supply VDL101 and the power supply VSL102.
The swing widths (the difference between the highest value and the lowest value) of the upper and lower swing power supplies VDD103 and VSS104 are equal. In the figure, the voltage of the power supply VDL101 and the swing power supply VDD103 are shown for explanation.
Between the power supply VSL102 and the swing power supply VSS.
A gap was provided between the upper portions of 104.

In FIG. 1A, a signal FLM 106 and a signal LP 107 input with the voltage width of the external system (the voltage difference between the high level and the low level) are high level by the level shifter 109 and the voltage of the power source VDL 101 is low. The level is converted to the voltage of the power supply VSL102. Power supply VD
Control circuit 111 operated by L101 and power supply VSL102
Is a signal obtained by converting the voltage of the signal FLM106 and the signal LP107, and various operation mode setting inputs (not shown).
The control signal group 112 is created based on After all power supply V
The selection signal generation circuit 112 operated by the DL 101 and the power supply VSL 102 outputs a selection signal 113 at a predetermined timing based on the control signal group 112. The level shifter 114 has a power supply VD
Low voltage selection signal 1 which is the voltage of L101 and power supply VSL
13 is converted into a voltage of the upper swing power supply VDD 103 and a lower swing power supply VSS 104 of low level, respectively. Similarly, the signal DB 108 input with the voltage width of the external system has a high level and a low level at the power supply VDL 101 and the power supply VS by the level shifter 117, respectively.
Is converted to the voltage of L102, and furthermore the level shifter 11
At 8, the high level and the low level are converted into voltages of the upper swing power supply VDD 103 and the lower swing power supply VSS 104, respectively. The output block 115 operated by the upper swing power supply VDD 103 and the lower swing power supply VSS 104 conducts with the liquid crystal panel driving ground VM 105 during the non-selection period in which the selection signal 113 is at the low level, and outputs this voltage. I do. The output block 115 in the selection period in which the selection signal 113 is at the high level conducts and outputs the lower swing power supply VSS 104 when the signal DB 108 is at the high level and outputs this voltage when the signal DB 108 is at the low level. The oscillation power supply VDD 103 is made conductive and outputs this voltage.

FIG. 2 shows the level shifters 109 and 117 (A) and the level shifter 11 of the first embodiment shown in FIG.
4 is a circuit diagram of FIG. In FIG. 2, power supplies equivalent to those in FIG. 1 are indicated by the same numbers. (A) shows a P-channel transistor 201 and an N-channel transistor 20.
2, and the P-channel transistor 203 and the N-channel transistor 204 are connected such that their drains are common. Transistors 201, 2
The substrate 03 and the source are connected to the power supply VDL101. The substrates and sources of the transistors 202 and 204 are connected to the power supply VSL102. The gate of the transistor 202 is an input terminal IN of the level shifter, and the gate of the transistor 204 receives the reference voltage Vref. Transistors 201, 203
Is connected to the drains of the transistors 203 and 204. The common drain of the transistors 201 and 202 is connected to the input terminal of the inverter 205, and the output of the inverter 205 becomes the output of the entire level shifter.

In FIG. 2A, a transistor 20
The circuit formed by 1, 202, 203, and 204 is the simplest comparator that compares the voltage of the input terminal IN with the reference voltage Vref. When the voltage of the input terminal IN is higher than the reference voltage Vref, the transistor 201,
The drain of 202 goes low. Conversely, when the voltage at the input terminal IN is lower than the reference voltage Vref, the drains of the transistors 201 and 202 go to a high level. The inverter 205 also performs waveform shaping while inverting the output signal of the comparator.

The level shifter shown in FIG. 2B has a two-stage configuration. In the first-stage level shifter, a P-channel transistor 211, N-channel transistors 212 and 212, and a P-channel transistor 2
14 and N-channel transistors 215 and 216 are arranged in series, respectively.
4 and the drain of the transistor 215, the source of the transistor 212 and the drain of the transistor 213, and the source of the transistor 215 and the transistor 2
16 drains are connected to each other. The substrates of the transistors 211, 212, 213, 214, 215, and 216 are connected to their own sources. The sources of the transistors 211 and 214 and the sources of the transistors 213 and 216 are connected to the power supply VDL101 and the lower swing power supply VSS104, respectively. Connected to In both the entire level shifter and the first-stage level shifter, the gates of the transistors 211 and 213 are the input terminals IN of the level shifters, and the transistors 214 and 21
The gate 6 is an inverting input terminal INB. The gate of the transistor 215 is connected to the drains of the transistors 211 and 212. Similarly, the gate of the transistor 212 is connected to the drains of the transistors 214 and 215. Also in the next level shifter, P-channel transistors 217 and 218, N-channel transistor 219, and P-channel transistor 22
0, 221 and an N-channel transistor 222 are respectively arranged in series, the drain of the transistor 217 and the source of the transistor 218, the drain of the transistor 220 and the source of the transistor 221;
The drains of the transistors 218 and 219, and the transistors 221 and 22
2 are connected to each other. The substrates of transistors 217, 218, 219, 220, 221 and 222 are connected to their sources, and the sources of transistors 217 and 220 and transistor 2
19 and 222 are the upper and lower swing power supply VDD, respectively.
103 and VSS 104. The gates of the transistors 217 and 219 are the positive input terminals of the next-stage level shifter, and are connected to the positive output (the drain of the transistor 214 and the like) of the first-stage level shifter. The gates of the transistors 220 and 222 are inverting input terminals of the next-stage level shifter, and are connected to the inverted output of the first-stage level shifter (the drain of the transistor 211, etc.). The gate of the transistor 221 is connected to the drains of the transistors 218 and 219, and serves as an inverted output OUTB of the entire level shifter. Similarly, the gate of the transistor 218 is connected to the drains of the transistors 221 and 222, and the positive output OUT of the entire level shifter is connected.
Becomes

In FIG. 2B, a selection signal 113 (or a signal obtained by voltage-converting the signal DB by the level shifter 117) input to the input terminal IN and an inversion signal (level shifter in the IC is input to the inversion input terminal INB) In general, an inverted signal is also used, so that it is not shown in FIG. 1 for the sake of simplicity of description). In the first-stage level shifter, the high level is converted into the voltage of the power supply VDL101, and the low level is converted into the voltage of the swing power supply VSS104. Next, in the next stage of the level shifter, the high level is the voltage of the oscillating power supply VDD103,
The low level is converted to the voltage of the swing power supply VSS104.

In the first embodiment, a low-voltage operating circuit area (level shifters 109, 11) is provided on an SOI substrate.
7, a control circuit 110, a selection signal generation circuit 112) and a circuit region (output block 115) operating at a high voltage are formed independently. Signals are transmitted between these two areas by level shifters 114 and 118. For more information,
In FIG. 2B, the P-type or N-type silicon region is divided at the transistor level as well, such that the substrate such as the transistor 212 is connected to its own source. Although this embodiment is an SOI, an example in which glass or sapphire is used as an insulator is known as a technique for forming an integrated circuit by independently forming a silicon region on an insulator.

FIG. 3 is a block diagram of a second embodiment of the present invention. 1 and 3, equivalent power supplies, circuit blocks, and signals are indicated by the same numbers. This embodiment is different from the first embodiment shown in FIG.
07 and VSS 308 are generated inside the IC chip 100. The upper and lower low-voltage and direct-current power supplies VDL101 and VSL102 and the ground VM105 for driving the liquid crystal panel are connected to each other in the same manner as in the first embodiment of FIG.
It is input from outside the C chip 100. On the other hand, a positive high voltage HV305 and a negative high voltage LV306 are input instead of the upper and lower swing power supplies VDD103 and VSS104. The upper and lower swing power supplies VDD 307 and VSS 308 generated inside the IC chip 100 are connected to the level shifter 1.
14, 118 and the output block 115. The signal DB 108 is converted into a low-voltage logic by the level shifter 117, and the logic-inverted signal is further inverted by the inverter 309.
SL, and the high level is the voltage of the high-voltage power supply HV305 on the positive side, and the low level is the power supply VDL101.
And the upper swing power supply VDD 307 is obtained. Similarly, the output signal of the inverter 309 is once converted to a voltage of the power supply VDL101 by a level shifter 303, a low level is converted to a voltage of the high-voltage power supply LV306 on the negative side, and a high level is further converted to a voltage of the power supply VSL102 by a level shifter 303.
The low level is converted into the voltage of the high voltage power supply LV306 on the negative side, and the lower swing power supply VSS308 is obtained.

FIG. 4 is a block diagram of a third embodiment of the present invention. 3 and 4, equivalent power supplies, circuit blocks, and signals are indicated by the same numbers. This embodiment is different from the second embodiment shown in FIG.
417 and the ground VM421 for driving the liquid crystal panel are generated inside the IC chip 100, and the IC chip 100
Outer coil 402 and capacitors 403, 404, 405
And a device inside the IC chip to constitute a switching regulator to generate positive and negative high voltages HV419 and LV420. The power supplied to the IC chip 100 is a positive / negative voltage of the battery 401, and a lower low-voltage power supply VSL41.
Reference numeral 8 is connected to the negative electrode (system ground) of the battery.
The power supply VDL 417 inside the IC chip 100 and the ground VM 421 for driving the liquid crystal panel are connected to a constant voltage generation circuit Vreg.
In step 406, the positive electrode voltage of the battery 401 is increased or decreased to create the voltage. The back electromotive force generated when the switching transistor 410 cuts off the current of the coil 402 by the output signal of the oscillator OSC 409 is output to the diodes 407 and 40.
8 and a capacitor 403 to obtain a positive high-voltage power supply HV419 inside the IC chip 100. Similarly I
The negative high-voltage power supply LV inside the C chip 100 is obtained by rectifying the back electromotive force of the coil 402 with the diode 416 and the capacitor 405.

In the third embodiment, in order to equalize the voltages of the high-voltage power supplies HV and LV with respect to the ground level VM of the liquid crystal panel, a two-stage diode is used when the positive high-voltage power supply HV419 is created, and a negative diode is used. Side high-voltage power supply LV
In creating 420, the top level of the back electromotive force waveform is clamped to the voltage of the power supply VDL. Back electromotive force is Va
(V), the voltage drop Vd (V) of the diode, and the voltage of the ground level VM for driving the liquid crystal panel are Vm (V), the voltage of the high voltage power supply HV419 on the positive side becomes Va-2Vd, The potential difference between the voltage of the high voltage power supply HV419 and the ground level VM421 for driving the liquid crystal panel is Va−2Vd−Vm, while the voltage of the negative high voltage power supply LV420 is clamped to the power supply VDL417 and the power supply VDL417. Is -Va + 2Vd + 2Vm, and the potential difference between the voltage of the negative high-voltage power supply LV420 and the ground level VM421 for driving the liquid crystal panel is-(Va-2Vd-Vm). Therefore, the upper and lower high-voltage power supplies HV419 and LV4
Reference numeral 20 has a voltage value symmetrical to the voltage of the ground level VM421 of the liquid crystal panel.

The booster circuit using the coil 402
1, the electronic volume 412, the controller 414 of the electronic volume, and the comparator 413 perform stabilization and output voltage control. A voltage obtained by dividing the voltage of the high voltage power supply HV 419 on the positive side by the resistor 411 and the electronic volume 412 is input to the inverting input terminal of the comparator 413. The reference voltage Vref is input to the non-inverting input of the comparator 413. When the divided voltage is higher than the reference voltage Vref, the comparator 413 outputs a low level signal to the control terminal of the oscillator OSC 409, and based on this signal, the oscillator OSC 409 also changes the output signal to the switching transistor 410 to low level. . As a result, switching boosting stops. Conversely, the divided voltage is the reference voltage V
If it is lower than ref, the comparator 413 outputs a high-level signal to the oscillator OSC 409, and based on this signal, the oscillator OSC 409 continues to output a pulse train to the switching transistor 410. As a result, switching boosting continues. By this feedback control, the upper high-voltage power supply HV is stabilized. In driving the scanning electrodes of the liquid crystal panel, upper and lower high-voltage power supplies HV419 and LV
Since the power consumption of the low-voltage power supply 420 is almost the same, the lower high-voltage power supply LV420 is also stable. The controller 414 of the electronic volume 412 includes the IC chip 10
The electronic volume is controlled on the basis of adjustment items such as panel brightness information, temperature correction data, and variations in the resistance 411 and the reference voltage Vref, which are given from outside, and the positive and negative high voltages HV419 and LV420 are varied.

[0032]

As is clear from the first embodiment,
The scan electrode driving IC according to the present invention is composed of a circuit that operates with a low DC voltage and a circuit that operates with a high-voltage swing power supply. The size of the scan electrode driving IC is greatly affected by the withstand voltage of elements operating at a high voltage, such as a level shifter and an output block. Since the breakdown voltage is almost proportional to the dimensional rule such as the gate width, if the breakdown voltage is doubled, the IC chip area is quadrupled. The scan electrode driving IC of the present invention maintains the characteristics of the oscillating power supply, which is effective for downsizing the scan electrode driving IC, because the high breakdown voltage section operates with the oscillating power supply. In addition, since the SOI structure is used, the low-voltage region can be operated with a DC voltage, and the exchange between the low-voltage region and the oscillating power supply is limited to a portion via a level shifter. In addition, the capacitive coupling between the power supplies on the low voltage logic circuit side and the output block side is greatly reduced as compared with the scan electrode driving IC having the conventional structure. As a result, the scanning electrode driving IC of the liquid crystal panel of the present invention is an IC that operates with a swing power supply of “small size”.
The effect of becoming strong against internal noise while maintaining the characteristic of is obtained.

As is clear from the second embodiment, if the swing power supply is built in the scan electrode driving IC, components mounted on the IC chip can be eliminated only by applying a high positive / negative voltage.
In addition, the level shifter for creating the oscillating power supply creates an oscillating power supply for only one side (either the upper or lower oscillating power supply), so that a voltage equivalent to that of an output block or the like operated by the oscillating power supply is generated. Will only be applied. As a result, the level shifter for generating the oscillating power supply can have the same withstand voltage as that of the output block, so that the characteristics of the IC operated by the oscillating power supply, which requires only a low withstand voltage when the oscillating power supply circuit is incorporated, can be maintained. In other words, in the scan electrode driving IC of the present invention, the design rules are for low-voltage logic and oscillating power supply / output block /
Two types for the level shifter are good. As a result, the scan electrode driving IC for a liquid crystal panel according to the present invention has the effect of reducing the number of components while making use of the characteristics of an IC that operates with an oscillating power supply that requires a low withstand voltage.

As is apparent from the third embodiment, a positive and negative high voltage can be easily obtained by forming a switching regulator using a coil mounted outside the IC, several capacitors, and elements in the scan electrode driving IC. . As a result, the scan electrode driving IC of the liquid crystal panel according to the present invention has an effect that components necessary for driving the scan electrode can be minimized.

[Brief description of the drawings]

FIG. 1 is a block diagram (A) and a waveform diagram of a power supply (B) according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a level shifter according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a block diagram of a third embodiment of the present invention.

5A and 5B are a schematic diagram and a waveform diagram of a conventional liquid crystal panel.

6A and 6B are a waveform diagram (A) and a circuit diagram (B) of a conventional swing power supply.

FIG. 7A is a block diagram of a conventional example and FIG. 7B is a waveform diagram of a power supply.

FIG. 8 is a circuit diagram of a conventional level shifter and an output block.

[Explanation of symbols]

100 IC chips 101, 417 made on SOI substrate, DC low voltage power supplies 102, 418 on the upper side of VDL, DC low voltage power supplies 103, 307 on the lower side of VSL, swing power supplies 104, 308 on the upper side of VDD, VSS lower side of VSS Dynamic power supply 105, 421, VM liquid crystal panel driving ground 106, FLM start signal 107, LP signal to shift the scanning electrode to be selected 108, DB signal indicating driving polarity of liquid crystal panel 109, 117 level shifter 110 control circuit 112 Selection signal generation circuit 113 Selection signal 114, 118 Level shifter 115 Output block 301, 302, 303, 304 Level shifter 305, 419, HV positive high voltage power supply 306, 420, LV negative high voltage power supply 401 Battery 402 coil 403, 404, 405 Condensers 406 Vreg controller of the constant voltage generating circuit 407,408,415,416 diode 409, OSC an oscillator 410 switching transistor 411 resistor 412 electronic volume 413 comparator 414 electronic volume

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 622 G09G 3/20 622A F term (Reference) 2H093 NA07 NB09 NB13 NC03 NC05 NC09 NC21 ND38 ND40 ND42 ND49 5C006 AF64 BC03 BF14 BF32 BF36 BF37 BF46 BF49 EB05 FA31 FA46 5C080 AA10 BB05 DD09 DD12 DD25 JJ02 JJ03 JJ04

Claims (3)

[Claims] 1. A low-voltage data signal waveform is applied to a signal electrode of a liquid crystal panel centering on a ground level for driving a liquid crystal, and a high-voltage positive or negative selection pulse is applied to a scanning electrode at the time of selection. In a scan electrode driving IC of a liquid crystal panel used in a driving method, a circuit operating at a low DC voltage, a level shifter, and an output block are provided on an insulator, and a power supply of the output block is a swing power supply. A selection signal output from a circuit operating at a low voltage with direct current is input to the level shifter, and a signal obtained by the level shifter converting the selection signal into a logic value of a swing power supply system is input to the output block. Scanning electrode driving IC of a liquid crystal panel. 2. An upper swing power supply circuit and a lower swing power supply circuit for forming the swing power supply are formed on the insulator substrate, and upper and lower power supply voltages of the upper swing power supply circuit are respectively The high voltage near the maximum value of the selection pulse and the low voltage near the ground level of the liquid crystal panel drive.The upper and lower power supply voltages of the lower swing power supply circuit are the low voltage near the ground level of the liquid crystal panel drive, respectively. 2. The scanning electrode driving IC for a liquid crystal panel according to claim 1, wherein the high voltage is near a minimum value of the selection pulse. 3. The liquid crystal panel according to claim 2, wherein said insulator substrate has an oscillator, a switching transistor, a diode, and voltage detecting means, and a coil and a capacitor are connected to form a booster circuit. Scan electrode drive IC.