JP2001075522A - Gain control circuit and display device using the circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gain control circuit and a display device that no malfunction is caused even in the case of a high speed clock without increasing the cost and electric power consumption. SOLUTION: In a display device 100, γ compensation look up tables of R, G and B are stored in a RAM, which is capable of writing and reading in synchronism with a 40 HMz master clock MCLK, to make the tables reloadable. Moreover, a gain control circuit 104 is provided to rewrite the data of the tables based on the addresses and gain data by a microcomputer 107.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gain control circuit for controlling a gain of a video signal and a display device using the same.

[0002]

2. Description of the Related Art In a display device using a plasma display panel or a liquid crystal display, for example, after an R, G, B primary color signal is restored from an input video signal, an analog signal is converted into a digital signal. Since the input signal and the number of pixels in the vertical and horizontal directions of the display device may be different, a so-called scan conversion process for adjusting and converting the input signal is performed, and if necessary, contrast, bright, white balance, and gamma (γ) adjustment. After that, the panel is driven by the driver circuit to display an image corresponding to the input video signal.

In the above-described series of processing, a gain control circuit for performing gamma correction includes, as shown in FIG. 8, a ROM 1, 2, or 3 storing a gamma lookup table for an image.
3 on the output side of these ROMs 1, 2, 3
For example, multipliers 4, 5, and 6 operating in real time with a master clock MCLK having a frequency of 30 MHz are arranged. The receiver 7 shown in FIG. 8 receives the gain control serial data DAT supplied from a microcomputer (not shown), converts it into parallel data, and converts it into 8-bit R, G, B digital gain data R-.
gain, G-gain, and B-gain are generated, and each multiplier 4,
5 and 6, respectively.

In the gain control circuit having such a configuration, an input digital R signal R-in and a digital G signal G-i by a scan converter (not shown) at the preceding stage are used.
n and the ROM 1 to the digital B signal B-in.
3 correction data S1 to S3 are read. This ROM
8-bit digital gain data R-gain, G-gain, and B-gain supplied from the microcomputer and generated by the receiver 7 and adjusted to a resolution of 0 to 255, for example, are output from the microcomputer. Each multiplier 4,
5 and 6, respectively. And each multiplier 4,
5 and 6, the correction data S1 to S3 and the digital gain data R are synchronized with the master clock (30 MHz).
-Gain, G-gain, and B-gain are multiplied to obtain a digital R signal R-out, a digital G signal G-out, and a digital B signal B-out whose gains are controlled.

[0005]

However, in the above-described gain control circuit, when the resolution is increased and the frequency of the master clock is further increased, for example, to 40 MHz, the operating speeds of the multipliers 4 to 6 cannot keep up with the error and the error occurs. There was a disadvantage that would occur.

In order to solve this problem, it is conceivable to use a higher-speed multiplier, but this disadvantageously increases the cost and power consumption.

The present invention has been made in view of the above circumstances, and has as its object to provide a gain control circuit and a gain control circuit which do not cause an increase in cost and power consumption and which do not cause a malfunction even with a high-speed clock. It is to provide a display device using the same.

[0008]

In order to achieve the above object, a gain control circuit according to the present invention stores gain data weighted with correction data according to an address and receives a write enable signal in an active state. Write the gain data to be stored based on the supplied address data and gain data weighted by the correction data, and when the write enable signal is inactively received, the input of the stored gain data Storage means for outputting gain data in accordance with the address signal to be received, and when receiving the gain data weighted by the address data and the correction data, actively outputs a write enable signal to the storage means, and outputs the received address data and The gain data is supplied to the storage means, and the When not receiving the gain data weighted with less data and correction data,
Supply means for inactively outputting the write enable signal to the storage means and supplying a predetermined digital video signal as the address signal to the storage means;

According to another aspect of the present invention, there is provided a display device for displaying an image corresponding to an input video signal on a predetermined display unit, wherein gain data weighted with correction data according to an address is stored, and a write enable signal is stored. Is active, the gain data to be stored is written based on the supplied address data and gain data weighted by the correction data, and when the write enable signal is received inactive, the stored gain data is stored. Storage means for outputting, to the display unit, gain data corresponding to an input address signal among the gain data being input, and generating the gain data weighted by the address data and the correction data upon receiving the gain data write command And the address data and correction data generated by the control means. When the gain data weighted by the above is received, a write enable signal is activated and output to the storage means, the received address data and gain data are supplied to the storage means, and the gain data weighted by the address data and the correction data are supplied. Supply means for inactively outputting the write enable signal to the storage means when not receiving the write enable signal and supplying a predetermined digital video signal as the address signal to the storage means.

According to the present invention, the storage means writes and reads the gain data in synchronization with a master clock signal having a predetermined frequency.

The gain control circuit of the present invention stores gain value data weighted with correction data in accordance with an address, and supplies the address data and correction data to be supplied when the write enable signal is actively received. When the gain data to be stored is written based on the gain value data weighted by the above, and when the write enable signal is inactively received, the gain data corresponding to the input address signal among the stored gain data. Receiving means for receiving the unweighted gain data, actively outputting a write enable signal to the storage means, and outputting a trigger signal at a predetermined timing received;
Address generation means for receiving the trigger signal and generating the address data, correction data generation means for generating weighting correction data based on the address data by the address generation means, and correction data generated by the correction data generation means Gain value data generating means for weighting the gain data received by the receiving means and supplying the weight data to the storing means; and when the write enable signal is active, the address data generated by the address generating means is stored in the storing means. And a supply unit for supplying a predetermined digital video signal as the address signal to the storage unit when the write enable signal is inactive.

According to another aspect of the present invention, there is provided a display device for displaying an image corresponding to an input video signal on a predetermined display unit, wherein gain value data weighted with correction data in accordance with an address is stored, and write enable is performed. When the signal is received in an active state, the gain data to be stored is written based on the supplied address data and gain value data weighted by the correction data, and when the write enable signal is received in an inactive state, Storage means for outputting, to the display unit, gain data corresponding to an input address signal among the stored gain data; and receiving the gain data write command, generating gain data not weighted by the correction data. Receiving the gain data not weighted by the control means, Receiving means for outputting a write enable signal to the storage means in an active manner and outputting a trigger signal at a predetermined timing received; address generating means for receiving the trigger signal and generating the address data; Correction data generating means for generating weighting correction data based on address data; and a gain value to be supplied to the storage means by weighting the gain data received by the receiving means with the correction data generated by the correction data generating means. When the write enable signal is active, the data generation means supplies the address data generated by the address generation means to the storage means, and when the write enable signal is inactive, a predetermined digital video signal is supplied to the storage means. Supply means for supplying an address signal to the storage means. That.

According to the present invention, the receiving means outputs the trigger signal in synchronization with a vertical retrace signal of the video signal.

In the present invention, the storage means writes and reads the gain data in synchronization with a master clock signal of a predetermined frequency, divides the frequency of the master clock, and outputs the address generation means and the correction data generation data. Means, and a frequency dividing circuit for supplying at least the gain value data generating means among the gain value data generating means as an operation clock.

Further, in the present invention, the correction data generating means includes a first multiplier for calculating a power of the address data generated by the address generating means, and the gain value data generating means includes a first multiplier for calculating the correction data generating means. A second multiplier for multiplying the correction data generated by the means and the gain data is provided, and an operation clock by the frequency dividing circuit is supplied to at least the first and second multipliers.

In the present invention, the storage means includes three storage circuits provided corresponding to the three primary color signals R (red), G (green), and B (blue), respectively. The address data is converted into three primary color signals R (red), G (green),
B (blue) is supplied to a storage circuit corresponding to each of the three primary color signals R (red), G (green), B
(Blue), and the supply means includes the three primary color signals R
(Red), G (green), and B (blue) are supplied to the corresponding storage circuits.

According to the present invention, when gain data weighted by the address data and the correction data is input to the supply means, the write enable signal is activated and output to the storage means, and the received address data and gain data are stored in the storage means. It is supplied to the storage means. At this time, the storage means writes gain data to be stored based on the supplied address data and gain data weighted by the correction data. On the other hand, when the supply means does not receive the gain data weighted by the address data and the correction data, the write enable signal is output to the storage means in an inactive state. As a result, the storage means is write-protected. Then, a predetermined digital video signal is supplied to the storage means as an address signal. Thereby, the gain data corresponding to the input address signal among the stored gain data is output.

Further, according to the present invention, when unweighted gain data is input to the receiving means, a write enable signal is activated and output to the storage means, and for example, in synchronization with a vertical retrace signal. A trigger signal is output to the address generation means. In the address generation means, address data is generated, correction data is generated by the correction data generation means based on the address data, and supplied to the gain value data generation means. In the gain value data generating means, the gain data received by the receiving means with the correction data is weighted and supplied to the storage means as gain value data. At this time, the supply means supplies the address data from the address generation means to the storage means, and the storage means writes gain value data to be stored based on the supplied address data and gain value data weighted by the correction data. It is. On the other hand, when the write enable signal is inactive, the storage means is prohibited from writing. Then, a predetermined digital video signal is supplied to the storage means as an address signal. Thereby, the gain data corresponding to the input address signal among the stored gain value data is output.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment FIG . 1 is a block diagram showing a first embodiment of a display device using a gain control circuit according to the present invention.

As shown in FIG. 1, the display device 100 includes a video signal supply device 101, a color decoder 102,
Scan converter 103, gain control circuit 1
04, a driver 105, a plasma display panel (PDP) 106, and a microcomputer 107 as a control circuit.

Upon receiving, for example, an external start signal, the video signal supply device 101 receives the analog video signal S101 to be displayed on the plasma display panel 106.
Is supplied to the color decoder 102.

The color decoder 102 receives a video signal S101 from the video signal supply device 100 which is a composite color signal.
, And demodulates the three primary color signals of R, G, and B, and supplies them to the scan converter 103 as a signal S102.

The scan converter 103 includes, for example, an analog / digital (A / A /
D) A / D-converts the demodulated input signal S102, that is, the R, G, B signals, including a converter and a line buffer, and writes the R, G, B digital signals to the line buffer with a predetermined clock. Then, the written data is read out in synchronization with a clock having a frequency different from the frequency of the write clock, and the plasma display panel 1 is read.
A video signal S 103 corresponding to the number of vertical and horizontal pixels 06 is generated and supplied to the gain control circuit 104.

The gain control circuit 104 includes, for example, a gamma correction circuit having a RAM, inputs a control signal S107 from the microcomputer 107 to, for example, a high level, and outputs R, G, B addresses and corresponding correction data. When receiving the serial data D107 which is gain data weighted by
Is rewritten based on the input address and the gain data. Also, the control signal S1
07 is received at a low level, the digital R, G, and B signals S103 by the scan converter 103 are subjected to γ correction and gain control to perform signal S1
04a (-R, -G, -B) is supplied to the driver 105. In this case, the plasma display panel 106 is driven by the driver 105 to display an image.

FIG. 2 is a circuit diagram showing a configuration example of the gain control circuit 104 according to the first embodiment. As shown in FIG. 2, the gain control circuit 104 includes a RAM 1041 for digital R signal (S103-R), a RAM 1042 for digital G signal (S103-G), a RAM 1043 for digital B signal (S103-B), a receiver 1044, And switch circuits 1045, 104
6,1047.

The RAM 1041 can store a gamma look-up table for an image and has a data input terminal Tdat.
a is connected to the gain data output terminal of the receiver 1044, and the address input terminal Tadr is connected to the switch circuit 1045.
The write (write) enable terminal Twe is connected to the output line of the R signal write enable signal R-we of the receiver 1044, and the clock terminal clk is connected to the master clock MCL having a frequency of 40 MHz.
It is connected to the K supply line. And RAM10
Reference numeral 41 denotes an active input of the write enable signal Rwe by the receiver 1044, input of address data by the receiver 1044 to the address input terminal Tadr via the switch circuit 1045, and input of gain data according to the input address to the data input terminal Tdata. Then
Write gain data according to the supplied address,
In other words, the gamma lookup table is newly written or rewritten. Also, the RAM 1041 receives the write enable signal R-we from the receiver 1044 in an inactive state, and receives the digital R signal S103 from the scan converter 103 via the switch circuit 1045.
-R is input to the address input terminal Tadr, and the data corresponding to the address is input to the driver 1 as a signal S104-R.
Output to 05. That is, in this case, the RAM 104
1 performs gamma correction and gain control based on the stored lookup table.

The RAM 1042 can store a gamma look-up table for an image and has a data input terminal Tdat.
a is connected to the gain data output terminal of the receiver 1044, and the address input terminal Tadr is connected to the switch circuit 1046.
Of the write enable terminal Twe
Is the write enable signal G for the G signal of the receiver 1044
−we output line, and a clock terminal clk is connected to a supply line of a master clock MCLK having a frequency of 40 MHz. Then, the RAM 1042 actively inputs the write enable signal G-we from the receiver 1044, inputs address data from the receiver 1044 to the address input terminal Tadr via the switch circuit 1046, and inputs gain data according to the input address. When input to the terminal Tdata, gain data corresponding to the supplied address is written, in other words, a gamma lookup table is newly written or rewritten. In addition, the RAM 1042 includes the receiver 104
4, the write enable signal G-we is inactively input, the digital R signal S103-G from the scan converter 103 is input to the address input terminal Tadr via the switch circuit 1046, and data corresponding to the address is input to the signal S104- G is output to the driver 105. That is, at this time, the RAM 1042 performs gamma correction and gain control based on the stored look-up table.

The RAM 1043 can store a gamma look-up table for an image and has a data input terminal Tdat.
a is connected to the gain data output terminal of the receiver 1044, and the address input terminal Tadr is connected to the switch circuit 1047.
Of the write enable terminal Twe
Is the write enable signal B for the B signal of the receiver 1044
−we output line, and a clock terminal clk is connected to a supply line of a master clock MCLK having a frequency of 40 MHz. The RAM 1043 receives the write enable signal B-we from the receiver 1044 as active, inputs address data from the receiver 1044 to the address input terminal Tadr via the switch circuit 1047, and inputs gain data corresponding to the input address. When input to the terminal Tdata, gain data corresponding to the supplied address is written, in other words, a gamma lookup table is newly written or rewritten. Further, the RAM 1043 stores the receiver 104
4, the write enable signal B-we is inactively input, the digital R signal S103-B from the scan converter 103 is input to the address input terminal Tadr via the switch circuit 1047, and the data corresponding to the address is input to the signal S104- B is output to the driver 105. That is, at this time, the gamma correction and the gain control are performed based on the RAM 1043 and the stored look-up table.

Note that an RA for generating a normal image signal is used.
The look-up table data stored in M is, for example, as shown in FIG.

The receiver 1044 receives the control signal S107 from the microcomputer 107 at a high level,
When the R, G, and B addresses and the corresponding serial data D107 as gain data are sequentially received, the look-up table data in the RAM is rewritten based on the input address and the gain data. , G, and B in this order.
-We, G-we, B-we are stored in RAM 1041, 104
2, 1043, and the address data is directly transferred to the RAM 104 via the switch circuits 1045 to 1047.
1, 1042, and 1043.

The switch circuit 1045 has an input terminal a connected to an address data output line of the receiver 1044, an input terminal b connected to a digital R signal S 103 -R input line from the scan converter 103, and an output terminal c connected thereto. The RAM 1041 is connected to an address input terminal Tadr. When the write enable signal R-we from the receiver 1044 is active, the switch circuit 1045 connects the output terminal c to the input terminal a, and stores the address data of the receiver 1044 in the RAM 104.
1, when the write enable signal R-we is inactive, the output terminal c is connected to the input terminal b,
Digital R signal S10 by scan converter 103
3-R is input to the RAM 1041.

The switch circuit 1046 has an input terminal a connected to an address data output line of the receiver 1044, an input terminal b connected to a digital G signal S 103 -G input line from the scan converter 103, and an output terminal c connected to the output terminal c. The RAM 1042 is connected to an address input terminal Tadr. When the write enable signal G-we from the receiver 1044 is active, the switch circuit 1046 connects the output terminal c to the input terminal a, and stores the address data of the receiver 1044 in the RAM 104.
2 and the output terminal c is connected to the input terminal b when the write enable signal G-we is inactive,
Digital G signal S10 by scan converter 103
3-G is input to the RAM 1042.

The switch circuit 1047 has an input terminal a connected to an address data output line of the receiver 1044, an input terminal b connected to a digital B signal S 103 -B input line of the scan converter 103, and an output terminal c. The RAM 1043 is connected to an address input terminal Tadr. When the write enable signal B-we from the receiver 1044 is active, the switch circuit 1047 connects the output terminal c to the input terminal a, and stores the address data of the receiver 1044 in the RAM 104.
3, when the write enable signal B-we is inactive, the output terminal c is connected to the input terminal b,
Digital B signal S10 by scan converter 103
3-B is input to the RAM 1043.

When the microcomputer 107 receives, for example, a gain data rewrite command CMD, the microcomputer 107 outputs a control signal S107 to the gain control circuit 104, for example, at a high level, and specifies a designated R, G, B address and γ. A weighting process or the like is performed with the correction data to generate gain data corresponding to the weighting data, and output as serial data D107.
4 is rewritten.

Next, the operation of the above configuration will be described.

For example, a gain data rewrite command CMD
Is issued, the microcomputer 107 sends a control signal S107 to the gain control circuit 104.
Is output at a high level, and the designated R, G, B addresses and the corresponding gain data are output as serial data D107.

In the gain control circuit 104, addresses for R, G, and B and gain data are sequentially input to the receiver 1044. Receiver 1044
Then, the R, G, B line enable signals R-we, G
-We, B-we are sequentially generated as active, and RAM
It is supplied to 1041, 1042, 1043. The address data is output to each input terminal a of the switch circuits 1045 to 1047, and the gain data corresponding to the address data is output directly to the RAMs 1041, 1042, and 1043.

First, in the switch circuit 1045 that has actively received the line enable signal R-we, the output terminal c is held in a state of connection with the input terminal a. Thus, in the RAM 1041 that has actively received the line enable signal R-we, the address data from the receiver 1044 is input to the address input terminal Tadr via the switch circuit 1045, and the gain data corresponding to the input address is input to the data input terminal Tdata. Input and gain data according to the supplied address are written,
The gamma lookup table is newly written or rewritten.

Next, in the switch circuit 1046 that has actively received the line enable signal G-we, the output terminal c is held in a connected state with the input terminal a. Thus, in the RAM 1042 that has actively received the line enable signal G-we, the address data from the receiver 1044 is input to the address input terminal Tadr via the switch circuit 1046, and the gain data corresponding to the input address is input to the data input terminal Tdata. Input and gain data according to the supplied address are written,
The gamma lookup table is newly written or rewritten.

Next, in the switch circuit 1047 that has actively received the line enable signal B-we, the output terminal c is held in a connected state with the input terminal a. As a result, in the RAM 1043 that has actively received the line enable signal B-we, the address data from the receiver 1044 is input to the address input terminal Tadr via the switch circuit 1047, and the gain data corresponding to the input address is input to the data input terminal Tdata. Input and gain data according to the supplied address are written,
The gamma lookup table is newly written or rewritten.

As described above, the RAMs 1041-10
The gamma correction lookup table data 43 is rewritten.

When a normal image display is performed in such a state, the analog video signal S
The supply of the image data 101 to the color decoder 102 is started.
The color decoder 102 demodulates three primary color signals of R, G, and B from the video signal S101 which is a composite color signal.
Scan converter 1 as R, G, B signals S102
03.

In the scan converter 103, the analog R, G, and B signals by the color decoder 102 are A / D converted, and the converted digital R, G, and B signals are written to a line buffer at a predetermined clock.
Then, in the scan converter 103, the written data is read out in synchronization with a clock having a frequency different from the frequency of the writing clock, and a digital signal R, which is a video signal corresponding to the number of vertical and horizontal pixels of the plasma display panel 106, is read. G and B signals S103-R, S103-
G and S103-B are generated and supplied to the gain control circuit 104.

In the gain control circuit 104, at this time, the write enable signals R-we, G-we, B-we
We are inactive and the switch circuits 1045 to 1045
1047, the switch circuit 10
Each of the output terminals c of 45 to 1047 is held in a connected state with the input terminal b side. Therefore, in the RAM 1041 of the gain control circuit 104, the write enable signal R-we from the receiver 1044 is inactively input, and the digital R signal S103-R from the scan converter 103 is input to the address input terminal Tadr via the switch circuit 1045. , Data corresponding to the address is output to the driver 105 as a signal S104-R. That is, at this time, the RAM 1041 performs gamma correction and gain control based on the stored look-up table. Similarly, RAM 1042
Now, the write enable signal G by the receiver 1044
-We is input inactive and the switch circuit 104
6, digital G by the scan converter 103
The signal S103-G is input to the address input terminal Tadr, and data corresponding to the address is output to the driver 105 as a signal S104-G. And the RAM 104
3, the write enable signal B-we from the receiver 1044 is input inactive and the switch circuit 10
47, a digital B signal S103-B from the scan converter 103 is input to an address input terminal Tadr, and data corresponding to the address is input to a signal S104-B.
To the driver 105.

Thus, the gain control circuit 1
04 output signals S104-R, S104-G,
S104-B is supplied to the driver 105, which drives the plasma display panel 106 to display an image corresponding to the input video signal.

As described above, according to the first embodiment, the RAMs 1041 to 1043 in which the R, G, and B gamma correction look-up tables can be written and read in synchronization with the 40 MHz master clock MCLK. And the gain control circuit 104 that rewrites the data of the look-up table based on the address and gain data from the microcomputer 107. Therefore, the gain control circuit 104 can be operated at high speed without increasing the cost and power consumption. There is an advantage that a display device in which a malfunction does not occur even with a clock can be realized.

Second Embodiment FIG. 4 is a block diagram showing a second embodiment of the display device using the plasma display panel according to the present invention.

The difference of the second embodiment from the first embodiment is that the gain control circuit receives only the gain serial data without receiving the address data from the microcomputer 107a and converts the received data into the received data. The master clock MCLK is divided by 4 based on 10
In addition to generating address data for γ correction using a multiplier in synchronization with the MHz clock, and generating gain value data based on the data for γ correction, the look-up table data of the RAM is rewritten. It is in. Other configurations are the same as those of the first embodiment.

FIG. 5 is a circuit diagram showing a configuration example of the gain control circuit 108 according to the second embodiment. As shown in FIG. 5, the gain control circuit 108 includes a RAM 1081 for digital R signal (S103-R), a RAM 1082 for digital G signal (S103-G), a RAM 1083 for digital B signal (S103-B), a receiver 1084, , A 1/4 frequency dividing circuit 1085, a counter 1086 as an address generating means, a first multiplier 1087 as a γ correction data generating means, a second multiplier 1088 as a gain value data generating means, and a switch circuit 1089. 1090 and 1091.

The RAM 1081 can store a gamma look-up table for an image and has a data input terminal Tdat.
a is the gain value data signal S10 of the second multiplier 1088
88, which are connected to the address input terminal Tad.
r is connected to the output terminal c of the switch circuit 1089, the write enable terminal Twe is connected to the output line of the R signal write enable signal R-we of the receiver 1084, and the clock terminal clk is connected to the supply line of the master clock MCLK having a frequency of 40 MHz. It is connected to the. Then, the RAM 1081 actively receives the write enable signal Rwe from the receiver 1084, inputs the address signal S1086, which is the output signal of the counter 1086, as address data to the address input terminal Tadr via the switch circuit 1089, and responds to the input address. When the gain data is input to the data input terminal Tdata, the gain data corresponding to the supplied address is written, in other words, the gamma lookup table is newly written or rewritten. Also, the RAM 1081
The write enable signal Rwe from the receiver 1084 is input inactive, and the digital R signal S10 from the scan converter 103 is input via the switch circuit 1089.
3-R is input to the address input terminal Tadr, and data corresponding to the address is output to the driver 105 as a signal S108-R. That is, in this case, the RAM 10
81 is γ based on the stored lookup table
Performs correction and gain control.

The RAM 1082 can store a gamma look-up table for an image, and has a data input terminal Tdat.
a is the gain value data signal S10 of the second multiplier 1088
88, which are connected to the address input terminal Tad.
r is connected to the output terminal c of the switch circuit 1090, the write enable terminal Twe is connected to the output line of the receiver 1084 for the G signal write enable signal G-we, and the clock terminal clk is connected to the supply line of the master clock MCLK having a frequency of 40 MHz. It is connected to the. Then, the RAM 1082 actively inputs the write enable signal Rwe from the receiver 1084, inputs the address signal S1086, which is the output signal of the counter 1086, as address data to the address input terminal Tadr via the switch circuit 1090, and responds to the input address. When the gain data is input to the data input terminal Tdata, the gain data corresponding to the supplied address is written, in other words, the gamma lookup table is newly written or rewritten. Also, the RAM 1082
Write enable signal G-we by receiver 1084
Is input inactive, and the digital R signal S1 by the scan converter 103 via the switch circuit 1090 is input.
03-G is input to the address input terminal Tadr, and data corresponding to the address is output to the driver 105 as a signal S108-G. That is, in this case, the RAM 1
082 performs gamma correction and gain control based on the stored lookup table.

The RAM 1083 can store a gamma look-up table for an image and has a data input terminal Tdat.
a is the gain value data signal S10 of the second multiplier 1088
88, which are connected to the address input terminal Tad.
r is connected to the output terminal c of the switch circuit 1091, the write enable terminal Twe is connected to the output line of the receiver 1084 for the B signal write enable signal B-we, and the clock terminal clk is connected to the supply line of the master clock MCLK having a frequency of 40 MHz. It is connected to the. Then, the RAM 1083 actively inputs the write enable signal B-we from the receiver 1084, inputs the address signal which is the output signal of the counter 1086 as address data to the address input terminal Tadr via the switch circuit 1091, and inputs the address. When the corresponding gain data is input to the data input terminal Tdata, the gain data corresponding to the supplied address is written, in other words, the gamma lookup table is newly written or rewritten. Also, the RAM 1083 stores the receiver 1
084, the write enable signal B-we is inactively input, the digital R signal S103-B from the scan converter 103 is input to the address input terminal Tadr via the switch circuit 1091, and data corresponding to the address is input to the signal S108- B is output to the driver 105. That is, at this time, the RAM 1083
Gamma correction and gain control are performed based on the stored lookup table.

It should be noted that RA for generating a normal image signal is used.
The look-up table data stored in M is, for example, as shown in FIG.

When the receiver 1084 receives the control signal S107a from the microcomputer 107 at a high level and sequentially receives the serial data D107a as gain data for R, G, and B, the lookup table data of the RAM is read. In order to rewrite based on the gain data, for example, write enable signals R-we, G-we, and B-we are stored in the RAM 108 in the order of R, G, and B.
1, 1082, and 1083, respectively.
The trigger signal tgr is output to the counter 1086, and the input gain data is output to the second multiplier 1088.

FIG. 6 is a circuit diagram showing a configuration example of a main part of the receiver 1084. As shown in FIG. 5, the receiver 1084 receives the R, G, B serial data of 8 bits each and shifts it by 1 bit.
And a latch 2002 for holding the R, G, B data held in the shift register 2001 and outputting the held data to the second multiplier 1088, and a control bit indicating the input of the R, G, B serial data. When the control bit register 2003 and the control bits of R, G, and B are set and the vertical blanking signal VBLK of the video signal is received, a trigger signal trg which is a pulse signal is output to the counter 1086. A generation circuit 2004 is provided.

The frequency dividing circuit 1085 divides the frequency of the master clock MCLK having a frequency of 40 MHz by １ ／ to obtain a frequency of 10 MHz.
MHz clock signal DCLK to generate the counter 1
086, the first multiplier 1087, and the second multiplier 1
088 as an operation clock.

When receiving the trigger signal trg, the counter 1086 counts from 0 to 255 corresponding to the 8-bit resolution, and uses each count value as an address signal S1086 as a first multiplier 1087 and a switch circuit 108.
9 to 1091.

The first multiplier 1087 includes a counter 108
6 by squaring the address signal S1086 with γ (=
2) Correction data is generated, and a second signal is generated as a signal S1087.
Is output to the multiplier 1088.

The second multiplier 1088 is connected to the first multiplier 1
087 and the receiver 1
The data is multiplied by the gain data according to the data No. 084 to generate gain value data corresponding to the actual address, and output to the RAMs 1081 to 1083 as a signal S1088.

The first multiplier 1087 and the second multiplier 1088 operate in real time with a clock signal having a frequency of 30 MHz or less. FIG.
Shows a timing chart showing the relationship among the trigger signal trg, the address signal S1086 of the counter 1086, and the gain value data signal S1088.

The switch circuit 1089 has an input terminal a connected to the output line of the address signal S1086 of the counter 1086, an input terminal b connected to the input line of the digital R signal S103-R from the scan converter 103, and an output terminal c. Is the address input terminal T of the RAM 1081
connected to adr. Then, the switch circuit 108
9 is a write enable signal R by the receiver 1084
When -we is active, output terminal c is connected to input terminal a
To the address signal S108 of the counter 1086.
6 is input to the RAM 1081, and when the write enable signal R-we is inactive, the output terminal c is connected to the input terminal b, and the digital R signal S103-R from the scan converter 103 is input to the RAM 1081.

The switch circuit 1090 has an input terminal a connected to the output line of the address signal S1086 of the counter 1086, an input terminal b connected to the input line of the digital G signal S103-G from the scan converter 103, and an output terminal c. Is the address input terminal T of the RAM 1082
connected to adr. Then, the switch circuit 109
0 is the write enable signal G by the receiver 1084
When -we is active, output terminal c is connected to input terminal a
To the address signal S108 of the counter 1086.
6 is input to the RAM 1082, and when the write enable signal G-we is inactive, the output terminal c is connected to the input terminal b, and the digital G signal S103-G from the scan converter 103 is input to the RAM 1082.

The switch circuit 1091 has an input terminal a connected to the output line of the address signal S1086 of the counter 1086, an input terminal b connected to the input line of the digital B signal S103-B from the scan converter 103, and an output terminal c. Is the address input terminal T of the RAM 1083
connected to adr. Then, the switch circuit 109
1 is a write enable signal B by the receiver 1084
When -we is active, output terminal c is connected to input terminal a
To the address signal S108 of the counter 1086.
6 is input to the RAM 1083, and when the write enable signal B-we is inactive, the output terminal c is connected to the input terminal b, and the digital B signal S103-B from the scan converter 103 is input to the RAM 1083.

Next, the operation of the above configuration will be described.

For example, gain data rewrite command CMD
Is issued, the microcomputer 107 sends a control signal S107 to the gain control circuit 108.
Is output at a high level, and the specified R, G, B gain data is output as serial data D107a.

In the gain control circuit 108, the gain data for R, G, and B are sequentially transmitted to the receiver 10.
84 is input. In the receiver 1084, R, G, B
Line enable signals R-we, G-we, B-we
Are sequentially generated as active, and the RAMs 1081 and 108
2,1083. Further, the gain data is latched by the latch 2002 to be made to the second multiplier 1088, and the trigger signal trg corresponding to each of R, G, and B is generated in synchronization with the vertical retrace signal VBLK, and the counter 1
086.

In the frequency dividing circuit 1085, the master clock MCLK having a frequency of 40 MHz is frequency-divided by ク ロ ッ ク to generate a clock signal DCLK having a frequency of 10 MHz, and the counter 1086, the first multiplier 1087, and the second The signal is supplied to the multiplier 1088 as an operation clock.

In the counter 1086, the trigger signal trg
Then, counting from 0 to 255 is performed corresponding to the 8-bit resolution, and each count value is stored in the address signal S1.
086 is output to the first multiplier 1087 and the switch circuits 1089 to 1091.

In the first multiplier 1087, the counter 10
The address signal S1086 of the signal 86 is squared, and γ
(= 2) Correction data is generated and output to the second multiplier 1088 as a signal S1087. Second multiplier 10
At 88, the γ-correction data signal S1087 from the first multiplier 1087 is multiplied by the gain data from the receiver 1084 to generate gain value data weighted according to the actual address, and the RAMs 1081 to 1083 are used as the signal S1088. Is output to

Then, in the switch circuit 1089 that has actively received the line enable signal R-we, the output terminal c is kept in a connected state with the input terminal a. As a result, in the RAM 1081 that has actively received the line enable signal R-we, the address signal S1086 from the counter 1086 is input to the address input terminal Tadr via the switch circuit 1089, and the gain value data S1088 corresponding to the input address is input. Terminal Td
The gain value data corresponding to the address input and supplied to the data is written, and the gamma lookup table is newly written or rewritten.

Next, in the switch circuit 1090 that has actively received the line enable signal G-we, the output terminal c is held in a connected state with the input terminal a. As a result, in the RAM 1082 that has actively received the line enable signal G-we, the address signal S1086 from the counter 1086 is input to the address input terminal Tadr via the switch circuit 1090, and the gain value data S1088 corresponding to the input address is input. Terminal Td
The gain data corresponding to the supplied address is input to the data, and the gamma lookup table is newly written or rewritten.

Next, in the switch circuit 1091 that has actively received the line enable signal B-we, the output terminal c is held in a connected state with the input terminal a. As a result, in the RAM 1083 that has actively received the line enable signal B-we, the address signal S1086 from the counter 1086 is input to the address input terminal Tadr via the switch circuit 1091, and the gain value data S1088 corresponding to the input address is input. Terminal Td
The gain data corresponding to the supplied address is input to the data, and the gamma lookup table is newly written or rewritten.

As described above, the RAMs 1081 to 10
The gamma correction lookup table data 83 is rewritten.

When normal image display is performed in such a state, the analog video signal S
The supply of the image data 101 to the color decoder 102 is started.
The color decoder 102 demodulates three primary color signals of R, G, and B from the video signal S101 which is a composite color signal.
Scan converter 1 as R, G, B signals S102
03.

In the scan converter 103, the analog R, G, and B signals from the color decoder 102 are A / D converted, and the converted digital R, G, and B signals are written to a line buffer at a predetermined clock.
Then, in the scan converter 103, the written data is read out in synchronization with a clock having a frequency different from the frequency of the writing clock, and a digital signal R, which is a video signal corresponding to the number of vertical and horizontal pixels of the plasma display panel 106, is read. G and B signals S103-R, S103-
G and S103-B are generated and supplied to the gain control circuit 108.

At this time, in the gain control circuit 108, the write enable signals R-we, G-we, B-we
We are inactive and the switch circuits 1089 to
1091, the switch circuit 10
The output terminals c of 89 to 1091 are connected to the input terminal b. Therefore, in the RAM 1081 of the gain control circuit 108, the write enable signal R-we from the receiver 1084 is inactively input, and the digital R signal S103-R from the scan converter 103 is input to the address input terminal Tadr via the switch circuit 1089. , Data corresponding to the address is output to the driver 105 as a signal S108-R. That is, at this time, the RAM 1081 performs gamma correction and gain control based on the stored look-up table. Similarly, RAM 1082
Now, the write enable signal G by the receiver 1084
−we are input inactive and the switch circuit 109
0 through the digital G by the scan converter 103
The signal S103-G is input to the address input terminal Tadr, and data corresponding to the address is output to the driver 105 as a signal S108-G. And the RAM 108
3, the write enable signal B-we from the receiver 1084 is inactively input and the switch circuit 10
The digital B signal S103-B from the scan converter 103 is input to the address input terminal Tadr via the interface 91, and the data corresponding to the address is input to the signal S108-B.
To the driver 105.

Thus, the gain control circuit 1
08, the signals S108-R, S108-G,
S108-B is supplied to the driver 105, which drives the plasma display panel 106 to display an image corresponding to the input video signal.

As described above, according to the second embodiment, the clock D obtained by dividing the master clock MCLK is used.
CLK, counter 1086, first and second multiplier 1
087, 1088, and the microcomputer 1
07a is latched, and a trigger signal is output at the rising edge of the vertical retrace signal VBLK, for example, and the counter 1086 counts to generate an address signal S1086.
86 is squared by a first multiplier 1087 to generate γ correction data, and a second multiplier 1088 generates the γ correction data S
Actual gain value data S1 weighted by multiplying the gain data latched by the receiver 1087 and the receiver 1084
088, and the R, G, and B gamma correction look-up tables can be rewritten with the gain value data S1088 in synchronization with the 40 MHz master clock MCLK, and the gain control has RAMs 1081 to 1083 that can be read. Since the circuit 108 is provided, a low-speed circuit may be used even if a multiplier is used. As in the first embodiment, the cost and power consumption are not increased.
There is an advantage that a display device in which a malfunction does not occur even with a high-speed clock can be realized. In the second embodiment, all data is rewritten within the vertical blanking period, as compared with the case where all the gain data weighted by the γ correction data is generated by the microcomputer as in the first embodiment. be able to. As a result, there is an advantage that a response at the time of gain control is fast and a practical gain control circuit can be realized.

[0080]

As described above, according to the present invention,
A malfunction can be prevented even with a high-speed clock without increasing the cost and the power consumption. Further, there is an advantage that a response at the time of gain control is fast and a practical gain control circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a display device using a plasma display panel according to the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a gain control circuit according to the first embodiment.

FIG. 3 is a diagram illustrating an example of data stored in a RAM.

FIG. 4 is a block diagram showing a second embodiment of the display device using the plasma display panel according to the present invention.

FIG. 5 is a circuit diagram illustrating a configuration example of a gain control circuit according to a second embodiment.

FIG. 6 is a circuit diagram illustrating a main configuration of a receiver of a gain control circuit according to a second embodiment.

FIG. 7 is a timing chart showing a relationship among a trigger signal trg, a counter address signal S1086, and a gain value data signal S1088 according to the second embodiment.

FIG. 8 is a circuit diagram showing a configuration example of a conventional gain control circuit.

[Explanation of symbols]

100: display device, 101: video signal supply device, 102
... Color decoder, 103 ... Scan converter, 10
4 ... gain control circuit, 105 ... driver, 10
6 ... Plasma display panel (PDP), 107 ...
Microcomputer (microcomputer), 1041, 104
2,1043 RAM, 1044 Receiver, 1045
-1047 switch circuit, 1081, 1082, 10
83 RAM, 1084 Receiver, 1085 1/4
Frequency dividing circuit, 1086 ... Counter, 1087 ... First multiplier, 1088 ... Second multiplier, 1089-1091 ... Switch circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 9/69 G09G 3/28

Claims (32)

[Claims] When gain data weighted with correction data is stored in accordance with an address and a write enable signal is actively received, the gain data is weighted based on the supplied address data and gain data weighted with the correction data. When writing the gain data to be stored and receiving the write enable signal inactive,
Storage means for outputting gain data corresponding to an input address signal among the stored gain data; and receiving the address data and the gain data weighted by the correction data to activate a write enable signal to activate the write enable signal. And the received address data and gain data are supplied to the storage means. When the gain data weighted by the address data and the correction data is not received, the write enable signal is inactive to the storage means. And a supply means for outputting a predetermined digital video signal to the storage means as the address signal. 2. The gain control circuit according to claim 1, wherein said storage means writes and reads said gain data in synchronization with a master clock signal having a predetermined frequency. 3. The storage means according to claim 1, wherein the three primary color signals R (red),
G (green) and B (blue) are provided for each of the three storage circuits, and the supply means stores the address data and the gain data weighted by the correction data in the three primary color signals R
(Red), G (green), and B (blue), respectively, and the digital video signal is converted into three primary color signals R (red), G
(Green) and B (blue), and the supply means includes the three primary color signals R (red) and G
2. The gain control circuit according to claim 1, wherein (green) and B (blue) are supplied to corresponding storage circuits. 4. The storage means comprises three primary color signals R (red),
G (green) and B (blue) are provided for each of the three storage circuits, and the supply means stores the address data and the gain data weighted by the correction data in the three primary color signals R
(Red), G (green), and B (blue), respectively, and the digital video signal is converted into three primary color signals R (red), G
3. A gain according to claim 2, wherein the supply means supplies the three primary color signals R (red), G (green), and B (blue) to the corresponding storage circuits. Control circuit. 5. A display device for displaying an image corresponding to an input video signal on a predetermined display unit, wherein the gain data weighted with correction data according to an address is stored, and a write enable signal is actively received. When the write enable signal is inactive, the gain data to be stored is written based on the supplied address data and gain data weighted by the correction data. Storage means for outputting gain data corresponding to an input address signal to the display unit, and a control means for generating gain data weighted by the address data and the correction data upon receiving an upper gain data write command. Weighted by the address data and the correction data generated by the control means. When the gain data is received, a write enable signal is activated and output to the storage means,
The received address data and gain data are supplied to the storage means, and when the gain data weighted by the address data and the correction data is not received, the write enable signal is inactive and output to the storage means. And a supply unit for supplying the digital video signal as the address signal to the storage unit. 6. The display device according to claim 5, wherein said storage means writes and reads said gain data in synchronization with a master clock signal having a predetermined frequency. 7. The storage means comprises three primary color signals R (red),
G (green) and B (blue) are provided for each of the three storage circuits, and the supply means stores the address data and the gain data weighted by the correction data in the three primary color signals R
(Red), G (green), and B (blue), respectively, and the digital video signal is converted into three primary color signals R (red), G
(Green) and B (blue), and the supply means includes the three primary color signals R (red) and G
6. The display device according to claim 5, wherein (green) and B (blue) are supplied to corresponding storage circuits. 8. The storage means comprises three primary color signals R (red),
G (green) and B (blue) are provided for each of the three storage circuits, and the supply means stores the address data and the gain data weighted by the correction data in the three primary color signals R
(Red), G (green), and B (blue), respectively, and the digital video signal is converted into three primary color signals R (red), G
7. The display according to claim 6, wherein the supply means supplies the three primary color signals R (red), G (green), and B (blue) to the corresponding storage circuits. apparatus. 9. A gain value data weighted by correction data in accordance with an address is stored, and when a write enable signal is actively received, the gain value data weighted by the supplied address data and correction data is stored. Write the gain data to be stored based on the
When receiving the write enable signal inactive, the storage means for outputting gain data corresponding to the input address signal among the stored gain data; A receiving means for actively outputting an enable signal to the storage means and outputting a trigger signal at a predetermined timing received; an address generating means for receiving the trigger signal and generating the address data; an address by the address generating means Correction data generating means for generating weighted correction data by data; gain value data to be supplied to the storage means by weighting the gain data received by the receiving means with the correction data generated by the correction data generating means Generating means; and when the write enable signal is active, Supply means for supplying the address data generated by the address generation means to the storage means, and supplying a predetermined digital video signal to the storage means as the address signal when the write enable signal is inactive. Gain control circuit. 10. The gain control circuit according to claim 9, wherein said receiving means outputs said trigger signal in synchronization with a vertical retrace signal of a video signal. 11. The storage means writes and reads the gain data in synchronization with a master clock signal of a predetermined frequency, divides the frequency of the master clock,
10. The gain control circuit according to claim 9, further comprising a frequency dividing circuit for supplying at least one of the correction data generation means and the gain value data generation means as an operation clock to the gain value data generation means. 12. The storage means writes and reads the gain data in synchronization with a master clock signal having a predetermined frequency, divides the frequency of the master clock,
11. The gain control circuit according to claim 10, further comprising a frequency dividing circuit that supplies at least the gain value data generation means as an operation clock to the correction data generation means and the gain value data generation means. 13. The correction data generating means includes a first multiplier for calculating a power of the address data generated by the address generating means, and the gain value data generating means is generated by the correction data generating means. A second multiplier for multiplying the corrected data and the gain data, wherein an operation clock by the frequency dividing circuit is at least the first clock.
13. The gain control circuit according to claim 12, which is supplied to a second multiplier and a second multiplier. 14. The correction data generating means includes a first multiplier for calculating a power of the address data generated by the address generating means, and the gain value data generating means is generated by the correction data generating means. A second multiplier for multiplying the corrected data and the gain data, wherein an operation clock by the frequency dividing circuit is at least the first clock.
14. The gain control circuit according to claim 13, wherein the gain control circuit is supplied to a second multiplier. 15. The storage means according to claim 3, wherein said three primary color signals R
(Red), G (green), and B (blue), each of which includes three storage circuits.
(Red), G (green), and B (blue), respectively, and the digital video signal is converted into three primary color signals R (red), G
10. The display according to claim 9, wherein the supply means supplies the three primary color signals R (red), G (green), and B (blue) to the corresponding storage circuits. apparatus. 16. The storage means comprises a three-primary-color signal R
(Red), G (green), and B (blue), each of which includes three storage circuits.
(Red), G (green), and B (blue), respectively, and the digital video signal is converted into three primary color signals R (red), G
(Green) and B (blue), and the supply means includes the three primary color signals R (red) and G
11. The display device according to claim 10, wherein (green) and B (blue) are supplied to corresponding storage circuits. 17. The memory according to claim 17, wherein the storage means stores the three primary color signals R
(Red), G (green), and B (blue), each of which includes three storage circuits.
(Red), G (green), and B (blue), respectively, and the digital video signal is converted into three primary color signals R (red), G
(Green) and B (blue), and the supply means includes the three primary color signals R (red) and G
12. The display device according to claim 11, wherein (green) and B (blue) are supplied to corresponding storage circuits. 18. The storage means according to claim 3, wherein the three primary color signals R
(Red), G (green), and B (blue), each of which includes three storage circuits.
(Red), G (green), and B (blue), respectively, and the digital video signal is converted into three primary color signals R (red), G
(Green) and B (blue), and the supply means includes the three primary color signals R (red) and G
13. The display device according to claim 12, wherein (green) and B (blue) are supplied to corresponding storage circuits. 19. The storage means stores the three primary color signals R
(Red), G (green), and B (blue), each of which includes three storage circuits.
(Red), G (green), and B (blue), respectively, and the digital video signal is converted into three primary color signals R (red), G
(Green) and B (blue), and the supply means includes the three primary color signals R (red) and G
14. The display device according to claim 13, wherein (green) and B (blue) are supplied to corresponding storage circuits. 20. The storage device, comprising:
(Red), G (green), and B (blue), each of which includes three storage circuits.
(Red), G (green), and B (blue), respectively, and the digital video signal is converted into three primary color signals R (red), G
(Green) and B (blue), and the supply means includes the three primary color signals R (red) and G
15. The display device according to claim 14, wherein (green) and B (blue) are supplied to corresponding storage circuits. 21. A display device for displaying an image corresponding to an input video signal on a predetermined display unit, wherein gain value data weighted with correction data according to an address is stored, and a write enable signal is activated. When the write enable signal is received, the gain data to be stored is written based on the supplied address data and the gain value data weighted by the correction data. When the write enable signal is received inactive, the gain data is stored. A storage unit for outputting gain data corresponding to an input address signal among the gain data to the display unit; and a control unit for generating gain data not weighted by the correction data when receiving an upper gain data write command. When the gain data not weighted by the control means is received, the write enable Receiving means for outputting a trigger signal to the storage means in an active manner and outputting a trigger signal at a predetermined timing received; address generating means for receiving the trigger signal and generating the address data; and an address by the address generating means. Correction data generating means for generating weighted correction data by data; gain value data to be supplied to the storage means by weighting the gain data received by the receiving means with the correction data generated by the correction data generating means Generating means for supplying the address data generated by the address generating means to the storage means when the write enable signal is active, and transmitting the predetermined digital video signal to the address when the write enable signal is inactive; Display device having supply means for supplying a signal to the storage means . 22. The display device according to claim 21, wherein said receiving means outputs said trigger signal in synchronization with a vertical blanking signal of a video signal. 23. The storage means writes and reads the gain data in synchronization with a master clock signal having a predetermined frequency, divides the frequency of the master clock,
22. The display device according to claim 21, further comprising a frequency dividing circuit that supplies at least one of the correction data generating means and the gain value data generating means as an operation clock to the gain value data generating means. 24. The storage means writes and reads the gain data in synchronization with a master clock signal of a predetermined frequency, divides the frequency of the master clock,
23. The display device according to claim 22, further comprising a frequency dividing circuit for supplying at least one of the correction data generating means and the gain value data generating means to the gain value data generating means as an operation clock. 25. The correction data generating means includes a first multiplier for calculating a power of the address data generated by the address generating means, and the gain value data generating means is generated by the correction data generating means. A second multiplier for multiplying the corrected data and the gain data, wherein an operation clock by the frequency dividing circuit is at least the first clock.
The display device according to claim 23, wherein the display device is supplied to a second multiplier and a second multiplier. 26. The correction data generating means includes a first multiplier for calculating a power of the address data generated by the address generating means, and the gain value data generating means is generated by the correction data generating means. A second multiplier for multiplying the corrected data and the gain data, wherein an operation clock by the frequency dividing circuit is at least the first clock.
25. The display device according to claim 24, wherein the display device is supplied to a second multiplier and a second multiplier. 27. The storage device according to claim 27, wherein the three primary color signals R
(Red), G (green), and B (blue), each of which includes three storage circuits.
(Red), G (green), and B (blue), respectively, and the digital video signal is converted into three primary color signals R (red), G
(Green) and B (blue), and the supply means includes the three primary color signals R (red) and G
22. The display device according to claim 21, wherein (green) and B (blue) are supplied to corresponding storage circuits. 28. The storage device according to claim 28, wherein the three primary color signals R
(Red), G (green), and B (blue), each of which includes three storage circuits.
(Red), G (green), and B (blue), respectively, and the digital video signal is converted into three primary color signals R (red), G
(Green) and B (blue), and the supply means includes the three primary color signals R (red) and G
23. The display device according to claim 22, wherein (green) and B (blue) are supplied to corresponding storage circuits. 29. The storage means according to claim 3, wherein the three primary color signals R
(Red), G (green), and B (blue), each of which includes three storage circuits.
(Red), G (green), and B (blue), respectively.
(Green) and B (blue), and the supply means includes these three primary color signals R (red) and G
24. The display device according to claim 23, wherein (green) and B (blue) are supplied to corresponding storage circuits. 30. The storage device according to claim 27, wherein the three primary color signals R
(Red), G (green), and B (blue), each of which includes three storage circuits.
(Red), G (green), and B (blue), respectively, and the digital video signal is converted into three primary color signals R (red), G
(Green) and B (blue), and the supply means includes the three primary color signals R (red) and G
25. The display device according to claim 24, wherein (green) and B (blue) are supplied to corresponding storage circuits. 31. The storage means, comprising: a three-primary-color signal R;
(Red), G (green), and B (blue), each of which includes three storage circuits.
(Red), G (green), and B (blue), respectively, and the digital video signal is converted into three primary color signals R (red), G
26. The display according to claim 25, wherein the supply means supplies the three primary color signals R (red), G (green), and B (blue) to the corresponding storage circuits. apparatus. 32. The storage device, comprising: a three-primary-color signal R;
(Red), G (green), and B (blue), each of which includes three storage circuits.
(Red), G (green), and B (blue), respectively, and the digital video signal is converted into three primary color signals R (red), G
(Green) and B (blue), and the supply means includes the three primary color signals R (red) and G
27. The display device according to claim 26, wherein (green) and B (blue) are supplied to corresponding storage circuits.