JP2001074804A - Testing apparatus and testing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a testing apparatus capable of reducing delivery loss of CMOS(complementary metal oxide semiconductor) integrated circuit. SOLUTION: This testing apparatus 100 is equipped with a power source circuit 10 supplying power to a CMOS integrated circuit 60, an applying circuit 30 applying a test signal to the CMOS integrated circuit 60, a measuring circuit 20 measuring, at a plurality of measurement points, a static power source current IDDQ supplied to the CMOS integrated circuit 60 from the power source circuit 10, and a judging circuit 40 which compares each of the measured values of the current IDDQ with a set value and detects normality/abnormality of each of the detected values. The judging circuit judges that the integrated circuit 60 is acceptable, when the abnormality detection frequency is at least a reference frequency, and judges that the integrated circuit 60 is unacceptable when the abnormality detection frequency is a positive value smaller than the reference frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS (Comple
mentary Metal Oxide Semiconductor) The present invention relates to a test apparatus and a test method for an integrated circuit.

[0002]

2. Description of the Related Art JP-A-8-271584, JP-A-9-211088, US Pat. No. 5,392,293, and US Pat.
P5519333 and US Pat. No. 5,889,408 include a static power supply current (I _DDQ : Quiesc) of a CMOS integrated circuit.
ent power supply current) ( _IDDQ test).

Japanese Patent Application Laid-Open No. 8-271584 discloses I
An invention of a test circuit capable of specifying a defective portion of a CMOS integrated circuit during a _DDQ test is disclosed. JP-A-9-2
Japanese Patent Publication No. 11088 discloses that a test pattern is applied to a CMOS integrated circuit and a static power supply current is detected from a specific frequency component in a power spectrum of the power supply current.

[0004] US Pat. No. 5,392,293 discloses that a static power supply current is detected by a current sensor, and a defect of a CMOS integrated circuit is detected based on the magnitude of the detection result and a set value. USP 5,519,333 has a burn-in (bu
rn-in) and the I _DDQ test in combination to detect defects in CMOS integrated circuits. USP58
89408 discloses that a first static power supply current when a part of a CMOS integrated circuit is biased is compared with a second static power supply current when no bias is applied to detect a defect. It has been disclosed.

The power supply current of the CMOS integrated circuit includes:
There is a current (switching current) that flows temporarily when the MOS transistor is switched, and a steady and minute leakage current. Therefore, by detecting a current other than the switching current and the leak current, the CM
It is possible to detect an abnormality of the OS integrated circuit. I
_{The DDQ} test is a test for a CMOS integrated circuit focusing on this point.

In the conventional I _DDQ test in which the static power supply current I _DDQ is measured and the CMOS integrated circuit is defective when the measured value is equal to or _larger than the set value, a shipping loss occurs in which a non-defective product is detected as defective. This is because the I _DDQ test is sensitive to a defect that does not cause a performance defect of the CMOS integrated circuit.

[0007] S. Davidson. "IS I _DDQ YIELD LOSS INEVITA
BLE?, ". In Int.Test.Conf., Pp.572-578.IEEE, 1994. And CFHawkins and JMSoden." TEST & MEASUREMEN
T, ". IEEE SPECTRUM, pp.65-69, Jan.1996. According to the conventional I _DDQ test, there is no way to avoid the shipping loss, and the shipping loss is the necessary cost to maintain the shipping quality. Have been.

[0008] Among shipping losses, a CMOS having a gate oxide film defect (GOS: Gate Oxide Shorts) in a deterioration process is included.
An integrated circuit was said to be included. P. Nigh, W. Needham,
K. Butler, P. Maxwell, R. Aitken, and W. Maly. "SO WHAT IS
ANOPTIMAL TEST MIX? A DISCUSSION OF THE SEMATECH
METHODS EXPERIMENT, ". InInt.Test.Conf., Pp.1037-103
8.IEEE, 1997. And JTYChang and E.McCluskey. "DET
ECTING DELAY FLAWS BY VERY-LOW-VOLTAGE TESTING, ". I
n Int. Test. Conf., pp. 367-376. IEEE, 1996. According to other tests for delay faults, etc., it is possible to detect gate oxide film defects in CMOS integrated circuits. It is possible. For this reason, even if a CMOS integrated circuit has detected an abnormality in the I _DDQ test, a CMOS integrated circuit that has passed another test with a high detection rate of a gate oxide film defect is likely to be a good product.

Here, a test flow of the CMOS integrated circuit will be described. FIG. 1 is an explanatory diagram illustrating a test flow of a CMOS integrated circuit by way of example. In step F1, Nin CMOS integrated circuits that have passed other tests are prepared.
In step F2, an I _DDQ test is performed on the Nin CMOS integrated circuits. As a result of this I _DDQ test, step F
In No. 3, Nof defective products are detected, and at step F4
Then, Nin-Nof non-defective products are detected.

In step F5, the CMOS integrated circuit which is determined to be defective in the I _DDQ test is mounted on a printed board of a final system into which a non-defective CMOS integrated circuit is to be finally incorporated, and operates normally on this printed board. Perform a system test to determine if As a result of this system test, Ng non-defective products are detected in step F6, and Ns defective products are detected in step F7.

N detected as a defective product in the system test
If the s CMOS integrated circuits are called intrinsically defective CMOS integrated circuits and the Ng CMOS integrated circuits detected as non-defective products are called pseudo defective CMOS integrated circuits, the pseudo defective CMOS integrated circuits pass the _IDDQ test. And loss of shipment (Yield Loss). The shipping loss rate YL, which is the ratio of the shipping loss, is expressed by the following equation.

[0012]

(Equation 1)

In the above equation, (Nof / Nin) is about several percent, (Ns / Nin) is about several tens to several hundred ppm, and the shipping loss rate YL can be approximated as the following equation.

[0014]

[Equation 2] YL ≒ Nof / Nin ...

[0015]

The shipping loss can reach 2 to 4% of CMOS integrated circuits that have passed tests other than the _IDDQ test (for example, functional tests, etc.). It increases as the circuit scale of the Integrated Circuit increases. For this reason, it is difficult to apply the conventional I _DDQ test to low-cost CMOS integrated circuits, and it is desired to reduce shipping loss.

From the above equation, to reduce the shipping loss, I
_What is necessary is just to reduce the number of detections Nof detected as defects in the _DDQ test. Here, increasing the set value for comparison, which is compared with the measured value of the static power supply current I _DDQ , corresponds to the detected number N
can be reduced, but the number of detected intrinsic defects Ns is undesirably reduced. This will be described with reference to FIGS.

FIG. 2 shows CMOs of intrinsic failure and pseudo failure.
9 is a histogram (columnar graph) illustrating the relationship between the maximum value (maximum I _DDQ ) of the static power supply current I _DDQ and the distribution ratio for the S integrated circuit. The number Ns of intrinsic defects is 42, the number Ng of pseudo defects is 258, and the maximum _IDDQ is 30 μA or more. The horizontal axis indicates the magnitude of the maximum I _DDQ , which is 0 μA or more and less than 100 μA,
0 μA or more and less than 200 μA,..., 700 μA or more and 800
It is classified into each category of less than μA and 800 μA or more.

As shown in FIG. 2, the maximum I _DDQ of intrinsically and pseudo-defective CMOS integrated circuits has a similar distribution. Therefore, when the set value for comparison is increased, the shipping loss is reduced, but the number of intrinsic defects is also reduced.

FIG. 3 is a graph showing the relationship between the set value and the CMOS integrated circuit having the maximum I _DDQ equal to or greater than the set value for the intrinsically defective and pseudo-defective CMOS integrated circuits of FIG. In FIG. 3, C having a maximum I _DDQ equal to or greater than the set value is used.
The ratio of the MOS integrated circuit is shown on the vertical axis as the inverse cumulative ratio. This inverse accumulation rate indicates the proportion of CMOS integrated circuits that are detected as defective in the conventional I _DDQ test. FIG.
As shown in the figure, the set value for comparison was changed from 30 μA to 450 μA.
When the value is increased to A, the reverse cumulative rate of the pseudo failure decreases to 50%, but the reverse cumulative rate of the intrinsic failure also decreases to 50%.

As described above, increasing the set value for comparison in order to reduce the shipment loss can reduce the number of detected defects Nof in the _IDDQ test, but is not preferable because the number Ns of intrinsic defects decreases. In order to reduce the shipping loss, a method other than increasing the set value for comparison is desired. An object of the present invention is to provide a test apparatus and a test method capable of reducing a shipping loss of a CMOS integrated circuit.

[0021]

According to the present invention, there is provided a test apparatus comprising: a power supply circuit for supplying power to a CMOS integrated circuit; an application circuit for applying a test signal to the CMOS integrated circuit; A measuring circuit for measuring static power supply current supplied to the circuit at a plurality of measuring points;
The measured value of the static power supply current is compared with a set value to detect normality / abnormality of each measured value. A determination circuit for determining the CMOS integrated circuit as a defective product when the number of times of abnormality detection is a positive value less than the reference number of times.

In the test apparatus according to the present invention, preferably, the reference number is equal to or less than the number of the measurement points and equal to or substantially equal to the number of the measurement points.

In the test apparatus according to the present invention, preferably, the test signal has a plurality of test patterns, and the application circuit includes the test signal between adjacent measurement points among the plurality of measurement points. Performs pattern switching.

In the test apparatus according to the present invention, preferably, when the measured value of the static power supply current is equal to or larger than the set value, the determination circuit detects that the measured value is abnormal.

According to the test method of the present invention, a static power supply current of the CMOS integrated circuit is measured at a plurality of measurement points by applying a test signal to the CMOS integrated circuit, and the quality of the CMOS integrated circuit is determined based on the measurement result. A test method for performing
Comparing each measured value of the static power supply current with a set value to detect normality / abnormality of each measured value; and determining that the CMOS integrated circuit is non-defective when the number of times of abnormality detection is equal to or greater than a reference number. Determining the CMOS integrated circuit as a defective product when the abnormality detection count is a positive value less than the reference count.

In the test method according to the present invention, preferably, the reference number is equal to or less than the number of the measurement points and equal to or substantially equal to the number of the measurement points.

In the test method according to the present invention, preferably, the test signal has a plurality of test patterns,
The method further includes the step of switching the test pattern between adjacent measurement points among the plurality of measurement points.

In the test method according to the present invention, preferably, in the detecting step, when the measured value of the static power supply current is equal to or larger than the set value, the measured value is detected as abnormal.

The test method according to the present invention preferably further comprises a step of accumulating the number of times of abnormality detection in the lot of the CMOS integrated circuit, and correcting the reference number of times based on the accumulated number of times of abnormality detection. .

In the test method according to the present invention, preferably, a step of creating a failure model of the CMOS integrated circuit, and applying the test signal to the failure model of the CMOS integrated circuit to reduce the static power supply current The method further includes a step of predicting the number of times of abnormality detection when measuring at a plurality of measurement points, and a step of determining the reference number of times based on the predicted number of times of abnormality detection.

The determination circuit compares each measured value of the measuring circuit with a set value and detects whether each measured value is normal or abnormal. This determination circuit determines that the CMOS integrated circuit is non-defective when the number of times of detection of the abnormality is equal to or more than the reference number, so that the static power supply current constantly flowing through the CMOS integrated circuit is slightly larger than the set value. In this case, this CMOS integrated circuit can be made a good product. On the other hand, the determination circuit
If the abnormality detection count is a positive value less than the reference count, C
Since the MOS integrated circuit is determined as defective, the CMOS
If the integrated circuit has an unsteady leakage current,
The MOS integrated circuit can be rejected.

[0032]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 4 is a schematic block diagram showing an embodiment of the test apparatus according to the present invention. The test apparatus 100 includes a power supply circuit 10, a measurement circuit 20, an application circuit 30, a determination circuit 40, and an output circuit 50.

The power supply circuit 10 receives C
Power is supplied to the MOS integrated circuit 60. This power supply circuit 1
0 supplies the power supply voltage V _DD and the power supply current I _DD to the CMOS integrated circuit 60.

The application circuit 30 applies a test signal to the CMOS integrated circuit 60. The test signal has a plurality of test patterns, and the application circuit 30 sequentially applies each test pattern TP to the CMOS integrated circuit 60.
The application circuit 30 includes, for example, a microcomputer (microcomputer) storing a plurality of test patterns TP.
Applied to the S integrated circuit 60. Further, the application circuit 30 applies the timing signal S3 indicating the measurement point of the static power supply current I _DDQ while applying the predetermined test pattern.
0 is supplied to the measurement circuit 20 and the determination circuit 40. Further, the application circuit 30 shifts to the next test pattern TP in response to the detection end signal S40 from the determination circuit 40, and applies the test pattern TP to the CMOS integrated circuit 60.

The measuring circuit 20 is such that the application circuit 30 is a CMOS
When the predetermined test pattern is applied to the integrated circuit 60, the power supply circuit 10
Measure the static power supply current I _DDQ supplied to zero. For example, according to the timing signal S30, the static power supply current I _DDQ
Is measured, and a measurement signal S20 indicating the measured value is determined by the determination circuit 40.
To supply.

The judgment circuit 40 has a microcomputer,
The measured value and the set value of the static power supply current I _DDQ are compared to detect whether each measured value is normal or abnormal, and a detection end signal S40 is supplied to the application circuit 30. Then, the determination circuit 40 determines whether the CMOS integrated circuit 60
Is determined as a non-defective product, and when the number of times of abnormality detection is a positive value less than the reference frequency, the CMOS integrated circuit 60 is determined as a defective product. The determination circuit 40 determines that the CMOS integrated circuit 60 is non-defective when the number of times of abnormality detection is zero.

The output circuit 50 is constituted by, for example, a display device or a printer.
A determination signal S45 indicating a determination result of pass / fail of 0 is supplied,
The pass / fail judgment result is displayed on a display screen or printed on a print medium.

FIG. 5 is a schematic flow chart showing an operation example of the test apparatus 100 shown in FIG. 4, and is a flow chart illustrating a test method according to the present invention. First, in step S1, initialization is performed, and the determination circuit 40
Resets the value of the abnormality detection frequency Nf to zero. In step S2, the application circuit 30 applies the test signal of the predetermined test pattern TP to the CMOS integrated circuit 60, and outputs the timing signal S30 when the test signal of the predetermined test pattern is applied.
To supply. The measurement circuit 20 measures the static power supply current I _DDQ when the predetermined test pattern is applied, and supplies a measurement signal S20 indicating the measured value to the determination circuit 40.

In step S3, the determination circuit 40 compares the measured value of the static power supply current I _DDQ with the set value Ith. If the measured value is less than the set value Ith, the process proceeds to step S5. If the measured value is equal to or greater than the set value Ith, the process proceeds to step S4, in which the number of times of abnormality detection Nf is incremented and increased by 1, and the process proceeds to step S5.

In step S5, the determination circuit 40 determines whether the application of the plurality of test patterns TP by the application circuit 30 has been completed and all the static power supply currents I _DDQ at the time of application of each of the predetermined test patterns have been measured. Determine whether or not. Proceeds to step S7 when measuring IDDQ I _DDQ of a plurality of measurement points that are scheduled, if not measured IDDQ I _DDQ of a plurality of measurement points that are scheduled, detection end signal S40 Is supplied to the application circuit 30, and the process proceeds to step S6.

In step S6, the application circuit 30 shifts to the next predetermined test pattern TP and applies the predetermined test pattern TP to the CMOS integrated circuit 60. When the predetermined test pattern is applied, the timing signal S3 is applied.
0 is supplied to the measurement circuit 20 and the determination circuit 40. The measurement circuit 20 measures the static power supply current I _DDQ when the predetermined test pattern is applied, and supplies a measurement signal S20 indicating the measurement result to the determination circuit 40. Then, returning to step S3, the determination circuit 40 compares the measured value with the set value Ith.

In step S7, the determination circuit 40 determines whether or not the number of times of abnormality detection Nf is equal to or greater than the reference number of times NA. If the abnormality detection frequency Nf is equal to or greater than the reference frequency NA, the CMOS integrated circuit 60 is determined to be non-defective in step S8, and a determination signal S45 indicating the determination result is supplied to the output circuit 50.
If the number of times of abnormality detection Nf is less than the reference number of times NA, the CMOS integrated circuit 60 is determined to be defective in step S9,
The determination signal S45 indicating the determination result is supplied to the output circuit 50.

Tests performed conventionally (for example, I _DDQ
In a test, a function test, a scan test, a delay test, and the like), when a CMOS integrated circuit is determined to be defective, the test is often terminated at that point. In the test apparatus 100, based on the measurement results at all predetermined measurement points, C
The quality of the MOS integrated circuit is determined, and the configuration is unique.

FIG. 6 is a histogram (column graph) showing the relationship between the abnormality detection rate and the distribution rate when a test pattern is applied to the intrinsically defective and pseudo-defective CMOS integrated circuits of FIG. The horizontal axis in FIG. 6 indicates the magnitude of the abnormality detection rate Rf, which is greater than 0% and 10% or less, greater than 10% and 20% or less,.
It is classified into the following categories.

The abnormality detection rate Rf is a ratio of the number of times of abnormality detection Nf to the number of measurements (the number of measurement points) Nt, and Rf = Nf /
Nt. In FIG. 6, the measured number Nt of the static power supply current I _DDQ for one CMOS integrated circuit is 390, and the test pattern is stuck-at fault (logic 1 or 0).
The test pattern for detecting the failure fixed to the above was used.
As shown in FIG. 6, the abnormality detection rate Rf is close to 100%,
When the number of times of abnormality detection Nf is the same or substantially the same as the number of measurements Nt, there are many false defects. On the other hand, the abnormality detection rate R
When f is 10% or less, there are many intrinsic defects.

FIG. 7 is a graph showing the relationship between the reference detection rate and the CMOS integrated circuit having an abnormality detection rate less than the reference detection rate for the intrinsically defective and pseudo-defective CMOS integrated circuits of FIG. The reference detection rate Ra is a ratio of the reference number of times Na and the number of measurements Nt, and Ra = Na / Nt. FIG.
In the case of a CMO with an abnormality detection rate less than the reference detection rate Ra,
The vertical axis indicates the ratio of the S integrated circuit as the cumulative ratio.
This accumulation rate corresponds to the percentage of CMOS integrated circuits that are determined to be defective by the test apparatus 100.

As shown in FIG. 7, the reference detection rate Ra is 90
%, And the reference number of times Na is set to 351 (= 390 × 0.9), it is possible to make the accumulation rate of the pseudo failure 39% and the accumulation rate of the intrinsic failure 98%. That is, most of the intrinsically defective CMOS integrated circuits can be determined to be defective, and the rate of detecting falsely defective CMOS integrated circuits as defective can be suppressed to 39%.

Further, by setting the reference detection rate Ra to 20% and the reference number of times Na to 78 (= 390 × 0.2), the accumulation rate of pseudo defects can be made 9%, and the accumulation of intrinsic defects can be made. The rate can be 64%. That is, the ratio of detecting a falsely defective CMOS integrated circuit is determined by the ratio of an intrinsically defective CM.
It can be lower than the rate of detecting an OS integrated circuit.

In the reference number and measurement number MOS transistors, a leakage current occurs due to a bridge between signal lines connected to the gate, source, or drain. The I _DDQ test detects a leak current caused by a bridge between a power supply line, a ground line, and a signal line of a CMOS integrated circuit.

The leak current due to the bridge between the power supply line and the ground line flows constantly without depending on the test pattern and is detected at all the measurement points, so that the abnormality detection rate Ra is 100%. Since this bridge does not affect the circuit operation of the CMOS integrated circuit and merely slightly increases the power consumption, the CMOS integrated circuit having the bridge should be determined as a non-defective product. That is, when the measured values are equal to or greater than the set value Ith at all the measurement points, the CMOS integrated circuit should be determined as a non-defective product.

If the increase in power consumption (or current consumption) cannot be tolerated as the power consumption (or current consumption) of the CMOS integrated circuit in the standby state, it is determined as a defective product. Such a CMOS integrated circuit with power consumption (or current consumption) exceeding the allowable range has a level of the magnitude of the leakage current different from the static power supply current I _DDQ ,
_It can be detected by a test different from the _DDQ test.

Intrinsically defective and pseudo defective CMOS shown in FIG.
In the integrated circuit (Ns = 42, Ng = 258), the measured values of all the measurement points in the 139 CMOS integrated circuits are equal to or larger than the set value Ith, which accounts for 54% of all the pseudo-defective CMOS integrated circuits. Further, by making the reference number Na equal to the number of measurements (the number of all measurement points) Nt, all intrinsically defective CMOS integrated circuits can be detected.

The reference number Na is determined by the relationship between the abnormality detection rate Rf and the distribution rate for the intrinsically defective and pseudo-defective CMOS integrated circuits as shown in FIG.
It can be determined from the relationship between and the accumulation rate.

However, in order to obtain the relationship between the abnormality detection rate Rf and the distribution rate or the relationship between the reference detection rate Ra and the accumulation rate for a CMOS integrated circuit having an intrinsic defect, a large number of CMs are required.
It is necessary to collect OS integrated circuits. For example, to obtain 40 intrinsically defective CMOS integrated circuits, Ns / Nin
Is 40,000 (= Nin) CMOS when is 1000 ppm
System testing of integrated circuits is required and is quite difficult. In such a case, the abnormality detection rate Rf is determined for Nof CMOS integrated circuits determined to be defective in the conventional I _DDQ test.
It is preferable to obtain the relationship between the distribution rate and the reference detection rate Ra and the cumulative rate. Alternatively, the number of times of abnormality detection Nf in the lot of the CMOS integrated circuit may be accumulated, and the reference number of times NA may be corrected based on the accumulated number of times of abnormality detection Nf.

It is possible to predict the number of abnormal detections at the time of applying the simulation test pattern by simulation and determine the reference number from the predicted number of abnormal detections. FIG. 8 is an explanatory diagram showing the flow of creating a graph using simulation.

First, the circuit information 70, the failure definition information 71, and the library information 72 of the CMOS integrated circuit to be tested are
The failure candidate creating means 74 is supplied to the failure candidate creating means 74.
4 creates information on a fault model and a fault candidate of the CMOS integrated circuit. The fault definition information 71 has information defining faults that can be detected in the I _DDQ test of the CMOS integrated circuit,
For example, it has information on a failure in which a leak current flows between a power supply line and a ground line. The library information 72 has predetermined information at the time of creating a CMOS integrated circuit, and has, for example, positioning information such as an arrangement of MOS transistors.

Next, the circuit information 70 of the CMOS integrated circuit,
A failure simulation 77 is performed based on the failure definition information 71, the library information 72, the test pattern measurement point information 73, the information on the failure model and the failure candidate. The test pattern measurement point information 73 includes information on a plurality of test patterns sequentially applied to the CMOS integrated circuit, and further includes information on a predetermined test pattern when the static power supply current I _DDQ is measured.

When the failure candidate created by the failure candidate creation means 74 is detected by the failure simulation 77, the failure candidate detection number 75 is counted up by the detection number addition means 76 and updated. This failure candidate detection frequency 7
Reference numeral 5 corresponds to the number of abnormalities detected when the CMOS integrated circuit is actually tested.

After the failure simulation 77 is completed, the relation calculating means 78 calculates the relation between the abnormality detection rate and the distribution rate based on the number of times of failure detection 75 of all the faults, and calculates the relation between the reference detection rate and the cumulative rate. Is calculated. Graph creation means 7
9 creates a graph showing the relationship between the abnormality detection rate and the distribution rate based on the calculation result of the relationship calculation means 78, and creates a graph showing the relationship between the reference detection rate and the cumulative rate. Based on the graph created in this way, it is possible to determine the optimal reference detection count for reducing shipping loss. For example, a reference detection rate that maximizes the difference between the cumulative rate of the genuine failure and the false failure may be determined, and the reference number may be determined based on the reference detection rate.

The above-mentioned fault candidate creating means 74, detection number adding means 76, relation calculating means 78 and graph creating means 79 are constituted by, for example, a computer, and perform a failure simulation using the computer.

Note that an automatic pattern generator (ATPG: Au
A plurality of test patterns generated by a tomatic test pattern generator) may be compared with a plurality of test patterns used for a functional test, and a test pattern that increases the number of detectable fault candidates may be used. .

According to the test apparatus 100, it is possible to reduce the shipping loss while suppressing the rise in the shipping failure rate, thereby making it possible to reduce the cost and increase the production amount of the CMOS integrated circuit.

[0064] Further, upon testing of CMOS integrated circuits, I _DDQ of measuring the IDDQ I _DDQ just a single measurement point
Test (hereinafter, referred to as "one point I _DDQ test") to, I _DDQ test that measures the IDDQ I _DDQ at a plurality of measurement points (hereinafter, referred to as "multi-point I _DDQ test") present and change in By adopting the embodiment, it is possible to improve the shipping defect rate and reduce the shipping rate.

This is for the following reason. Y. Okuda,
I.Kubota, and M.Watanabe. "DEFECT LEVEL PREDICTION F
OR I _DDQ TESTING, ". In Int.Test.Conf., Pp.900-909.IEE
According to E, 1998., the defective detection rate per measurement point in the _IDDQ test for defective products in the manufactured product may be 70 to 90%. The defect detection rate in the one-point I _DDQ test is D1
Assuming that the defect detection rate per measurement point is 80%,
The defect detection rate D2 in the ideal multipoint I _DDQ test is D2 =
D1 / 0.8 = 1.25D1. Since the shipping loss rate can be approximated to the defect detection rate, if the reduction of the shipping loss in the multi-point I _DDQ test of the present embodiment is set to 80% or less, the shipping loss can be reduced to one point I _DDQ test or less. Multipoint I of the embodiment
The increase in the number of intrinsic defects detected by the _DDQ test can improve the shipping defect rate.

The standby test (standby current test) measures the static power supply current I _DDQ and is similar to the one-point I _DDQ test. In the standby test, the multi-point I _DDQ test of the present embodiment can be applied other than a special test such as turning on / off a power supply circuit of a CMOS integrated circuit.

Also, due to the cost increase due to the shipping loss, I _DDQ
The multipoint I _DDQ test of the present embodiment can be applied to a CMOS integrated circuit for which application of the test has been refrained from being applied, and the defective shipment rate can be improved. The above embodiment is an exemplification of the present invention, and the present invention is not limited to the above embodiment.

[0068]

According to the test apparatus and the test method of the present invention, each measured value of the static power supply current is compared with a set value to detect normality / abnormality of each measured value. If the number of times of abnormality detection is equal to or more than the reference number, the CMOS integrated circuit is determined to be non-defective. Therefore, if the static power supply current constantly flowing through the CMOS integrated circuit is larger than the set value, the CMOS
The S integrated circuit can be a non-defective product, and shipping loss can be reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating a test flow of a CMOS integrated circuit by way of example;

FIG. 2 is a histogram illustrating the relationship between the maximum value (maximum I _DDQ ) of the static power supply current I _DDQ and the distribution ratio for intrinsically defective and pseudo-defective CMOS integrated circuits.

3 is a graph showing a relationship between a set value and a CMOS integrated circuit having a maximum I _DDQ equal to or _larger than the set value, for the intrinsically defective and pseudo-defective CMOS integrated circuits of FIG. 2;

FIG. 4 is a schematic block diagram showing an embodiment of a test apparatus according to the present invention.

FIG. 5 is a flowchart showing an embodiment of a test method according to the present invention.

6 is a histogram showing a relationship between an abnormality detection rate and a distribution rate when a predetermined test pattern is applied to the intrinsically defective and pseudo-defective CMOS integrated circuits of FIG. 2;

7 is a graph showing a relationship between a reference detection rate and a CMOS integrated circuit having an abnormality detection rate less than the reference detection rate for the intrinsically defective and pseudo-defective CMOS integrated circuits of FIG. 6;

FIG. 8 is an explanatory diagram showing a flow of creating a graph using a simulation.

[Explanation of symbols]

10 power supply circuit, 20 measurement circuit, 30 application circuit, 4
0 ... determination circuit, 50 ... output circuit, 60 ... CMOS integrated circuit, 70 ... circuit information, 71 ... failure definition information, 72 ... library information, 73 ... test pattern measurement point information, 74 ...
Failure candidate creation means, 75: Number of failure candidate detections, 76: Detection number addition means, 77: Failure simulation, 78 ...
Relationship calculation means, 79: Graph creation means, 100: Test equipment, I _DD ... Power supply current, I _DDQ ... Static power supply current, Ith: Set value, NA: Reference count, Nf: Abnormal detection count, S20 ...
Measurement signal, S30 timing signal, S40 detection end signal, S45 determination signal, TP test pattern, V _DD
…Power-supply voltage.

Claims (10)

[Claims] A power supply circuit for supplying power to the CMOS integrated circuit; an application circuit for applying a test signal to the CMOS integrated circuit; and a plurality of static power supply currents supplied from the power supply circuit to the CMOS integrated circuit. A measuring circuit for measuring at a measuring point; comparing each measured value of the static power supply current with a set value to detect normality / abnormality of each measured value; A test circuit for judging the integrated circuit as a non-defective product, and judging the CMOS integrated circuit as a defective product when the abnormality detection count is a positive value less than the reference count. 2. The test apparatus according to claim 1, wherein the reference number is equal to or less than the number of the measurement points and equal to or substantially equal to the number of the measurement points. 3. The test signal has a plurality of test patterns, and the application circuit switches the test patterns between adjacent ones of the plurality of measurement points.
Test apparatus as described. 4. The test apparatus according to claim 1, wherein the determination circuit detects that the measured value of the static power supply current is abnormal when the measured value is equal to or larger than the set value. 5. A test method for applying a test signal to a CMOS integrated circuit, measuring a static power supply current of the CMOS integrated circuit at a plurality of measurement points, and judging pass / fail of the CMOS integrated circuit based on the measurement result. Comparing each measured value of the static power supply current with a set value to detect normality / abnormality of each measured value; and determining that the CMOS integrated circuit is non-defective when the number of times of abnormality detection is equal to or more than a reference number. Judging, and judging the CMOS integrated circuit as a defective product when the abnormality detection count is a positive value less than a reference count. 6. The test method according to claim 5, wherein the reference number is equal to or less than the number of the measurement points and equal to or substantially equal to the number of the measurement points. 7. The test signal according to claim 5, wherein the test signal has a plurality of test patterns, and further comprising the step of switching the test patterns between adjacent ones of the plurality of measurement points. Test method. 8. The test method according to claim 5, wherein in the detecting step, when the measured value of the static power supply current is equal to or larger than the set value, the measured value is detected as abnormal. 9. The method according to claim 5, further comprising the step of accumulating the number of times of abnormality detection in the lot of the CMOS integrated circuit, and correcting the reference number of times based on the accumulated number of times of abnormality detection.
Test method described. 10. A step of creating a failure model of the CMOS integrated circuit, wherein the step of applying the test signal to the failure model of the CMOS integrated circuit and measuring the static power supply current at the plurality of measurement points. The test method according to claim 5, further comprising: a step of predicting the number of times of abnormality detection; and a step of determining the reference number of times based on the predicted number of times of abnormality detection.