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JP2001068514A - Dummy chip with bump and method of evaluating flip-chip packaging - Google Patents

Dummy chip with bump and method of evaluating flip-chip packaging

Info

Publication number
JP2001068514A
JP2001068514A JP24226399A JP24226399A JP2001068514A JP 2001068514 A JP2001068514 A JP 2001068514A JP 24226399 A JP24226399 A JP 24226399A JP 24226399 A JP24226399 A JP 24226399A JP 2001068514 A JP2001068514 A JP 2001068514A
Authority
JP
Japan
Prior art keywords
chip
bumps
flip
dummy
lsi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24226399A
Other languages
Japanese (ja)
Other versions
JP3711801B2 (en
Inventor
Shigeaki Koyama
茂昭 小山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP24226399A priority Critical patent/JP3711801B2/en
Publication of JP2001068514A publication Critical patent/JP2001068514A/en
Application granted granted Critical
Publication of JP3711801B2 publication Critical patent/JP3711801B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【課題】 フリップチップ実装工程の評価を簡易な手法
で且つ短時間に行えるようにする。 【解決手段】 バンプ付きLSIチップを配線基板にフ
リップチップ実装する工程を評価する際、透明ガラスか
らなり且つ寸法形状が製品のLSIチップと同じダミー
チップ1の片面に製品のバンプと同じバンプ4が製品の
バンプ付きLSIチップと同じ配列で且つ同じバンプ下
地金属膜2を介して形成されたバンプ付きダミーチップ
を使用してフリップチップ実装のトライアルを行い、ト
ライアル品のボンディング部分とその周辺をダミーチッ
プ1を透して目視により観察することで、ボンディング
位置精度、バンプ接続形状等をチェックする。
(57) [Summary] [PROBLEMS] To evaluate a flip chip mounting process by a simple method and in a short time. SOLUTION: When evaluating a process of flip-chip mounting an LSI chip with bumps on a wiring board, bumps 4 which are the same as the bumps of the product are formed on one side of a dummy chip 1 which is made of transparent glass and has the same dimensions and shape as the LSI chip of the product. A flip chip mounting trial is performed using a dummy chip with bumps formed in the same arrangement as the LSI chip with bumps of the product via the same bump base metal film 2, and the bonding portion of the trial product and its surroundings are dummy chips. By visually observing through 1, bonding position accuracy, bump connection shape, and the like are checked.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、バンプ付きLSI
チップを配線基板にフリップチップ実装する工程を評価
するためのバンプ付きダミーチップ及びそれを用いたフ
リップチップ実装評価方法に関する。
The present invention relates to a bumped LSI.
The present invention relates to a dummy chip with bumps for evaluating a step of flip-chip mounting a chip on a wiring board, and a flip-chip mounting evaluation method using the same.

【0002】[0002]

【従来の技術】バンプ付きLSIチップを配線基板にフ
リップチップ実装する工程(フリップチップ・ボンディ
ングの他、洗浄,アンダーフィルを含む)を立ち上げる
際、或いは、フリップチップ実装すべきバンプ付きLS
Iチップが、チップサイズ,バンプ数,バンプ配置,バ
ンプ材料,バンプ寸法等が異なる別の品種に切り換わる
際には、バンプ付きダミーチップを配線基板にフリップ
チップ実装し(即ち、トライアルを行い)、そのトライ
アル品の品質をチェックすることで工程を評価し、その
結果に応じて処理装置の微調整や処理条件の最適化を図
る必要がある。その代表的な品質チェック項目は、ボン
ディング位置精度、バンプの接続形状、アンダーフィル
樹脂充填不完全、フラックス洗浄不完全等である。
2. Description of the Related Art When starting a step of mounting an LSI chip with bumps on a wiring board by flip chip bonding (including cleaning and underfill in addition to flip chip bonding), or an LSI with bumps to be flip chip mounted
When the I-chip is switched to another type having different chip size, number of bumps, bump arrangement, bump material, bump dimensions, etc., a dummy chip with bumps is flip-chip mounted on a wiring board (ie, a trial is performed). It is necessary to evaluate the process by checking the quality of the trial product, and to fine-tune the processing apparatus and optimize the processing conditions according to the result. Typical quality check items are bonding position accuracy, bump connection shape, incomplete filling of underfill resin, incomplete flux cleaning, and the like.

【0003】従来、このフリップチップ実装工程評価の
ためのトライアルには、バンプ付きダミーチップとして
フリップチップ実装すべき製品のバンプ付きLSIチッ
プを用いており、そして上記項目の品質チェックをX線
透視,超音波探傷,断面研磨等の方法で行っていた。
Conventionally, in a trial for evaluating the flip-chip mounting process, an LSI chip with bumps of a product to be flip-chip mounted is used as a dummy chip with bumps. Ultrasonic flaw detection, cross section polishing, etc. were used.

【0004】[0004]

【発明が解決しようとする課題】ところが、このX線透
視,超音波探傷,断面研磨等は簡易な作業ではなく、従
って、従来技術ではフリップチップ実装工程の評価に長
時間を要する、という問題があった。
However, X-ray fluoroscopy, ultrasonic inspection, cross-section polishing, and the like are not simple tasks, and the conventional technique requires a long time to evaluate the flip-chip mounting process. there were.

【0005】本発明は、このような問題を解決して、ト
ライアル品の品質チェックが簡便な手法で且つ短時間に
行えるバンプ付きダミーチップ及びフリップチップ実装
評価方法を提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for evaluating the mounting of a dummy chip with bumps and a flip chip, which can solve such a problem and can check the quality of a trial product in a simple manner and in a short time.

【0006】[0006]

【課題を解決するための手段】この目的を達成するた
め、本発明においては、LSIチップの一面にバンプが
配設されてなるバンプ付きLSIチップを配線基板にフ
リップチップ実装する工程を評価するためのバンプ付き
ダミーチップであって、透明ガラスからなり且つ寸法形
状が該LSIチップと同一であるダミーチップの一面
に、該バンプ付きLSIチップのバンプと同一のバンプ
が該バンプ付きLSIチップと同一の配列で且つ該バン
プ付きLSIチップと同一のバンプ下地金属膜を介して
配設されてなることを特徴とするバンプ付きダミーチッ
プとしている。
In order to achieve this object, the present invention provides a method for evaluating a process of flip-chip mounting a bumped LSI chip having bumps on one surface of an LSI chip on a wiring board. A dummy chip made of transparent glass and having the same dimensions and shape as the LSI chip is provided on one surface of the dummy chip with the same bumps as the bumps of the LSI chip with bumps. A dummy chip with bumps, which is arranged and arranged via the same bump base metal film as the LSI chip with bumps.

【0007】また、本発明においては、前記のバンプ付
きダミーチップを配線基板にフリップチップ・ボンディ
ングした後、該ダミーチップを透してボンディング品質
をチェックすることを特徴とするフリップチップ実装評
価方法としている。
In the present invention, a flip chip mounting evaluation method is characterized in that after bonding the dummy chip with bumps on a wiring board by flip chip bonding, the bonding quality is checked through the dummy chip. I have.

【0008】また、本発明においては、前記のバンプ付
きダミーチップを配線基板にフリップチップ・ボンディ
ングし、さらに該ダミーチップと該配線基板との間隙に
樹脂を充填した後、樹脂充填状況を該ダミーチップを透
してチェックすることを特徴とするフリップチップ実装
評価方法としている。
In the present invention, the dummy chip with bumps is flip-chip bonded to a wiring board, and a resin is filled in a gap between the dummy chip and the wiring board. The flip chip mounting evaluation method is characterized by checking through a chip.

【0009】即ち、本発明においては、ダミーチップが
透明ガラスであるから、面倒なX線透視,超音波探傷,
断面研磨等を行うことなく、非破壊でダミーチップを透
して目視によりボンディング位置精度,バンプの接続形
状,アンダーフィル樹脂の充填状況等を観察することが
できる。一方、ガラスは熱膨張率がLSIチップを構成
するSiに近く、またLSIチップと同じ下地金属膜を
形成することも可能である。従って、チップの寸法形
状,バンプ,下地金属等をフリップチップ実装すべき製
品に合わせておけば、透明ガラスのダミーチップを使用
したトライアルの結果によりフリップチップ実装工程の
評価が容易に且つ短時間にできる。
That is, in the present invention, since the dummy chip is made of transparent glass, it is troublesome to perform X-ray fluoroscopy, ultrasonic inspection,
The bonding position accuracy, the connection shape of the bumps, the filling state of the underfill resin, and the like can be visually observed through a dummy chip in a non-destructive manner without performing cross section polishing or the like. On the other hand, glass has a coefficient of thermal expansion close to that of Si constituting an LSI chip, and it is possible to form the same underlying metal film as the LSI chip. Therefore, if the chip dimensions, bumps, base metal, etc. are matched to the product to be flip-chip mounted, evaluation of the flip-chip mounting process can be performed easily and in a short time based on the results of trial using dummy chips made of transparent glass. it can.

【0010】[0010]

【発明の実施の形態】以下、本発明の実施の形態を図1
を参照しながら説明する。図1は本発明の実施形態を示
す模式断面図である。同図において、1はダミーチッ
プ、2はUBM(バンプ下地金属膜)、3はバンプ、4
は表面保護膜である。
FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIG. FIG. 1 is a schematic sectional view showing an embodiment of the present invention. In the figure, 1 is a dummy chip, 2 is a UBM (metal substrate under bump), 3 is a bump, 4
Is a surface protective film.

【0011】ダミーチップ1は材質が透明ガラスであ
り、その寸法形状はフリップチップ実装すべき製品のL
SIチップと同じである。UBM2は板状のダミーチッ
プ1の片面に製品のLSIチップと同じ配列で形成され
ており、その材質(例えばTi/Ni)・寸法形状も製
品のLSIチップと同じである。バンプ3は製品のバン
プ付きLSIチップのバンプと同じであり(材質は半
田,Au,Sn−Ag等)、これが製品のバンプ付きL
SIチップと同じ数量,同じ配列で、ダミーチップ1の
片面にUBM2を介して形成されている。更に、ダミー
チップ1のバンプ3形成面の露出部分には、製品のLS
Iチップと同一の表面保護膜4が被着されている(例え
ば窒化膜,ポリイミド膜)。
The material of the dummy chip 1 is transparent glass, and its dimensions and shapes are the same as those of the product to be flip-chip mounted.
Same as the SI chip. The UBM 2 is formed on one side of the plate-shaped dummy chip 1 in the same arrangement as the product LSI chip, and its material (for example, Ti / Ni) and dimensions are the same as those of the product LSI chip. The bump 3 is the same as the bump of the bumped LSI chip of the product (the material is solder, Au, Sn-Ag, etc.).
The same number and the same arrangement as the SI chips are formed on one surface of the dummy chip 1 via the UBM 2. Further, the LS of the product is placed on the exposed portion of the dummy chip 1 where the bump 3 is formed.
The same surface protection film 4 as the I chip is applied (for example, a nitride film, a polyimide film).

【0012】このバンプ付きダミーチップは、次のよう
にして作ることができる。先ず、ウェーハ形状のガラス
板の片面に、UBMとなる金属膜(例えばTi/Ni)
をスパッタ法で被着する。次に、この金属膜上にレジス
ト膜を形成し、このレジスト膜をパターニングする。次
にこの金属膜をめっき導通膜としてめっき法で半田,A
u,Sn−Ag等のバンプを形成する。次に、このバン
プをマスクとして金属膜をエッチングし、その後、この
バンプ付きガラス・ウェーハをダイシングして、バンプ
付きダミーチップとする。
The dummy chip with bumps can be manufactured as follows. First, a metal film (for example, Ti / Ni) serving as a UBM is formed on one surface of a wafer-shaped glass plate.
Is deposited by a sputtering method. Next, a resist film is formed on the metal film, and the resist film is patterned. Next, this metal film is used as a plating conductive film by soldering using a plating method, A
A bump such as u, Sn-Ag is formed. Next, the metal film is etched using the bumps as a mask, and thereafter, the glass wafer with the bumps is diced into dummy chips with bumps.

【0013】尚、表面保護膜の被着やバンプのリフロー
が必要な場合には、ダイシング工程の前に行う。また、
バンプ形成方法としては前述のめっき法の他に、印刷
法,転写法,メタルジェット法,スタッドバンプ法等が
ある。
If it is necessary to apply a surface protective film or reflow bumps, the process is performed before the dicing step. Also,
As the bump forming method, there are a printing method, a transfer method, a metal jet method, a stud bump method and the like in addition to the plating method described above.

【0014】次に、本発明のフリップチップ実装工程の
評価方法を説明する。先ず、前記のバンプ付きダミーチ
ップを配線基板にフリップチップ・ボンディングした
後、前記ダミーチップを透してのボンディング部分の目
視観察により、ボンディング位置精度,バンプ接続形状
等のボンディング品質をチェックし、その結果に基づい
てフリップチップ・ボンディング工程を評価する。
Next, a method for evaluating the flip-chip mounting process of the present invention will be described. First, after the dummy chip with bumps is flip-chip bonded to a wiring board, bonding quality such as bonding position accuracy and bump connection shape is checked by visual observation of a bonding portion through the dummy chip. The flip chip bonding process is evaluated based on the result.

【0015】また、フリップチップ・ボンディング後に
洗浄を行い、その後、前記ダミーチップを透してボンデ
ィング部分やその周辺を目視観察して、残留するフラッ
クスの有無等の洗浄品質をチェックし、その結果により
洗浄工程を評価する。
After the flip chip bonding, cleaning is performed. Thereafter, the bonding portion and its surroundings are visually observed through the dummy chip to check the cleaning quality such as the presence of residual flux. Evaluate the washing process.

【0016】また、フリップチップ・ボンディング後の
ダミーチップと配線基板との間隙に樹脂を充填し、前記
ダミーチップを透して樹脂充填部を目視観察して、ボイ
ド等の充填欠陥をチェックし、その結果によりアンダー
フィル工程を評価する。尚、樹脂充填時に樹脂の挙動を
ダミーチップを透して観察することもできる。従って、
樹脂の挙動も観察することにより、アンダーフィル工程
の評価をより的確に行うことができる上、樹脂そのもの
の評価や実装部材のデザインを評価することも可能であ
る。
The gap between the dummy chip and the wiring board after the flip chip bonding is filled with resin, and the resin filling portion is visually observed through the dummy chip to check for filling defects such as voids. The underfill process is evaluated based on the result. Incidentally, the behavior of the resin at the time of filling the resin can be observed through a dummy chip. Therefore,
By observing the behavior of the resin, it is possible to more accurately evaluate the underfill step, and also to evaluate the resin itself and the design of the mounting member.

【0017】本発明は以上の例に限定されることなく、
更に種々変形して実施することができる。
The present invention is not limited to the above examples,
Further, various modifications can be made.

【0018】[0018]

【発明の効果】以上説明したように、本発明によれば、
フリップチップ実装工程の評価が簡便な手法で且つ短時
間に行えるバンプ付きダミーチップ及びフリップチップ
実装評価方法を提供することができる。
As described above, according to the present invention,
It is possible to provide a dummy chip with bumps and a flip chip mounting evaluation method that can evaluate the flip chip mounting process in a simple manner and in a short time.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の実施形態を示す模式断面図である。FIG. 1 is a schematic sectional view showing an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 ダミーチップ 2 UBM(バンプ下地金属膜) 3 バンプ 4 表面保護膜 DESCRIPTION OF SYMBOLS 1 Dummy chip 2 UBM (under bump metal film) 3 Bump 4 Surface protective film

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 LSIチップの一面にバンプが配設され
てなるバンプ付きLSIチップを配線基板にフリップチ
ップ実装する工程を評価するためのバンプ付きダミーチ
ップであって、 透明ガラスからなり且つ寸法形状が該LSIチップと同
一であるダミーチップの一面に、該バンプ付きLSIチ
ップのバンプと同一のバンプが該バンプ付きLSIチッ
プと同一の配列で且つ該バンプ付きLSIチップと同一
のバンプ下地金属膜を介して配設されてなることを特徴
とするバンプ付きダミーチップ。
1. A dummy chip with bumps for evaluating a step of flip-chip mounting an LSI chip with bumps on one surface of an LSI chip on a wiring board, the dummy chip being made of transparent glass and having a dimensional shape. Is provided on one surface of a dummy chip which is the same as the LSI chip, a bump base metal film having the same arrangement as the bumps of the bumped LSI chip and having the same arrangement as the bumped LSI chip, and the same as the bumped LSI chip. A dummy chip with bumps, wherein the dummy chip has bumps.
【請求項2】 請求項1記載のバンプ付きダミーチップ
を配線基板にフリップチップ・ボンディングした後、該
ダミーチップを透してボンディング品質をチェックする
ことを特徴とするフリップチップ実装評価方法。
2. A flip-chip mounting evaluation method, comprising: after flip-chip bonding the dummy chip with bumps according to claim 1 to a wiring board, checking bonding quality through the dummy chip.
【請求項3】 請求項1記載のバンプ付きダミーチップ
を配線基板にフリップチップ・ボンディングし、さらに
該ダミーチップと該配線基板との間隙に樹脂を充填した
後、樹脂充填状況を該ダミーチップを透してチェックす
ることを特徴とするフリップチップ実装評価方法。
3. The method according to claim 1, wherein the dummy chip with bumps is flip-chip bonded to a wiring board, and a resin is filled in a gap between the dummy chip and the wiring board. A flip-chip mounting evaluation method characterized by checking through.
JP24226399A 1999-08-27 1999-08-27 Bumped dummy chip and flip chip mounting evaluation method Expired - Fee Related JP3711801B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24226399A JP3711801B2 (en) 1999-08-27 1999-08-27 Bumped dummy chip and flip chip mounting evaluation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24226399A JP3711801B2 (en) 1999-08-27 1999-08-27 Bumped dummy chip and flip chip mounting evaluation method

Publications (2)

Publication Number Publication Date
JP2001068514A true JP2001068514A (en) 2001-03-16
JP3711801B2 JP3711801B2 (en) 2005-11-02

Family

ID=17086673

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24226399A Expired - Fee Related JP3711801B2 (en) 1999-08-27 1999-08-27 Bumped dummy chip and flip chip mounting evaluation method

Country Status (1)

Country Link
JP (1) JP3711801B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008140890A (en) * 2006-11-30 2008-06-19 Fujitsu Ltd Component assembly state observation apparatus and component assembly state observation method using the same
JP2008198710A (en) * 2007-02-09 2008-08-28 Fujitsu Ltd Observation device and method for manufacturing electronic device
JP2014183140A (en) * 2013-03-19 2014-09-29 Apic Yamada Corp Dummy chip, dummy substrate, dummy frame, manufacturing method of dummy frame, resin fluidity evaluation method, and resin mold method
US20220377882A1 (en) * 2021-05-20 2022-11-24 Honeywell Federal Manufacturing & Technologies, Llc Transparent package for use with printed circuit boards

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008140890A (en) * 2006-11-30 2008-06-19 Fujitsu Ltd Component assembly state observation apparatus and component assembly state observation method using the same
JP2008198710A (en) * 2007-02-09 2008-08-28 Fujitsu Ltd Observation device and method for manufacturing electronic device
JP2014183140A (en) * 2013-03-19 2014-09-29 Apic Yamada Corp Dummy chip, dummy substrate, dummy frame, manufacturing method of dummy frame, resin fluidity evaluation method, and resin mold method
US20220377882A1 (en) * 2021-05-20 2022-11-24 Honeywell Federal Manufacturing & Technologies, Llc Transparent package for use with printed circuit boards

Also Published As

Publication number Publication date
JP3711801B2 (en) 2005-11-02

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