JP2001052599A - Manufacturing method and structure of cold cathode array device and cold cathode array imaging device - Google Patents

Abstract

(57) Abstract: A method of manufacturing a cold cathode array element in which a cold cathode array that emits an electron beam and a drive control circuit that controls the driving of the cold cathode array are integrated on the same substrate and manufactured. A structure and a cold cathode array imaging device are provided. A driving control circuit includes a step of forming a cold cathode array for emitting an electron beam on the same required conductivity type semiconductor substrate, and a region selection circuit and a level conversion circuit for controlling the driving of the cold cathode array. And a step of connecting the cold cathode array formed in each step and the drive control circuit to manufacture a cold cathode array element constituted by the cold cathode array and the drive control circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cold cathode array integrally formed with a cold cathode array for emitting an electron beam and a drive control circuit for driving and controlling the emission of the electron beam from the cold cathode array in a required scanning order. Manufacturing method and structure of array element,
Further, the present invention relates to a cold cathode array imaging device including a cold cathode array element and a photoelectric conversion target for converting incident light from a subject into a video signal.

[0002]

2. Description of the Related Art Conventionally used image pickup devices for emitting an electron beam to a photoelectric conversion target include an image pickup tube (Image Pickup Tube) such as a vidicon tube, a plumbicon tube, and a saticon tube. It was frequently used for equipment. However, these image pickup tubes (FIG. 1)
7 shows an example of an image pickup tube).
There is a cathode for emitting an electron beam 173 to 71 (for example, a transparent electrode and a photoconductive film are provided on a glass face plate), and an electron gun portion 172 including a heater for heating the cathode. Further, since it is necessary to deflect the single electron beam 173 emitted from the electron gun portion 172 in a required direction, a deflection portion having a required length in a direction perpendicular to the tube surface is required, and the electron beam is deflected in a required direction. In addition to the deflecting device (not shown), the television camera device requires a considerable volume. In the current television camera device, a solid-state image pickup device is used as an image pickup device in which an electron gun portion which emits an electron beam by incorporating such a heater and the like and a deflection portion having a required length in a direction perpendicular to the tube surface are eliminated. , For example, C
CDs (Charge Transfer Type Imaging Devices) are used, and applications and quantities are increasing. However, this solid-state imaging device also has some disadvantages depending on the purpose of use, for example, a problem that the sensitivity is insufficient in imaging when it cannot be illuminated brightly, and an imaging tube is still used for such imaging. Have been.

[0003] In recent years, as an alternative to an image pickup tube combining a conventional photoelectric conversion target and an electron gun having a built-in heater for heating a cathode for emitting an electron beam, a photoelectric conversion target for an image pickup tube, For example, a photoconductive film target and a cold cathode array (also referred to as a field emitter array: FEA: Field Emitter Array) having a plurality of cold cathodes for emitting an electron beam are opposed to each other. Of 1
A cold cathode array imaging device (field emission imaging device: FEP: Field) in which an electron beam is emitted from a cold cathode in a required scanning order corresponding to each pixel to extract a video signal current from an opposing photoconductive film target. Emissi
on Pickup Tube) is being studied as a solution to the problem of CCD. The cold-cathode array imaging device has a photoelectric conversion target and a cold-cathode array facing each other, and presses the glass envelope and the glass face plate portion of the photoelectric conversion target through metal indium, similarly to a conventional imaging tube. It is sealed and generally has the shape of an imaging tube that is extremely short in length compared to conventional imaging tubes.

FIG. 16 is a partial cross-sectional view of a cold cathode array for emitting an electron beam. The structure of a conventional cold cathode array for emitting an electron beam from a cold cathode and a method of driving the cold cathode array will be described. . In FIG. 16, reference numeral 161 denotes a cold cathode array substrate; 162, a cathode electrode for emitting electrons formed on the substrate 161; 164, a gate electrode for controlling electron emission from the cathode electrode 162;
Reference numeral 3 denotes an insulating layer formed between the cathode electrode 162 and the gate electrode 164, and reference numeral 165 denotes a cathode for emitting a beam of electrons which is formed between the gate electrodes 164 by sharpening a part of the cathode electrode 162. (Cold cathode) 166 denotes an opening formed in the gate electrode. The cold cathode array includes a cathode electrode 162, a gate electrode 164, and a cathode 16
5, a plurality of power supplies connected to the respective rows and columns of the cathode electrode 162 and the gate electrode 164,
A voltage is applied from a so-called drive voltage generation circuit. When the potential of the gate electrode 164 reaches a predetermined value with respect to the cathode electrode 162, an electric field concentrates on the tip of the cathode 165 where a part of the cathode electrode 162 is sharpened. An electron beam is emitted from the
Such a device that emits electrons without being heated by a heater or the like is called a cold cathode.

[0005] Such a cold cathode array in which a plurality of cathode electrodes, gate electrodes, and cold cathodes are arranged in an array is used when the voltage E between the cathode electrode 162 and the gate electrode 164 is higher than a predetermined voltage. An electron beam is emitted from the cold cathode 165, and when the voltage is lower than a predetermined voltage, the emission of the electron beam stops. Therefore, by changing the voltage E between the cathode electrode 162 and the gate electrode 164, the cold cathode 165 emits an electron beam. Emission of the electron beam can be controlled. Conventionally, such ON / OFF control of the electron beam and control of the emission amount in a partial region of the cold cathode array are performed as follows. A region where each row or each column of the gate electrode and each column or each row of the cathode electrode intersects as one region, and a row including a cold cathode gate electrode in a region selected to emit an electron beam,
Alternatively, a column is provided with a required voltage for obtaining a required amount of electron beam, a row where the cold cathode gate electrode of the selected region is not included, or 0 V is applied to the column, and a cold cathode of the selected region is applied. The column or row containing the cathode electrode has 0
V. A voltage equivalent to the required voltage is applied to a column or a row that does not include the cold cathode electrode in the selected region. As a result, the voltage between the cathode electrode and the gate electrode of the cold cathode in the selected region becomes a required voltage, and a required amount of electron beam can be emitted. The cold cathodes in the other regions have the gate electrode at a negative potential or the same potential as the cathode electrode, and do not emit an electron beam. As described above, a drive control circuit is used to control the application of a voltage to each row and each column, and this drive control circuit needs to have a withstand voltage of at least the required voltage. In order to minimize the required voltage, that is, the voltage for obtaining the required amount of emitted electron beam, the tip of the cathode 165 is sharpened as much as possible to increase the concentration of the electric field, or the diameter of the opening 166 is reduced. It is effective to minimize the distance between the tip of the cathode 165 and the gate electrode 164. In recent years, this cold cathode array also has a voltage between the cathode electrode 162 and the gate electrode 164 due to the development of a technology for forming a cold cathode having a sharper tip and a gate opening technology for generating a gate electrode having a minute opening. Is 8
Although it has become possible to emit a required amount of electron beam even at a voltage as low as about 0 volt, even at such a voltage, a drive control circuit including a level conversion circuit having a withstand voltage can be densely arranged in a small area. It is difficult to make.

An image sensor having the above-described structure, in which a cold cathode array for emitting an electron beam and a photoelectric conversion target for an image pickup tube is combined, requires an image sensor corresponding to each pixel of the opposing photoelectric conversion target. In order to emit the electron beam from the cold cathode in the scanning order, a region selection circuit for selecting an electron beam emission region of the cold cathode array and a power supply for supplying a high voltage to the cold cathode array are required. A video signal output circuit for extracting a video signal current from the target and outputting a video signal is required.

[0007]

An image pickup device combining a cold cathode array for emitting an electron beam and a photoelectric conversion target for an image pickup tube according to the prior art is provided with an external drive control circuit for controlling the drive of the cold cathode array. Therefore, the connection between the cold cathode array and the drive control circuit and the arrangement of the drive control circuit are very troublesome. The present invention solves the above-mentioned problems, and manufactures a cold-cathode array element in which a cold-cathode array that emits an electron beam and a drive control circuit that performs drive control of the cold-cathode array are integrated and manufactured on the same substrate. It is an object to provide a method and structure and a cold cathode array imaging device.

[0008]

In order to achieve the above object, a method of manufacturing a cold cathode array according to the present invention comprises the steps of forming a cold cathode array for emitting an electron beam on the same required conductivity type semiconductor substrate. Forming a drive control circuit including a region selection circuit for selecting an electron beam emission region of the cold cathode array and a level conversion circuit for generating a voltage for controlling electron beam emission; and A method of manufacturing a cold cathode array element including the cold cathode array and the drive control circuit by a step of connecting the formed cold cathode array and the drive control circuit. Also,
In the method of manufacturing a cold cathode array according to the present invention, a cold cathode array region for emitting an electron beam is formed on the same required conductivity type semiconductor substrate, and then an area for selecting an electron beam emitting region of the cold cathode array is formed. Forming a drive control circuit composed of a selection circuit and a level conversion circuit for generating a voltage for controlling electron beam emission, and then connecting the cold cathode array and the drive control circuit, And a method for manufacturing a cold cathode array element comprising the drive control circuit. The method for manufacturing a cold cathode array according to the present invention may further comprise a region selection circuit for selecting an electron beam emission region of the cold cathode array for emitting an electron beam on the same required conductivity type semiconductor substrate, and a voltage for controlling the electron beam emission. And a level control circuit for generating a drive control circuit.
The cold cathode array region is formed, and then, the cold cathode array is connected to the drive control circuit to manufacture a cold cathode array element including the cold cathode array and the drive control circuit.

Further, according to a method of manufacturing a cold cathode array of the present invention, a polycrystalline semiconductor layer is formed on the same required conductivity type semiconductor substrate via an insulating film, and the polycrystalline semiconductor layer is formed using an etching mask material. After selectively etching the crystalline semiconductor layer, the mask material is removed, and the polycrystalline semiconductor layer is ion-implanted into a mask, or a diffusion region of the other conductive type impurity is formed on the required conductive type semiconductor substrate by thermal diffusion. Forming a metal layer on the diffusion region and the required conductivity type semiconductor substrate after selectively removing the mask material by selectively etching the insulating film on the diffusion region using an etching mask material. Selectively etching the metal layer using an etching mask material, removing the mask material, and forming an electrode including a wiring pattern of the metal layer on the diffusion region. Forming a second metal layer on the required conductive type semiconductor substrate via the insulating film; and forming a third metal layer on the required conductive type semiconductor substrate via the second insulating film. Forming a metal layer, and selectively etching the third metal layer using a mask material for etching to remove the mask material; and then removing the second insulating film using the third metal layer as a mask. Selectively etching;
Continuously forming one or more metal layers including the fourth metal layer on the selectively etched third metal layer on the required conductivity type semiconductor substrate. The method for manufacturing a cold cathode array according to the present invention further comprises a step of forming a polycrystalline semiconductor layer on the same required conductivity type semiconductor substrate via an insulating film, and the step of forming the polycrystalline semiconductor layer by using an etching mask material. Removing the mask material after selective etching, ion-implanting the polycrystalline semiconductor layer into a mask, or forming a diffusion region of the other conductivity type impurity on the required conductivity type semiconductor substrate by thermal diffusion. ,
Forming a metal layer on the diffusion region and the required conductivity type semiconductor substrate after selectively removing the mask material by selectively etching the insulating film on the diffusion region using an etching mask material; Selectively etching the layer using an etching mask material, removing the mask material and forming an electrode including a wiring pattern of the metal layer on the diffusion region; and Forming a second metal layer via the insulating film;
Forming a third metal layer on the required conductivity type semiconductor substrate via a second insulating film; and selectively etching the third metal layer to emit an electron beam from at least a required region of the cold cathode. Forming an opening that constitutes an electrode structure for controlling the second metal layer, selectively etching the second insulating film using the third metal layer as a mask, and forming a hole on the selectively etched third metal layer. Forming a fourth metal layer to reduce the diameter of the opening formed in the third metal layer.

Further, an image pickup device using the cold cathode array element of the present invention includes an envelope in which a cold cathode array element in which a cold cathode array and a drive control circuit are integrally formed on the same substrate is incorporated. A photoelectric conversion target in which a transparent electrode and a photoconductive film are formed on a face plate is pressure-bonded via metal indium disposed in a sealing portion, and is hermetically sealed. More specifically, the imaging device using the cold cathode array device of the present invention is a device in which at least a part of the envelope and the face plate are made of glass, or
It is made of quartz.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an embodiment of a method and a structure for manufacturing a cold cathode array element according to the present invention will be described. One embodiment of a method and structure for manufacturing a cold cathode array element according to the present invention will be described with reference to FIGS. The cold cathode array element of the present invention is formed by integrally forming a cold cathode array and a drive control circuit for driving and controlling the cold cathode array. The drive control circuit includes a shift register circuit that outputs a signal voltage for sequentially scanning and selecting the electron beam emission area of the cold cathode array in a required order, and a signal voltage output from the shift register circuit. Is converted to a required voltage for obtaining a required emission current, and is applied to a cathode electrode and a gate electrode.
The cold cathode array element is formed, for example, on a silicon substrate. The cold cathode array element includes a cold cathode array area and a CMOS logic circuit area that forms a drive control circuit (area selection circuit and level conversion circuit). Further, it is composed of a PMOS transistor region and an NMOS transistor region. 1 (a) to 6 (r)
Represents P of the CMOS logic circuit constituting the drive control circuit.
4 shows a step of forming a MOS transistor and an NMOS transistor. PMOS transistor and N
The MOS transistor is formed by first forming a silicon oxide film 2 having a thickness of about 500 ° on a semiconductor N-type silicon substrate 1 by thermal oxidation at about 1000 ° C. or by chemical vapor deposition. Further, on the silicon oxide film 2, a silicon nitride film 3 as a thermal oxidation prevention film is formed to a thickness of about 1000 ° by a chemical vapor deposition method. (FIG. 1 (a)
reference)

Next, the PM of the CMOS logic circuit area is
In the steps described below, a PMOS transistor and an NMOS transistor are formed in the OS transistor region and the NMOS transistor region. First, a photoresist is applied on the silicon nitride film 3, and the silicon nitride film 3 in the PMOS transistor region is removed by photoetching. (Specifically, in the photoetching, a photoresist is applied on the silicon nitride film 3, a required pattern is exposed on the photoresist, and a developing process is performed to form a patterned photoresist. Using this photoresist as a mask, the photoresist and the silicon nitride film 3 are etched by a dry etching method or a wet etching method, and PM
The photoresist and the silicon nitride film 3 in the OS transistor region are removed, and the photoresist 91 and the silicon nitride film 31 patterned in the NMOS transistor region are formed. This is a general manufacturing technique. Will be described, but detailed description is omitted. Next, using the photoresist 91 and the silicon nitride film 31 remaining in the NMOS transistor region as a mask, ion implantation I1 of phosphorus or arsenic is performed in the PMOS transistor region. This ion implantation I
For example, in the case of ion implantation of phosphorus (P +), the conditions 1 are 125 keV and 2.0 × 10 ¹² cm ^{2 2} . (See FIG. 1 (b))

Next, the photoresist 91 remaining in the NMOS transistor region is removed, and thermal oxidation is performed.
A silicon oxide film 21 having a thickness of about 1500 ° is formed in the MOS transistor region. (Refer to FIG. 1C.) Further, the silicon nitride film 31 remaining in the NMOS transistor region is removed, and the remaining silicon oxide film 21 is used as a mask, and boron (BF ₂ +) is applied to 60 keV, 2.0 ×
10 ¹² cm ~ performing ion implantation I2 in ² conditions.
Next, phosphorus or arsenic (shown by a dotted line below the silicon oxide film 21 in FIG. 2D) subjected to the ion implantation I1 and I2 by performing thermal diffusion, and Boron (shown by a dotted line below the silicon oxide film 2 in FIG. 2D) is diffused to form an NWell diffusion layer 4 in the PMOS transistor region and a PWell diffusion layer 5 in the NMOS transistor region. The diffusion layers of the NWell diffusion layer 4 and the PWell diffusion layer 5 have a depth of 3 to 4 pm. (See FIG. 2E.) Next, a silicon nitride film 32 is formed on the silicon oxide films 2 and 21 to a thickness of about 1500 ° by a chemical vapor deposition method. (See FIG. 2 (f))

Next, a photoresist is applied on the silicon nitride film 32, and a photo-etching of a required pattern for forming a MOS transistor region is performed. The photoresist 92 and the silicon nitride film 321 are left as a mask, and boron (BF) is used. ₂ +) of 60ke the ion implantation I3
V, 2.0 × 10 ¹³ cm- ² . (FIG. 3
(Refer to FIG. 3 (g).) Then, after removing the remaining photoresist 92, thermal oxidation is performed to form a silicon oxide film 22 having a thickness of about 8000 to 10000 °, and boron ion-implanted I3 (FIG. g), which is indicated by a dotted line below the silicon oxide film 2), to form an NF diffusion layer 51 having a depth of about 1 μm which is necessary for a channel stopper. (See FIG. 3H) Next, the silicon nitride film 321 is removed. Further, after removing the silicon oxide films 2 and 21, thermal oxidation,
Alternatively, a silicon oxide film 2 ′ having a thickness of about 500 ° is formed again by a chemical vapor deposition method. (See FIG. 3 (i))

Subsequently, the ion implantation I4 of boron (B +) for adjusting the threshold voltage of the MOS transistor is set to 3
Under the conditions of 0 keV and 6.0 × 10 ¹¹ cm ² , the process is performed only in the MOS transistor region using the silicon oxide film 22 as a mask. Then, a polycrystalline silicon film 10 having a thickness of about 3500 ° is formed on the silicon oxide films 2 ′ and 22 by a chemical vapor deposition method or a sputtering method. Furthermore, in order to reduce the resistance of the formed polycrystalline silicon film 10, a liquid diffusion source of phosphorus oxychloride (POC13) is bubbled with a nitrogen gas or the like using a thermal diffusion furnace, and the bubbled gas (atmosphere) is used. Is diffused in a furnace at a temperature of about 1000 ° C. This thermal diffusion lowers the resistance of the polycrystalline silicon film 10 to a sheet resistance of about several Ω. (See Fig. 4 (k))

Next, a photoresist is applied on the polycrystalline silicon film 10 and photoetching of a required pattern is performed to leave the photoresist 93 and the polycrystalline silicon film 101 serving as the gate electrode of the MOS transistor (FIG. 4 (l)).
And a polycrystalline silicon film 1 serving as a gate electrode.
After removing the photoresist 93 on the polysilicon film 01, thermal oxidation or chemical vapor deposition is performed to remove the polycrystalline silicon film 10.
A silicon oxide film 201 having a thickness of about 300.degree. (See FIG. 5 (m).) The electrode length of the polycrystalline silicon film 101 serving as the gate electrode is about several μm.

Subsequently, the silicon oxide films 22, 2 ', 2
01 in the PMOS transistor area above
A photoresist 94 is formed by pattern formation, and high-concentration ion implantation I5 of phosphorus or arsenic is performed using the silicon oxide film 22, the polycrystalline silicon film 101, and the photoresist 94 as a mask. For example, in the case of phosphorus (P +), 50 keV, and the implantation conditions 6.0 × 10 ¹⁴ cm ~ ^2. (Refer to FIG. 5 (n).) After the photoresist 94 is removed, a photoresist 95 is similarly formed in the NMOS transistor region by forming a photoresist pattern, and the silicon oxide film 22, the polycrystalline silicon film 101, and the photoresist 95 are used as masks. , Boron (B +) high-concentration ion implantation I6 at 80 keV,
2.5 × 10 ¹⁵ cm ~ carried out in ^two conditions. (Refer to FIG. 5 (o).) Further, after removing the photoresist 95, a heat annealing step is performed at about 900 ° C. to recover crystal defects after ion implantation, and the source and drain diffusion layers 6 of the PMOS transistor and the source of the NMOS transistor are removed. Then, a drain diffusion layer 7 is formed. (See FIG. 6 (p).) The depth of these diffusion layers is about 0.5 μm.

Next, the silicon oxide films 22, 2 ', 20
1 as an insulating film by chemical vapor deposition (PSG).
A pho Silicate Glass (phosphor glass) film or a silicon oxide film 25 is formed to a thickness of about 10,000 °.
(See FIG. 6 (q).) Further, the PSG film 25 is photo-etched to
A contact hole 210 of several μm square is formed for connecting the diffusion layer of each of the gate, source and drain of the OS transistor. Then, a conductive layer made of a metal such as Al (aluminum) or a material having high conductivity such as silicide is vacuum deposited. An Al electrode wiring 81 which also functions as a source electrode, a drain electrode and a gate electrode of a MOS transistor is formed by photolithography after forming the film to a thickness of about 10,000 ° by a sputtering method or a sputtering method. (Refer to FIG. 6 (r).) Through the above manufacturing steps, a CMOS logic circuit constituting the drive control circuit of the cold cathode array element is formed.

FIGS. 7A to 11L show the steps of forming a cold cathode array of a cold cathode array element. The cold cathode array is formed in the cold cathode array area adjacent to the CMOS logic circuit area constituting the drive control circuit whose formation has been described with reference to FIGS. (Refer to FIG. 7A.) The final PS used in forming the CMOS logic circuit area
The G film 25 is removed by photo-etching only in the region where the cold cathode array is formed. (See FIG. 7B.) Next, a photoresist pattern 96 for lift-off is formed to a thickness of about 1 μm on the entire surface of the CMOS logic circuit area by forming a photoresist pattern.
Alternatively, the metal layer 82 made of Cr (chromium), Mo (molybdenum), or a material having high conductivity is used for the cathode electrode of the cold cathode array by the sputtering method for about 1000 Å.
Formed to a thickness of (Refer to FIG. 7C.) Then, the photoresist 96 is lifted off, and the CM
Cr, Mo, or all over the OS logic circuit area
Removing the metal layer 82 of a material having high conductivity;
By subjecting the metal layer 82 to photolithography in a required pattern, a cathode electrode line 821 of a metal layer made of Cr, Mo, or a material having high conductivity is formed. (Refer to FIG. 8D.) Next, a silicon oxide film 23 is formed to a thickness of about 8000 ° by a chemical vapor deposition method or a sputtering method. (See FIG. 8 (e))

Subsequently, Cr, Mo, Cr and Mo are again deposited on the silicon oxide film 23 by a vacuum evaporation method or a sputtering method.
Alternatively, a metal layer made of a material having a high conductivity is formed by about 2000
Then, a metal layer 831 of a gate electrode having an opening 832 having a diameter of about 1 μm is formed by photoetching. (Refer to FIG. 8F.) Next, the silicon oxide film 23 is etched almost vertically and with good anisotropy by anisotropic dry etching such as reactive ion etching using the metal layer 831 as a mask as a mask. Then, wet etching is performed and isotropically (laterally) etched to form the silicon oxide film 2.
3, a hole 230 for forming a cathode electrode is formed. (FIG. 9
(Refer to (g)) Subsequently, the metal layer 84 made of Cr, Mo, or a highly conductive material having a thickness of about 2000 mm and the bottom surface portion 842 of the cathode electrode of the cold cathode array are again formed by a vacuum evaporation method or a sputtering method. To form At this time, the material is also deposited on the inner wall of the opening 832 of the gate layer 831. As a result, the size of the opening 832 is further reduced, and the size of the opening 832 is reduced to 0.6 to 0.3.
It becomes as small as 9 μm. (See FIG. 9 (h))

Further, a lift-off Al layer 85 is formed on the metal layer 84 made of Cr, Mo, or a material having a high conductivity by about 30 degrees by an oblique evaporation method at an angle of about 20 degrees.
It is formed to a thickness of 00 to 7000 mm. (See FIG. 10 (i).) This oblique evaporation method is a formation method for preventing Al to be evaporated from entering the cathode electrode forming hole 230. Vacuum evaporation method on the lift-off Al layer 85,
Alternatively, Mo, which has a high melting point and a high conductivity by a sputtering method,
Is formed to a thickness of about 10000. At the same time, a conical cathode electrode 862 is formed in the cathode electrode forming hole 230 by the metal layer 86 such as Mo. (See FIG. 10 (j).) Then, the Al layer 85 is wet-etched to perform lift-off, and the metal layer 86 such as Mo is removed.
(See FIG. 11 (k))

Subsequently, the metal layer 84 made of Cr, Mo or a material having high conductivity, and the metal layer 831 made of Cr, Mo or a material having a high conductivity as a gate layer are collectively photo-etched. , Metal layer 8
4, the gate electrode lines 841 and 8311 of the cold cathode array element selection wiring are formed. Further, a portion of the silicon oxide film 231 on the CMOS logic circuit region and the cathode electrode line 82 are
1 to remove the portion near the CMOS logic circuit area,
An electrode connection area 2310 is formed. (See FIG. 11 (l).) These electrode lines have, for example, a width of 8 μm and an interval of 2 μm.
m. Through the above manufacturing steps, a cold cathode array of the cold cathode array elements is formed.

[0023] For example, the 3
FIG. 12 shows a plan view (top view) of a cold cathode array element having × 3 cold cathode arrays and a drive control circuit constituted by a shift register circuit and a level conversion circuit which constitute an area selection circuit. A method for electrically connecting the drive control circuit and the cold cathode array by photoetching will be described. A cathode electrode line 821 of a metal layer made of Cr, Mo, or a highly conductive material of the cold cathode array, and a gate electrode 841 of a metal layer made of a material of Cr, Mo, or a highly conductive material are combined with components of a CMOS logic circuit. Is connected to the high voltage level conversion circuit LC, one circuit per line.

That is, one of the cathode electrode lines of the cold cathode array is connected to the level conversion circuit LC.
The photo-etching is performed between the wiring connection portion 812, which is a part of the electrode wiring on the cathode electrode line side, and the metal electrode cathode electrode line 821 of Cr, Mo, or a material having high conductivity in the cathode electrode line connection area 2310. A wiring 819 made of a material such as Al, Al or the like is formed and electrically connected. At the same time, the gate electrode line side is connected to the wiring connection portions 812 connected to the level conversion circuit LC and Cr,
A wiring 819 made of a material such as Al is formed between the gate electrode line 841 of the metal layer made of Mo or a material having high conductivity and electrically connected. Through the above manufacturing steps, a cold cathode array device according to the method for manufacturing a cold cathode array device of the present invention is completed. FIG.
It is sectional drawing of the -A line. In this embodiment, the method of electrically connecting the cold cathode array and the drive control circuit composed of the CMOS logic circuit in which the AL electrode wiring is formed by photoetching with the AL wiring formed by photoetching has been described. In the manufacturing process of the CMOS logic circuit portion, the formation of the AL electrode wiring is omitted, and in the photo etching process of forming the AL wiring for electrically connecting the cold cathode array and the drive control circuit including the CMOS logic circuit, the AL of the CMOS logic circuit is formed. The electrode wiring may be formed at the same time. Further, in this embodiment, the method of electrically connecting the drive control circuit and the cold cathode array by photoetching has been described. However, in addition to photoetching, connection by wire bonding or solder may be used.

FIG. 14 shows a cold cathode array according to the method of manufacturing a cold cathode array element of the present invention in which a cold cathode array and a drive control circuit for sequentially controlling the individual cold cathodes are integrally formed on one substrate. 1 shows a simplified overall view of the device. As shown in FIG. 14, the cold cathode array element 140 is
41 are integrally formed. The respective ends of the plurality of striped cathode electrodes 142 formed on the silicon substrate 141 are connected to the drive control circuit 148, and the respective ends of the plurality of striped gate electrodes 144 are connected to the drive control circuit 147. And are connected.
The plurality of striped cathode electrodes 142 and the plurality of striped gate electrodes 144 intersect, and the gate electrode 144 at the intersection of the cathode electrode 142 and the gate electrode 144 has a minute opening 146. Cathode (cold cathode) 1 with sharp tip from electrode 142
45 project. In the above description, the case where the cold cathode formed from the opening of the gate electrode, the conical portion of the cathode electrode, the bottom portion of the cathode electrode, and the like is set in a region where the gate electrode and the cathode electrode intersect is described. However, any number of two or more sets may be used.

Next, FIG. 15 shows the configuration of the cold cathode array imaging device of the present invention in which the cold cathode array device and the photoelectric conversion target according to the above-described method of manufacturing the cold cathode array device of the present invention are incorporated in an envelope. Show. In FIG.
Is a cold cathode array image sensor, 151 is a face plate made of glass or quartz, which is a substrate of a photoelectric conversion target, 158 is a signal electrode provided through the face plate 151, and 152 is a face electrode of the face plate 151. A transparent electrode 15 made of, for example, SnO ₂ , In ₂ O ₃ ,
3 is formed on the transparent electrode 152, for example,
A photoconductive film made of Se-As-Te, Sb ₂ S ₃ , PbO, CdSe, etc.,
154 is a cold cathode array element that emits an electron beam to the photoconductive film 153 in a required scanning order, 155 is an envelope made of glass or quartz, 157 is an electrode lead provided on the envelope 155, 156 Is the face plate 15
1 shows metal indium used to press-fit seal 1 and envelope 155. The face plate 15
1 is provided with a signal electrode 158 through which a video signal current flows, and an electrode lead 15 provided on an envelope 155 is provided.
7, or the face plate 151 and the envelope 155
May be used as the signal electrode.

The process of manufacturing a cold cathode array imaging device of the present invention by combining a photoelectric conversion target and a cold cathode array device according to the manufacturing method of the present invention will be described. The electrode lead 157 is provided in an envelope 155 made of glass or quartz in a separate step. The cold cathode array element 154 in which the cold cathode array manufactured according to the present invention and the drive control circuit are integrally formed is connected to the envelope 155 provided with the electrode lead 157. Next, Be or A, which is an X-ray window material in which glass or quartz of the photoelectric conversion target is coated or bonded with glass or quartz on the surface to be pressure-sealed, is used.
A metal indium 156 is interposed between a face plate 151 made of a plate material 1 and an envelope 155 made of glass or quartz, and pressure bonding is performed under an air pressure of 1 × 10 to ⁴ Pa or less. Alternatively, face plate 1
After a metal indium 156 is interposed between the envelope 51 and the envelope 155 and pressure-bonded and sealed at atmospheric pressure, the inside is evacuated to 1 × 10 to ⁴ Pa or less using an exhaust pipe (not shown). Then, the exhaust pipe may be sealed.

[0028]

According to the present invention, a cold-cathode array device is manufactured by integrating a cold-cathode array for emitting an electron beam and a drive control circuit for controlling the driving of the cold-cathode array on the same substrate. A method and structure and a cold cathode array imaging device can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing process of a drive control circuit region of a cold cathode array element by a method of manufacturing a cold cathode array element according to the present invention.

FIG. 2 is a view showing a manufacturing process of a drive control circuit area of a cold cathode array element by a method of manufacturing a cold cathode array element of the present invention.

FIG. 3 is a view showing a manufacturing process of a drive control circuit area of a cold cathode array element by a method of manufacturing a cold cathode array element of the present invention.

FIG. 4 is a view showing a manufacturing process of a drive control circuit region of a cold cathode array element by a method of manufacturing a cold cathode array element according to the present invention.

FIG. 5 is a view showing a manufacturing process of a drive control circuit area of a cold cathode array element by a method of manufacturing a cold cathode array element of the present invention.

FIG. 6 is a view showing a manufacturing process of a drive control circuit area of the cold cathode array element according to the method of manufacturing a cold cathode array element of the present invention.

FIG. 7 is a view showing a manufacturing process of a cold cathode array region of the cold cathode array device according to the cold cathode array device manufacturing method of the present invention.

FIG. 8 is a view showing a manufacturing process of a cold cathode array region of the cold cathode array device according to the cold cathode array device manufacturing method of the present invention.

FIG. 9 is a view showing a process of manufacturing a cold cathode array region of the cold cathode array device according to the cold cathode array device manufacturing method of the present invention.

FIG. 10 is a diagram showing a manufacturing process of a cold cathode array region of the cold cathode array device according to the cold cathode array device manufacturing method of the present invention.

FIG. 11 is a view showing a manufacturing process of a cold cathode array region of the cold cathode array device according to the cold cathode array device manufacturing method of the present invention.

FIG. 12 is a view showing a process of manufacturing a cold cathode array element according to the method of manufacturing a cold cathode array element of the present invention.

FIG. 13 is a diagram showing a manufacturing process of a cold cathode array element according to the method of manufacturing a cold cathode array element of the present invention.

FIG. 14 is a simplified overall view of a cold cathode array element according to the method for manufacturing a cold cathode array element of the present invention.

FIG. 15 is an explanatory diagram of a cold cathode array imaging device of the present invention.

FIG. 16 is a partial cross-sectional view of the cold cathode array.

FIG. 17 is an explanatory diagram of an imaging tube.

[Explanation of symbols]

1, 141 silicon substrate, 2, 2 ', 21, 22, 23, 201, 231 silicon oxide film, 3, 31, 32, 321 silicon nitride film, 4 NWell diffusion layer, 5 PWell diffusion layer, 6 source, drain P , A source and drain N-type diffusion layer, 10, 101 polycrystalline silicon film, 25, 251 phosphorus glass, 51 NF diffusion layer, 81 Al electrode and wiring, 82, 84, 821, 831, 841, 842, 831
1 Cr or Mo layer, 85 Al layer, 86, 862 Mo layer, 91, 92, 93, 94, 95, 96 photoresist, 140, 154 Cold cathode array element, 142, 162 Cathode electrode, 144, 164 Gate electrode, 145 165 cold cathode, 146 minute opening of gate electrode, 147, 148 drive control circuit, 150 cold cathode array imaging device, 151 face plate, 152 transparent electrode, 153 photoconductive film, 155 envelope, 156 metal indium, 157 electrode lead, 158 signal electrode, 161 substrate, 163 insulating layer, 171 photoelectric conversion target, 172 electron gun part, 173 electron beam, 210 contact hole, 230 cathode electrode forming hole, 811 AL wiring, 812 wiring connection part, 819 Wiring, 832 opening, 2310 Electrode connecting area.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/14 H01L 27/14 Z (72) Inventor Saburo Okazaki 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Masakazu Namba 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Noriaki Okamura Kamisasao, Kobuchizawa-machi, Kita-Koma County, Yamanashi Prefecture 3434-1 Hitachi Electronics Co., Ltd. Kobuchizawa Plant (72) Inventor Ryoichi Ito 32 Miyukicho, Kodaira-shi, Tokyo Hitachi Electronics Co., Ltd. 1 Hitachi Electronics Co., Ltd. Kobuchizawa Plant (72) Inventor Shigeru Inoue 3434-1, Kasasao, Kobuchizawa-machi, Kita-Koma-gun, Yamanashi Prefecture Hitachi Electronics Formula company Kobuchizawa in the factory (72) inventor Saito, Masanori Tokyo Kodaira Miyuki-cho, address 32 Hitachi Electronics Co., Ltd. Koganei factory in the F-term (reference) 4M118 AA10 AB01 BA30 DA34 EA01 EA02 EA04 5C031 DD09 DD19 5C032 AA01 5C037 AB08 AB23

Claims (10)

[Claims] 1. A step of forming a cold cathode array for emitting an electron beam on the same required conductivity type semiconductor substrate, an area selection circuit for selecting an electron beam emission area of the cold cathode array, and controlling the electron beam emission. Forming a drive control circuit composed of a level conversion circuit that generates a voltage for performing the operation, and connecting the drive control circuit to the cold cathode array formed in each of the steps. A method for manufacturing a cold cathode array element, comprising manufacturing a cold cathode array element including an array and the drive control circuit. 2. A cold cathode array region for emitting an electron beam is formed on the same required conductivity type semiconductor substrate.
Forming a drive control circuit including an area selection circuit for selecting an electron beam emission area of the cold cathode array and a level conversion circuit for generating a voltage for controlling electron beam emission;
Next, a method of manufacturing a cold cathode array element, comprising connecting the cold cathode array and the drive control circuit to manufacture a cold cathode array element constituted by the cold cathode array and the drive control circuit. 3. An area selection circuit for selecting an electron beam emission area of a cold cathode array for emitting an electron beam on the same required conductivity type semiconductor substrate, and a level conversion circuit for generating a voltage for controlling the electron beam emission. Forming a drive control circuit, and then forming the cold cathode array region, and then connecting the cold cathode array and the drive control circuit, the cold cathode array and the drive control circuit A method for manufacturing a cold cathode array element, comprising manufacturing a cold cathode array element comprising: 4. A step of forming a polycrystalline semiconductor layer on the same required conductivity type semiconductor substrate via an insulating film; and selectively etching the polycrystalline semiconductor layer using an etching mask material, Removing a material, ion-implanting the polycrystalline semiconductor layer into a mask, or forming a diffusion region of the other conductivity type impurity on the required conductivity type semiconductor substrate by thermal diffusion; Forming a metal layer on the diffusion region and the required conductivity type semiconductor substrate after selectively removing the mask material by selectively etching the film using an etching mask material; and etching the metal layer with a mask material for etching. Using a selective etching process to remove the mask material to form an electrode including a wiring pattern of the metal layer on the diffusion region; The via the insulating film on the body substrate 2
Forming a third metal layer on the required conductivity type semiconductor substrate via a second insulating film; and using an etching mask material to form the third metal layer. Selectively etching the second insulating film using the third metal layer as a mask after the mask material is removed by etching selectively; and forming a fourth metal on the selectively etched third metal layer. Continuously forming one or more metal layers including the layers on the semiconductor substrate of the required conductivity type. 5. A step of forming a polycrystalline semiconductor layer on the same required conductivity type semiconductor substrate with an insulating film interposed therebetween, and selectively etching the polycrystalline semiconductor layer using an etching mask material; Removing a material, ion-implanting the polycrystalline semiconductor layer into a mask, or forming a diffusion region of the other conductivity type impurity on the required conductivity type semiconductor substrate by thermal diffusion; Forming a metal layer on the diffusion region and the required conductivity type semiconductor substrate after selectively removing the mask material by selectively etching the film using an etching mask material; and etching the metal layer with a mask material for etching. Using a selective etching process to remove the mask material to form an electrode including a wiring pattern of the metal layer on the diffusion region; The via the insulating film on the body substrate 2
Forming a third metal layer on the required conductivity type semiconductor substrate via a second insulating film; and selectively etching the third metal layer to obtain at least a required metal layer. Forming an opening constituting an electrode structure for controlling electron beam emission from the cold cathode in the region, selectively etching the second insulating film using the third metal layer as a mask, and selectively etching the second insulating film. Forming a fourth metal layer on the third metal layer to reduce the diameter of the opening formed in the third metal layer. Method. 6. A cold cathode array for emitting an electron beam, formed on the same required conductivity type semiconductor substrate, an area selecting circuit for selecting an electron beam emission area of the cold cathode array, and controlling the electron beam emission. A cold-cathode array device comprising: a drive control circuit configured by a level conversion circuit that generates a voltage of (c); and a structure that connects the cold-cathode array and the drive control circuit. 7. A polycrystalline semiconductor layer formed on the same required conductivity type semiconductor substrate via an insulating film, and said polycrystalline semiconductor layer is selectively etched using an etching mask material, and then said mask material is formed. Is removed, and the polycrystalline semiconductor layer is ion-implanted into a mask, or a diffusion region of the other conductivity type impurity formed on the required conductivity type semiconductor substrate by thermal diffusion and the insulating film on the diffusion region are selected. After removing the mask material by etching, a metal layer formed on the diffusion region and the semiconductor substrate of the required conductivity type; a wiring pattern formed by the metal layer formed by selectively etching the metal layer; A second metal layer formed on the semiconductor substrate with the insulating film interposed therebetween, a second insulating film formed on the required conductivity type semiconductor substrate, and formed with the second insulating film interposed therebetween A third metal layer, and one or more metal layers including a fourth metal layer on the third metal layer obtained by selectively etching the second insulating film using the third metal layer as a mask. Are continuously formed on the semiconductor substrate of the required conductivity type. 8. An envelope in which a cold cathode array element in which a cold cathode array and a drive control circuit are integrally formed on the same substrate is incorporated, and a transparent electrode and a photoconductive film are formed on a face plate. A cold-cathode array imaging device, wherein a cold-cathode array image sensor is pressure-bonded to a photoelectric conversion target via metal indium disposed in a sealing portion and hermetically sealed. 9. The cold-cathode array imaging device according to claim 8, wherein at least a part of the envelope and the face plate are made of glass. 10. The cold cathode array imaging device according to claim 8, wherein at least a part of the envelope and the face plate are made of quartz.