JP2001044817A - Input output circuit for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the current consumption of an input output circuit for a semiconductor device. SOLUTION: An input output circuit 11 has a control signal generator 116 that controls a selective operation of a selector 113 and an output operation of a tristate output buffer 115 with two different control signals OE, SEL respectively. In an input state, where the tristate output buffer 115 reaches the high impedance state by one (OE) of the different control signals, when the selector 113 selects consecutive data streams D1-D4 given to an input output common use terminal 10a of an input buffer 111 and the output buffer 115 as external input data and an output side latch 114 latches the data stream, a selector control signal SEL of the selector 113 is generated in only the same clock timing as a data output timing of the final order, in consecutive data streams to allow the output side latch 114 to latch only the final data D4. Thus, number of times of operations of the output side latch at an input operation can be suppressed, to reduce the current consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output circuit, and more particularly, to a timing margin connected from an input / output terminal of a semiconductor device to a latch circuit provided immediately before a three-state output buffer. The present invention relates to an input / output circuit that has been improved to improve operation speed, power consumption, and reliability.

[0002]

2. Description of the Related Art A conventional input / output circuit of this kind is used particularly for an input / output circuit connected to an input / output terminal of a semiconductor device.

The input / output circuit generally includes an input buffer for inputting data supplied from the outside and supplying the data to an internal circuit, and an output buffer for receiving data output from the internal circuit and outputting the data to an external circuit. Further, the output buffer has three output states of a high level (hereinafter, referred to as H level), a low level (hereinafter, referred to as L level) of a logic level, and a high impedance state of an undefined state. Some have a function as a buffer, and the input terminal of the input buffer and the output terminal of the output buffer are commonly connected to one input / output terminal.

In other words, one input / output terminal has a three-state output buffer in a high impedance state when data is input, and the three-state output buffer outputs an H-level or L-level binary signal when data is output. Input terminal and output terminal.

The input / output circuit mediates the exchange of data with an external circuit as described above, but also has a role of preventing unnecessary noise from the outside and protecting the inside of the semiconductor device from static voltage breakdown. I have

[0006] Such an input / output circuit is usually built in a semiconductor device at the time of manufacture, requires a continuous data input / output function as a function, and has a higher speed than conventional ones. It is also required to have low power consumption and high reliability.

An example disclosed to meet this requirement is described in Japanese Patent Application Laid-Open No. Sho 60-170994. Referring to FIG. 10 showing the configuration of an input / output circuit described in the publication, this conventional input / output circuit includes an input / output terminal 100.
An input / output switching control signal (read enable) based on an input buffer 101 to which a signal is externally supplied to this terminal via an input terminal, and an output of the input buffer 101 and data N1 to be output from an internal circuit to the outside. Signal) The output signal DI of the input buffer 101 in response to the OE low level
And a latch 103 for holding the selected signal SD, and a three-state for outputting the output signal of the latch 103 to the input / output terminal 100. Output buffer 1
04.

The input / output circuit includes an input / output terminal 100
The data input to the input buffer 101 and the selector 1
02, and the latched data is output to the latch 103 at the same time as the operation state of the I / O terminal 100 is switched to the output operation, that is, the data that has been input to the I / O terminal 100 until immediately before is output. This prevents unnecessary change of the input / output terminal.

Referring to FIG. 11 showing a timing chart for explaining the operation of the conventional input / output circuit, the output data N1 of the internal circuit includes the data D0 during the period when the state of the input / output circuit is in the input state. The read enable signal OE supplied to the selector 102 and the three-state output buffer 104 is set to the L level, for example, for six clock periods, and the state of the input / output circuit is set to the input state. Is returned to the H level to be in the output state.

When the read enable signal OE goes low and the three-state output buffer 104 enters the high impedance state, the input / output terminal 100
Are input with data D1, D2, D3, and D4, and are selected by the selector 102 via the input buffer 101. The latch 103 sequentially latches and holds the selected signal SD at the rising edge of the next internal clock signal.

When the read enable signal OE is inverted to the H level, the selector 102 selects and outputs the output data N1 (D5, D6) of the internal circuit.
5 and D6 are latched and held by the latch 103 at the next rise of the internal clock signal. This held data D
5 and D6 are output to the I / O terminal 100 via the three-state output buffer 104.

In the figure, a high-impedance period for one clock is provided before and after the data strings D1, D2, D3, and D4. This high-impedance period is generally called a turnaround time and the like. Simultaneous activation of 3-state output buffer and external data,
That is, it is generally defined as a specification for avoiding bus fight (for example, PCI, SDRAM).
etc).

[0013]

The conventional input / output circuit described above will be apparent from a comparison between FIG. 2 showing the structure of a first embodiment of the present invention described later and FIG. 7 showing a timing chart thereof. In addition, data input from the outside to the input / output terminal is selected by a selector in response to a read enable signal OE, and is derived to a subsequent latch circuit.

Therefore, while the input / output terminal is functioning as an input terminal, the latch circuit operates in response to a change in input data, and as a result, wasteful power is consumed. . Further, wasteful power consumption causes an increase in noise components, leading to a decrease in reliability.

Further, since the input data is directly derived to the selector via the input buffer, the timing margin from the input / output terminal to the latch following the selector is reduced by the delay of the selector and the input buffer. There is also a problem that an extra wiring delay to the selector is required.

SUMMARY OF THE INVENTION An object of the present invention has been made in view of the above-mentioned drawbacks of the related art, and it is possible to select and latch necessary data from a continuous data string input to an input / output terminal, thereby obtaining an input / output signal. It is an object of the present invention to improve the timing margin from a terminal to a latch subsequent to a selector, and to provide an extremely good input / output circuit with higher speed, lower power consumption and higher reliability.

[0017]

A feature of the input / output circuit of the present invention is that a selector for selectively leading external input data or output data of an internal circuit to a three-state output buffer via output side holding means. And an input / output circuit that controls the selection operation of the selector and the output operation of the three-state output buffer by a predetermined control signal, wherein the selection operation of the selector and the output operation of the three-state output buffer are different from each other. Control signal generating means for controlling with the two control signals, the three-state output buffer being in an input state in which the three-state output buffer is in a high impedance state by one of the two different control signals. And a continuous data string input to the input / output terminal of the input buffer as the external input data. When the data is selected by the selector and held by the output side holding means, a selector control signal of the selector is generated only at the same clock timing as the last data output timing of the continuous data string, and only the final data is output. By holding the output side holding means, the number of operations of the output side holding means during the input operation is suppressed.

When the external input data is derived to the output side holding means, an input side holding means may be further provided between the input buffer connected to the input / output terminal and the selector.

Further, the control signal generating means is responsive to a first control signal input from the outside in synchronization with an internal clock signal, for setting the selector control signal and the three-state output buffer to a high impedance or output state. The read control signal is generated together with the enable signal, and the generation period of the selector control signal is included in the period in which the read enable signal is activated to the high impedance state.

Further, the control signal generating means generates the selector control signal at least two cycles before the end of the activation period of the read enable signal, so that the control signal generating means is provided at the front of the three-state output buffer. In response to the selector control signal, the output-side holding means latches the last data of a continuous data string externally input to the input / output terminal of the three-state output buffer. The final data can be output to the input / output terminal.

When the predetermined write request signal and the selector control signal are at a high level, the selector selects the output data of the internal circuit and holds the output data in the output side holding means. When the selector control signal is at a high level and the write request signal is at a low level, an input buffer provided between the input buffer connected to the input / output terminal and the selector is provided. Means for selecting the output data of the means, and when the write request signal and the selector control signal are both at the low level, the output data of the input side holding means held by the output side holding means is changed to the high level by the selector control signal. You can keep it until you do.

Further, the output-side holding means converts the last data held in response to the high level of the selector control signal to the output data of the internal circuit in response to the high level of the write request signal. It is also possible to keep holding the data until it is selected and read by the selector.

Another feature of the input / output circuit of the semiconductor device of the present invention is that the mode is controlled in response to a high level of the write request signal from a control circuit for inputting a write request signal, a read request signal, and a mode setting signal. If the value of the setting signal is n (n is a real number), the write enable signal is set to a high level for n cycles of the internal clock signal, and the value of the mode setting signal is n in response to the high level of the read request signal.
Then, a data output timing control signal which is set to a high level for an n-cycle period of an internal clock signal, and n continuous data strings generated by a data generation circuit which inputs a data string control signal obtained by shifting this signal by one cycle, and And output data of the circuit are provided as input signals, respectively, and in response to the data output timing control signal, the data is output at the same clock timing as the output timing of the last data of the data string input in synchronization with the internal clock signal.
First control signal generating means for generating a read enable signal for controlling an output buffer of a state and also generating a selector control signal of the selecting means in synchronization with the internal clock signal in response to the write enable signal; An input / output terminal for receiving an input signal also from the data train and other external circuits; and a second terminal for holding the input signal from the external device and the data train input to this terminal in synchronization with a predetermined internal clock signal. (1) holding means, selector means for selecting data held by the first holding means and output data of an internal circuit, and holding means for holding selected data output from the selector means in synchronization with the internal clock signal. 2 is connected between the second holding means and the input / output terminal, and the output state is changed by the read enable signal. It is to consist of a 3-state output buffer which is controlled impedance.

The control signal generating means includes cascaded third, fourth, and fifth holding means for inputting the data output timing control signal in synchronization with the internal clock signal; , ORing means for calculating the logic of the output signal of the fourth and fifth holding means and the data output timing control signal, and sixth holding for holding the output of the ORing means in synchronization with the internal clock signal Means for generating a read enable signal, a logical AND means for calculating a logic of a polarity inverted output of an output of the third holding means and an output of the fourth holding means, and an output of the logical AND means. And a selector control signal generation unit including a seventh holding unit that holds the data in synchronization with the internal clock signal.

Further, the synchronization means of the first and second holding means is controlled by first clock control means and second clock control means, respectively, instead of the internal clock signal, and the first control means A second control signal generating means is provided in place of the signal generating means, wherein the second control signal generating means transmits the data output timing control signal together with the read enable signal and the selector control signal to two cycles of the internal clock signal. A latch control signal shifted by an amount corresponding to the internal clock signal, wherein the first clock control means holds the latch control signal in synchronization with the internal clock signal, and an output signal of the eighth hold means. And a logical AND means for extracting an internal clock signal, wherein the second clock control means comprises: ORing means for taking the logic of the selector control signal, ninth holding means for holding the output signal of the ORing means in synchronization with the internal clock signal, and the output signal of the ninth holding means It can also be configured with logical product means for extraction.

Further, the second control signal generating means, the first clock control means, and the second clock control means are each provided in a pair, so that the second holding means corresponding to a plurality of the input / output terminals is provided. The selector means, the second holding means, and the three-state output buffer which are provided before the means can be commonly controlled.

Further, the first and second holding means operate only at the rising timing of the control clock signal output from the first clock control means and the second clock control means. During the internal clock signal period, the holding operation can be suppressed, and the current amount due to the holding operation in response to the internal clock signal can be suppressed.

Further, only the output signals of the first and second holding means are used as input signals of selector means provided in front of the second holding means, and a signal selected from these two signals is output. The three-state output buffer may be used as a means for preventing the input / output terminal from floating.

Still further, the output data of the internal circuit and the write enable signal are not supplied to the selector means provided in front of the second holding means, and are provided between the second holding means and the input / output terminal. The input / output terminal may not be set in a floating state by an output state set by the connected read enable signal.

Further, the selector means can directly input the data string inputted to the input / output terminal without passing through the first holding means.

Further, the control circuit and the data generation circuit may be formed on the same chip, or only one of them may be formed on the same chip.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described first with reference to the drawings. FIG. 1 is a system configuration diagram to which the first embodiment of the present invention is applied. Referring to FIG. 1, a system using the input / output circuit of the present invention includes an input / output circuit 11 of the present invention and a write request signal WR (Write Request) which is a control signal generated by a predetermined signal generation circuit (not shown). ), Read request signal RD (Read Request) and mode setting signal M
D (Mode), and if the value of the mode setting signal MD is n (n is a real number) in response to the H level of the write request signal WR as a control signal, the internal clock signal n
Write enable signal WE to be at H level during cycle period
(Write Enable) and the read request signal RD
The value of the mode setting signal MD changes to n in response to the H level of the signal.
Then, a data output timing control signal N2 for setting the H level during the n-cycle period of the internal clock signal, and this signal is set to 1
A control circuit 12 generates and outputs a data string control signal N3 shifted by the number of cycles, and a data generation circuit 13 which receives the data string control signal N3 and generates and outputs n continuous data strings N4. Input / output circuit 11
Write request signal WR, data output timing control signal N2, data string N4, and output data N1 of the internal circuit.
Are given as input signals.

These may be formed on the same chip, or may be formed as separate chips. Further, only one of them may be formed as a separate chip.

On the other hand, the input / output circuit 11 of the present invention has an internal clock signal C in response to a data output timing control signal N2, as shown in FIG.
A read enable signal OE for controlling a three-state output buffer is generated at the same clock timing as the output timing of the last data of the data string N4 input in synchronization with LK, and an internal clock signal is generated in response to the write enable signal WE. A control signal generator 116 which is a first control signal generating means which also generates a selector control signal SEL of the selecting means in synchronization with CLK, and an input / output terminal 10 which receives input signals from the data train N4 and other external circuits.
a and an input buffer 111 receiving a data string N4 input to this terminal 10a or an input signal from an external circuit.
And a latch 112 serving as first holding means for holding an input signal via the input buffer 111 in synchronization with a predetermined internal clock CLK, and selecting data held by the latch 112 and output data N1 of the internal circuit. Selector 113, a selector 114, a latch 114, a second holding unit for holding the selection data output from the selector 113 in synchronization with the internal clock CLK, and a connection between the latch 114 and the input / output terminal 10a. And a three-state buffer 115 whose output state is controlled to high impedance by the read enable signal OE.

Referring to FIG. 3 showing the structure of control signal generator 116, cascade-connected third, fourth, and fourth data input timing control signals N2 are input in synchronization with internal clock CLK. Latches 1161, 1162, 1163 which are fifth holding means, and latches 11
61, 1162, 1163 output signals M3, M4, M5
And a data output timing control signal N2, a NOR circuit 1164 as a logical sum means, and a latch 1165 as a sixth holding means for holding the output of the NOR circuit 1164 in synchronization with the internal clock CLK. Means for generating a read enable signal OE, and an output M3 of an inverter circuit 1166 for inverting the polarity of the output of the latch 1161
AND circuit 1167 which is a logical AND means for taking the logic of B and the output M4 of the latch 1162, and the AND circuit 1167
And a generating means for generating a selector control signal SEL comprising a latch 1168 which is a seventh holding means for holding the output M2 in synchronization with the internal clock CLK.

Referring to FIG. 4 showing a truth table of the operation of selector 113, when the write enable signal WE and the selector control signal SEL, which are input signals, are "0" and "0", the output SD is The output DO of the latch 114 is selectively output. When "0" or "1", the output SD selects and outputs the output DI of the latch 112. When "1" or "0", the output SD selects the output data N1 of the internal circuit. Output. A combination of "1" and "1" is a prohibition condition. Here, "0" indicates an L level and "1" indicates an H level.

Referring to FIG. 1, the relationship between the input / output circuit 11, the control circuit 12, and the data generation circuit 13 is based on the fact that the input / output circuit 11 of the present invention is controlled by a data output control timing signal N2 from the control circuit 12. The timing control of the data string N4 of the data generation circuit 13 is also performed by the data string control signal N3 input from the control circuit 12, and when the data string control signal N3 is at the H level, the data generation circuit 13 switches the data string N4. Output. Further, the output data string N4 of the data generating circuit 13 is the input / output circuit 1 of the present invention.
The input / output terminal 10 is controlled by a data output control timing signal N2. Furthermore, input / output circuit 11, control circuit 12, and data generation circuit 13 all have a common feature that they operate in synchronization with the rising of internal clock signal CLK.

That is, the control circuit 12 detects the H level of the read request signal RD. If the detection result indicates that the data value of the mode setting signal MD is "4", the control circuit 12 sets the data output control timing signal N2 to 4 When the data value of the mode setting signal MD is "2", the data output control timing signal N2 is set to the H level for the two cycle period H.
To level.

When the H level of the write request signal WR is detected, if the data value of the mode setting signal MD is "4", the write enable signal WE is set to the H level for "4" cycle periods, and the data value of the mode setting signal MD is changed. Is "2", the write enable signal WE is kept at the H level for two cycle periods.

On the other hand, the data stream control signal N3 output from the control circuit 12 is generated by shifting the data output control timing signal N2 output from the control circuit 12 by one cycle.

The control circuit 12 and the data generation circuit 13 for performing the above-described operations can be easily realized by those skilled in the art, and are not directly related to the configuration of the present invention. .

Next, the operation of the system shown in FIG. 1 will be described. Referring to FIG. 1 and FIG. 5 showing a timing chart for explaining the operation thereof, and FIG. 2 as needed, the mode setting signal MD outputs a data value “4” and the write request signal WR outputs an L level. It is assumed that At this time, when the read request signal RD goes to H level, the data value of the mode setting signal MD is “4”.
2 outputs a data output control timing signal N2 at the H level for four cycle periods in synchronization with the falling timing of the write request signal RD.

At this time, the data string control signal N3 is similarly output at the H level for the four cycle period with the data output control timing signal N2 shifted by one cycle.

When the data output control timing signal N2 goes high, the input / output circuit 11 enters the input state. When the data string control signal N3 is at the H level during the four cycle period, the data generation circuit 13 is shifted by one cycle from the rising timing of the data string control signal N3 in response to the data string control signal N3 at the H level during the four cycle period. For four cycle periods from the timing, the data D1, D2,
D3 and D4 are output as a data string N4.

The input / output circuit 11 takes in the data D1, D2, D3 and D4 from the input / output terminal 10 as input data into the input buffer 111 of FIG.

Next, when the data string control signal N3 goes to the L level after a lapse of 4 cycle periods, the data generation circuit 13 responds to the L level timing and the data D1, D2, one cycle after the L level timing. The outputs of D3 and D4 are terminated, and the potential of the I / O terminal 10 of the I / O circuit 11 is in a high impedance state for two cycles from the termination timing. During this time, the mode setting signal M
D is assumed to have its data value reset to, for example, "2".

On the other hand, the data output control timing signal N2
Becomes low level, the input / output circuit 11 enters an output state and starts outputting predetermined data to the input / output terminal 10.

When the write request signal WR goes high when the input / output circuit 11 is in the output state, the write enable signal WE is output from the control circuit 12 at a timing one clock after the rising timing of the high level. However, the data of the mode setting signal MD at that time is “2”.
Therefore, the write enable signal WE is output as the H level for two cycles.

When the write enable signal WE goes high when the input / output circuit 11 is in the output state, the input / output circuit 11 outputs the output data N of the internal circuit at a timing one clock after the rising timing of the high level.
1 is output via the input / output terminal 10.

When the input / output circuit 11 is in the input state, the data D1, D2, D
3, the high impedance period before and after the D4 input period is generally referred to as a turnaround time, as described above. However, the three-state of FIG. 2 to which the input / output terminal 10 (10a in FIG. 2) is connected. Output buffer 11
5 is generally defined as a standard for avoiding simultaneous activation of the output signal and the input data, that is, bus fight.

The high impedance period after data input in this embodiment is two cycles longer than one cycle in the conventional example, and is longer by one cycle. This is because the output signal DO of the latch 114 in FIG. This is because the change (D0 → D4) and the rise of the read enable signal OE have skew. If the change of the output signal DO of the latch 114 and the rise of the read enable signal OE are simultaneous, the data D0 is output to the input / output terminal 10 once, and then the data D4 is prevented from being output. .

Next, the operation of the input / output circuit 11 according to the first embodiment of the present invention will be described.
The operation of No. 6 will be described. FIG. 3 and control signal generator 1
Referring to FIG. 6 showing a timing chart for explaining the operation of No. 16, the data output control timing signal N2 at the H level, for example, for four cycle periods is latched by the latch 1161 in synchronization with the rising timing of the internal clock signal CLK. The data output control timing signal N2 is shifted by three cycles by sequentially latching its output by the latches 1162 and 1163, and the data output control timing signal N2, the output M3 of the latch 1161, and the latch 11
The output signal M1 of the NOR circuit 1164 having the input M4 of the output M4 and the output M5 of the latch 1163 as inputs is latched by the latch 116.
By shifting by 5, the read enable signal OE at L level is generated for a period of 7 cycles.

On the other hand, an output signal M3B of the inverter circuit 1166 having the output M3 of the latch 1161 as an input and an AND circuit 1167 having the output M4 of the latch 1162 as an input.
Is shifted by the latch 1168 to generate the selector control signal SEL.

These data output control timing signals N
2, read enable signal OE and selector control signal SE
Looking at the phase relationship with L, the falling timing of the read enable signal OE is shifted by one clock cycle with respect to the rising timing of the data output control timing signal N2, and the selector control is performed with respect to the falling timing of the read enable signal OE. The rising timing of the signal SEL is shifted by five clock cycles and is synchronized with the internal clock signal CLK.

Next, the operation of the entire input / output circuit 11 will be described. Referring to FIG. 2 and FIG. 7 showing a timing chart for explaining the operation of the input / output circuit 11, first, it is assumed that the write enable signal WE is at the L level. At this time, when the data output control timing signal N2 is at the H level for, for example, four clock cycles, the data generation circuit 13 responds to this H level by the above-described operation and performs one clock from the rising timing of the data output control timing signal N2. A read enable signal OE which is at L level for seven clock cycles from the timing after the cycle is output.

In response to the low level of read enable signal OE, 3-state buffer 115 is deactivated, input / output terminal 10a enters a high impedance state and waits for input data.

As described above, the data generating circuit 13 outputs the data D from the timing two clock cycles after the rising timing of the data output control timing signal N2.
1, D2, D3, and D4 are output as a data string N4, so that the data D1, D2, D3, and D4 are input to the I / O terminal 10a as continuous data of one cycle or more.

The data D1, D2, D3, and D4 input to the input / output terminal 10a are latched by the latch 112 via the input buffer 111, shifted by one clock cycle, and input to the selector 113.

At this time, the selector 113 selects and outputs the output of the subsequent latch 114 because the write enable signal WE and the selector control signal SEL are both at the L level in accordance with the truth table of FIG. Is data D0 which is a selector selection output when the previous selector control signal SEL is at H level.

The data D1, D2, D
The selector control signal SEL rises to the H level at a timing four clock cycles after the input of 3, D4 (shifted by 5 clock cycles with respect to the fall timing of the read enable signal OE), and during this H level period, the selector 113 Is selectively output, latched by the subsequent latch 114, shifted by one clock cycle, and output (output value D4 of the output signal DO of the latch 114).

That is, the clock timing for selecting the data D4 and the clock timing when the selector control signal SEL rises to the H level are synchronized with the rising of the same clock. Also, the output signal DO of the latch 114
Output value D4 output timing and selector control signal SE
The falling timing of L is synchronized with the rising timing of the same clock.

The above continuous data D1, D2, D
3, the selector control signal SEL goes high in synchronization with the rising timing of the same clock at which the rising timing of the last data D4 of D4 is synchronized, and the data D1, D2 because the read enable signal OE is still at the low level. , D3, and D4 have been input, the input / output terminal 10a returns to the high impedance state.

The above-mentioned high impedance state does not generally change the potential of the I / O terminal 10a, but keeps the potential for a certain period of time (several milliseconds to several seconds) due to the parasitic capacitance of the I / O terminal 10a. To be
In a high-speed system with a short clock cycle time (several nanoseconds to several microseconds), the potential of the input / output terminal 10a is maintained even in the high impedance state.

Next, read enable signal OE attains an H level, and 3-state buffer 115 switches from an input state to an output state. 3-state buffer 115 is activated to an output state, and outputs output signal DO of latch 114 to input / output terminal 10a. At this time, the last data D4 input to input / output terminal 10a is output.
Is latched by the latch 114 and held and output as the signal DO, so that the input / output terminal 10a
The switching from the input state to the output state is performed while holding.

When read enable signal OE is at H level, 3-state buffer 115 is in an output state.
The 3-state buffer 115 outputs the output signal D of the latch 114.
Data D4 that is O is output to the input / output terminal 10a.

At this time, since the selector control signal SEL is already at L level, if the write enable signal WE is at L level, the output signal DO (data D
4), as shown in the truth table of FIG.
Is output from the selector 113 as the selection output signal SD of

Since the latch output is again input to the selector and selected, the output signal SD of the selector 113 continues to output the same data D4 even if the internal clock signal changes, and the signal SD is input. Latch 11
4 also keeps its data D4, so that its output signal DO does not change, and therefore the input / output terminal 10a does not change either.

Since the selector control signal SEL is already at the L level, if the write enable signal WE is at the H level, as shown in the truth table of FIG. 4, the data D5 and D6 of the output signal N1 of the internal circuit are changed. The signal is selected by the selector 113 and output as the selected output signal SD.
And data D5 and D6 are output to the input / output terminal 10a via the 3-state buffer 115.

In the above-described embodiment, the control circuit 12 generates the control signal of the input / output circuit of the present invention as an example of the system configuration.
3, a signal corresponding to the data output control timing signal N2 and the data string control signal N3 may be generated, and the input / output circuit of the present invention may be controlled by these signals.

That is, as described above, the control circuit 12
Detects the H level of the read request signal RD. If the detection result indicates that the data value of the mode setting signal MD is "4", the data output control timing signal N2 is set to the H level for four cycles, If the data value of the signal MD is "2", the data output control timing signal N2 is set to the H level for two cycles, and if the H level of the write request signal WR is detected, the data value of the mode setting signal MD is set to "4". Then, the write enable signal WE is set to the H level for the "4" cycle, and the mode setting signal MD
Is "2", the write enable signal WE
Is set to the H level for two cycle periods, and the control circuit 12
The output data string control signal N3 is generated by the data generation circuit so as to satisfy that the data output control timing signal N2 output from the control circuit 12 is generated by shifting by one cycle.

In the above-described embodiment, one control signal generator 116 is used to control the I / O terminal 10a, one selector 113, and the three-state buffer 115. It is also possible to adopt a configuration in which a single unit 116 controls a selector for a plurality of input / output terminals and a three-state buffer.

Further, when the output state of the input / output circuit of the present invention is used only for preventing floating of the input / output terminal, the signal N1 and the write enable signal WE can be omitted. That is, the input / output circuit of the present invention
Since it can also be used as a means for preventing the input terminal from floating in the input circuit, it is not necessary to attach a pull-up resistor or a pull-down resistor to the input / output terminal.

As described above, in the input / output circuit of the present invention, the control signal generator 116 is provided, so that, when the three-state buffer is in the input state, a data string that has been input to the input / output terminal 10a and that has been continuously input to the input / output terminal 10a continues for an arbitrary cycle. , Only the last data is taken into the latch 114, the output signal DO of the latch 114 changes only once in synchronization with the same clock timing as the output timing of the last data, thereby reducing current consumption. The effect is obtained.

For example, when data arrives for four consecutive cycles, the number of changes of the output signal DO of the latch 114 can be reduced to one-fourth from four to one. Can be reduced to one-eighth.

That is, the number of changes of the signal DO when data comes for n consecutive cycles can be reduced to 1 / n, and the effect of reducing current consumption can be obtained.

Further, since the reduction of the current consumption leads to the reduction of the noise component, the effect of improving the reliability at the same time is obtained.

Further, by providing the latch 112 at the output of the input buffer 111, the timing margin from the input / output terminal 10a to the latch 114 can be reduced by the selector 1
13 and the effect of improving the delay due to the signal wiring from the input buffer 111 to the selector 113 can be obtained.

Conventionally, the latch 1
The signal path up to 14 was the input / output terminal 10a → the input buffer 111 → the selector 113 → the latch 114. However, in the input / output circuit of the present invention, the latch 112 was provided between the input buffer 111 and the selector 113. As a result, the input / output terminal 10a → the input buffer 111 → the latch 112, so that the timing margin from the input / output terminal 10a to the latch 114 is reduced by the selector 113.
Therefore, the effect of improving the signal delay and the wiring delay from the input buffer 111 to the selector 113 can be obtained.

Furthermore, even when the latch 112 is not provided and the wiring of the output signal I1 of the input buffer 111 and the wiring of the output signal DI of the latch 112 are directly connected, the timing margin from the input / output terminal 10a to the latch 114 is improved. However, it is clear that the effect of reducing current consumption can be obtained.

Next, a second embodiment of the present invention will be described. Its basic configuration is the same as that of the first embodiment,
The control of the latch 112 and the latch 114 is further devised.

Referring to FIG. 8, which is a block diagram showing the configuration of the second embodiment, the difference from the first embodiment is that a clock signal control circuit 87 for applying an internal clock signal CLK to a latch 112, a latch A clock signal control circuit 88 for providing an internal clock signal CLK is newly provided at 114, and a control signal generator 86 is provided so that a control signal generator 116 generates a signal M4 for controlling the clock signal control circuit 88. It is.

That is, the control signal generator 86 as the second control signal generating means is the same as the control signal generator 116 of FIG. 2 shown in FIG. 3, but the read enable signal OE
And a data output timing control together with a selector control signal SEL and a latch control signal M4 obtained by shifting the data output control timing signal N2 by two cycles of the internal clock signal CLK (the output signal M4 of the latch 1162 in the control signal generator 116 in FIG. Use).

A clock control circuit 87 serving as first clock control means includes a latch 871 serving as eighth holding means for holding the latch control signal M4 in synchronization with the internal clock signal CLK, and an output signal from the latch 871. An AND 872 which is a logical product means for extracting the internal clock signal CLK.

The clock control circuit 88 as the second clock control means includes an OR circuit 881 as a logical sum means for calculating the logic of the write enable signal WE and the selector control signal SEL, and an output signal J3 of the OR circuit 881. A latch 882 as ninth holding means for holding in synchronization with the clock signal CLK, and an output signal J of the latch 882;
2 and AND 883 which is a logical product means for extracting the internal clock signal CLK. The other configuration is the same as that of the first embodiment, and the description of the configuration here is omitted.

Next, the operation of the second embodiment will be described with reference to FIG. 9 showing a timing chart for explaining the operation.

First, the operation of the clock control circuit 87 and the clock control circuit 88 will be described. The latch 871 of the clock control circuit 87 sets the latch control signal M4 to 1 when the internal clock signal CLK falls at the L level.
The output signal J1 is shifted by / 2 clock cycles and output as an output signal J1, and the AND 872 receiving the output signal J1 outputs, for example, four continuous internal clock signals CLK in the H level period only when the output signal J1 is in the H level period. And outputs the same as the control clock signal K1 for the latch 82.

On the other hand, the OR circuit 8 of the clock control circuit 88
81 extracts the H level of each of the write enable signal WE and the selector control signal SEL and outputs the extracted signal to the latch 882 as a signal J3. The latch 882 outputs the signal J when the internal clock signal CLK falls at the L level.
3 by 1/2 clock cycle and output signal J2
AND883 receiving this output signal J2
Extracts, for example, only two continuous internal clock signals CLK during the H level period of the output signal J2, and outputs the control clock signal K2
Output as

Next, the operation of the entire input / output circuit will be described taking into account the above-mentioned control clock signals K1 and K2. The input / output circuit enters the input state in response to the level of the read enable signal OEL. Since the state output buffer 85 is in a high impedance state, the input / output terminal 10b is also in a high impedance state.

The data D1, after one clock cycle, is applied to the input / output terminal 10b in the high impedance state.
Data strings D2, D3, and D4 are provided, and input to the latch 82 via the input buffer 81. Latch 82 controls clock signal K supplied from clock control circuit 87.
The data D1, D2, D3, and D4 are respectively latched in synchronization with 1, and the latched held data are sequentially transmitted to the selector 83, and the last data D4 is held.
At this time, the input / output terminal 10b holds these data D
After receiving D1, D2, D3, and D4, respectively, the state returns to the high impedance state.

The selector 83 outputs the write enable signal W
In accordance with the above truth table under the condition that E is at the L level, in response to the H level of the selector control signal SEL for one clock cycle period, only the data D4 given at the same clock timing as the H level is selected. Then, it outputs the selection output signal SD to the latch 84. Latch 84
Latches and holds the data D4 of the selected output signal SD and outputs it to the input / output terminal 10b in synchronization with the rising timing of the control clock signal K2 supplied from the clock control circuit 88.

Next, when the read enable signal OE becomes inactive and goes to H level, the three-state output buffer 85 changes from the high impedance state to the signal output state, and outputs the data D4 held in the latch 84. I do.

In this state, the write enable signal WE becomes 2
When the clock period goes to the H level, the selector 83 responds to the H level in the two clock cycle period of the write enable signal WE in accordance with the above-described truth table under the condition that the selector control signal SEL is at the L level. Only the output data D5 and D6 of the internal circuit given at the same clock timing as the level are selected and output to the latch 84 as the selected output signal SD and the input / output terminal 10
Output to b.

The latch 84 outputs the selected output signal SD in synchronization with the rising timing of each of the two clocks of the control clock signal K2 supplied from the clock control circuit 88.
Are latched and held.

As described above, the clock signal control circuit 8
The input / output circuit using the control clock signal K1
Is the internal clock signal CLK when the signal M4 is at the H level.
The control clock signal K2 is output in synchronization with the internal clock signal when either the write enable signal WE or the selector control signal SEL is at the H level.

Therefore, the clock CL of the latches 82 and 84
The number of latch operations synchronized with K can be minimized. When the input / output circuit is in the output state and the write enable signal WE is at the H level, the latch 82 does not operate and its output Since the signal DI does not change, the present embodiment has an effect of further reducing current consumption.

In the above-described second embodiment, the control signal generator 86 and the clock signal control circuits 87 and 88 each have a set of selectors 8 corresponding to one input / output terminal.
3, 3-state output buffer 85, latches 82, 84
The control signal generator 86 and the clock signal control circuits 87 and 88 each correspond to a selector corresponding to a plurality of input / output terminals, a 3-state output buffer group, and latches 82 and 84. And a group of latches to be controlled.

[0097]

As described above, in the input / output circuit of the present invention, a selector for selectively leading external input data or output data of an internal circuit to a three-state output buffer via output side holding means. And an input / output circuit that controls the selection operation of the selector and the output operation of the three-state output buffer by a predetermined control signal, wherein the selection operation of the selector and the output operation of the three-state output buffer are controlled by different control signals. Control signal generating means for generating an external input signal to the input / output terminals of the three-state output buffer and the input buffer when the input buffer turns into a high-impedance state by one of the different control signals. When a continuous data string input as data is selected by the selector and held by the output holding means By generating the selector control signal of the selector only at the same clock timing as the last data output timing of the continuous data string and holding only the final data in the output side holding means, the output side holding means at the time of input operation When the external input data is led to the output-side holding means, the input-side holding means is further provided between the input buffer connected to the input / output terminal and the selector. The output signal changes only once in synchronization with the same clock timing as the last data output timing, and the effect of reducing current consumption can be obtained.

For example, when data arrives for four consecutive cycles, the number of times the output signal of the output side latch changes from four to one.
The number of times can be reduced to one fourth, and similarly, when data comes in eight consecutive cycles, the number can be reduced to one eighth. In other words, the number of changes in the output signal of the output-side latch when data arrives for n consecutive cycles can be reduced to 1 / n, and the effect of reducing the current consumption corresponding to that can be obtained.

Further, since the reduction of the current consumption leads to the reduction of the noise component, the effect of improving the reliability at the same time is obtained.

Further, by providing the input side latch, an effect is obtained that the timing margin from the input / output terminal to the output side latch is improved by the delay of the selector and the wiring delay from the input buffer to the selector. Conventionally, the signal path from the I / O terminal to the output side latch is as follows: input / output terminal → input buffer → selector →
Although the output side latch was used, in the input / output circuit of the present invention, the input side latch was provided, so that the input / output shared terminal → input buffer → input side latch, and therefore, the input / output terminal to the output side latch This has the effect of improving the timing margin by the delay of the selector and the wiring delay from the input buffer to the selector.

Further, when the output state of the input / output circuit of the present invention is used only for preventing floating of the input / output terminal, the output data of the internal circuit and the write enable signal WE can be omitted. That is, the input / output circuit of the present invention can also be used as a means for preventing the input / output terminal from floating in the input circuit, which contributes to the improvement of reliability.

Furthermore, even if the input signal is not provided and the output signal of the input buffer is directly supplied to the selector, the timing margin from the input / output terminal to the output latch is not improved, but the current consumption is reduced. Obviously, the effect described above can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a system to which an embodiment of the present invention is applied.

FIG. 2 is a block diagram showing a first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a control signal generator 116.

FIG. 4 is a diagram showing a truth table of the operation of a selector 113;

FIG. 5 is a timing chart for explaining the operation of the system shown in FIG. 1;

FIG. 6 is a timing chart for explaining the operation of the control signal generation circuit 116.

FIG. 7 is a timing chart for explaining the operation of the input / output circuit 11 according to the first embodiment.

FIG. 8 is a block diagram illustrating a configuration of a second embodiment.

FIG. 9 is a timing chart for explaining the operation of the input / output circuit according to the second embodiment.

FIG. 10 is a block diagram showing a configuration of a conventional input / output circuit.

FIG. 11 is a timing chart for explaining the operation of a conventional input / output circuit.

[Explanation of symbols]

10, 10a, 10b, 100 I / O terminal 11 I / O circuit 12 Control circuit 13 Data generation circuit 101, 111, 81 Input buffer 112, 82 Input side latch 113, 83 Selector 114, 84 Output side latch 115, 85 3 states Output buffers 116, 86 control signal generators 1161-1163, 1165, 1168, 871, 8
82 Latch 881 OR circuit 1166 Inverter circuit 1167, 872, 883 AND circuit 87, 88 Clock control circuit 1164 NOR circuit CLK Internal clock signal DI Output signal of input side latch I1 Output signal of input buffer J1 Output signal of latch 871 J2 Latch 882 J3 Output signal of OR circuit 881 K1 Output signal of AND circuit 872 K2 Output signal of AND circuit 883 M1 Output signal of OR circuit 1164 M2 Output signal of AND circuit 1167 M3 Output signal of latch 1161 M4 Output signal of latch 1162 M5 Output signal of latch 1163 N1 Output data of internal circuit N2 Data output control timing signal N3 Data column control signal N4 Data column MD mode setting signal OE Read enable signal RD Read request signal WE write enable signal WR write request signal

Claims (15)

[Claims] 1. A selector for selectively deriving external input data or output data of an internal circuit to a three-state output buffer via an output side holding means, and selecting the selector by a predetermined control signal. And an input / output circuit for controlling an output operation of the three-state output buffer, further comprising control signal generating means for controlling a selection operation of the selector and an output operation of the three-state output buffer with different control signals, respectively. In one of the different control signals, the input buffer is input to the input / output terminal of the three-state output buffer and the input buffer as the external input data in an input state in which the three-state output buffer enters a high impedance state. When a continuous data string is selected by the selector and held by the output side holding means, By generating a selector control signal of the selector only at the same clock timing as the last data output timing of the continuous data string and holding only the final data in the output side holding means, the output side holding means An input / output circuit for a semiconductor device, wherein the number of operations of the output side holding means is suppressed. 2. The semiconductor device according to claim 1, further comprising an input-side holding unit provided between the input buffer connected to the input / output terminal and the selector when the external input data is derived to the output-side holding unit. The input / output circuit of the device. 3. A read circuit for setting the selector control signal and the three-state output buffer to high impedance or an output state in response to a first control signal input from the outside in synchronization with an internal clock signal. 2. The input / output of a semiconductor device according to claim 1, wherein the input / output of the semiconductor device is performed together with an enable signal, and a generation period of the selector control signal is included in a period in which the read enable signal is activated to the high impedance state. circuit. 4. The three-state output buffer, wherein the control signal generating means generates the selector control signal at least two cycles before an end of an activation period of the read enable signal. In response to the selector control signal, the output side holding means latches the last data of the continuous data string input from the outside into the input / output terminal of the three-state output buffer. 4. The input / output circuit of a semiconductor device according to claim 3, wherein data is output to said input / output terminal. 5. The three-state output buffer, wherein the selector selects output data of the internal circuit and holds the output data in the output side holding means when a predetermined write request signal and the selector control signal are at a high level. When the selector control signal is at a high level and the write request signal is at a low level, an input buffer provided between the input buffer connected to the input / output terminal and the selector is provided. Means for selecting the output data of the means, and when the write request signal and the selector control signal are both at the low level, the output data of the input side holding means held by the output side holding means is changed to the high level by the selector control signal. 2. The input / output circuit of a semiconductor device according to claim 1, wherein the input / output circuit is maintained until the operation is completed. 6. The output-side holding means converts the last data held in response to the high level of the selector control signal to the output data of the internal circuit in response to the high level of the write request signal. 2. The input / output circuit of a semiconductor device according to claim 1, wherein the input / output circuit keeps holding the data until the data is selected and read by the selector. 7. When a value of the mode setting signal is n (n is a real number) in response to a high level of the write request signal from a control circuit that inputs a write request signal, a read request signal, and a mode setting signal. A write enable signal which is set to a high level for an n-cycle period of an internal clock signal; and a data output which is set to a high level for an n-cycle period of the internal clock signal if the value of the mode setting signal is n in response to the high level of the read request signal A timing control signal, n continuous data strings generated by a data generation circuit for inputting a data string control signal obtained by shifting this signal by one cycle, and output data of an internal circuit are provided as input signals, respectively; Output of the last data of the data string input in synchronization with the internal clock signal in response to the output timing control signal. A read enable signal for controlling a three-state output buffer is generated at the same clock timing as the output timing, and a selector control signal of the selection means is also generated in synchronization with the internal clock signal in response to the write enable signal. (1) a control signal generating means, an input / output terminal for receiving an input signal also from the data string and another external circuit, and a predetermined internal clock for transmitting the input signal from the data string or the external circuit to this terminal. First holding means for holding in synchronization with a signal, selector means for selecting data held by the first holding means and output data of an internal circuit, and selecting data output from the selector means to the internal clock. A second holding means for holding in synchronization with a signal, and a second holding means connected between the second holding means and the input / output terminal. Input-output circuit of a semiconductor device, wherein the output state at the read enable signal is composed, and the output buffer of the three-state controlled to a high impedance. 8. The cascade-connected third, fourth, and fifth holding means for inputting the data output timing control signal in synchronization with the internal clock signal; , ORing means for calculating the logic of the output signal of the fourth and fifth holding means and the data output timing control signal, and sixth holding for holding the output of the ORing means in synchronization with the internal clock signal Means for generating a read enable signal, a logical AND means for calculating a logic of a polarity inverted output of an output of the third holding means and an output of the fourth holding means, and an output of the logical AND means. 8. The input / output circuit of a semiconductor device according to claim 7, wherein said selector control signal generation means comprises: a seventh holding means for holding in synchronization with an internal clock signal. 9. The first control means controls the synchronization means of the first and second holding means by first clock control means and second clock control means in place of the internal clock signal, respectively, and said first control means A second control signal generating means is provided in place of the signal generating means, wherein the second control signal generating means transmits the data output timing control signal together with the read enable signal and the selector control signal to two cycles of the internal clock signal. A latch control signal shifted by an amount corresponding to the internal clock signal, wherein the first clock control means holds the latch control signal in synchronization with the internal clock signal, and an output signal of the eighth hold means. And logical product means for extracting the internal clock signal,
The second clock control means includes: a logical sum means for calculating a logic of the write enable signal and the selector control signal; a ninth holding means for holding an output signal of the logical sum means in synchronization with the internal clock signal; 8. The input / output circuit of a semiconductor device according to claim 7, wherein said input / output circuit comprises logical product means for extracting said internal clock signal from an output signal of said ninth holding means. 10. The second holding means corresponding to a plurality of input / output terminals by a set of each of the second control signal generation means, the first clock control means, and the second clock control means. The input / output circuit of a semiconductor device according to claim 9, wherein the selector means, the second holding means, and the three-state output buffer, which are provided in front of the semiconductor device, are commonly controlled. 11. The first and second holding means operate only at the rising timing of a control clock signal output from the first clock control means and the second clock control means, and 10. The input / output circuit of a semiconductor device according to claim 9, wherein a holding operation is suppressed during an internal clock signal period, and a current amount due to the holding operation in response to the internal clock signal is suppressed. 12. Only the output signals of said first and second holding means are used as input signals of selector means provided before said second holding means, and a signal selected from these two signals is output. 10. The input / output circuit of a semiconductor device according to claim 7, wherein said three-state output buffer is a means for preventing floating of said input / output terminal. 13. A connection between the second holding means and the input / output terminal without providing output data of the internal circuit and the write enable signal to a selector means provided in front of the second holding means. 10. The input / output circuit of a semiconductor device according to claim 7, wherein said input / output terminal is not brought into a floating state by an output state set by said read enable signal. 14. The input / output circuit of a semiconductor device according to claim 7, wherein said selector means directly inputs said data string input to said input / output terminal without passing through said first holding means. 15. The control circuit and the data generation circuit, including the control circuit and the data generation circuit, are formed on the same chip.
10. The semiconductor device according to claim 7, wherein only one device is formed on the same chip.
An input / output circuit of the semiconductor device according to claim 1.