JP2001043179A - Information processing apparatus and bus operating frequency control method - Google Patents

Abstract

(57) [Summary] [PROBLEMS] When a PCI bus operates at 66.6 MHz, up to two expansion cards can be installed, and the PCI bus is 33.3M.
The present invention provides an information processing apparatus capable of mounting up to four slots of an expansion card at the time of the Hz operation. SOLUTION: A PCI bus 210 divided into bus sections 211 and 212, a bus control means 21 connected to the bus section 211, a bus switch 79 connecting the bus section 211 and the bus section 212, and a bus section 211 , Slots 403 and 404 connected to the bus section 212, bus clock supply units 31 and 32, and a control unit 71. The control unit 71 detects the presence or absence of an expansion card and the upper limit operation frequency of the expansion card, and controls the output frequency of the bus clock supply unit and the bus switch 79 according to the detection result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus and a bus operating frequency control method capable of inserting and removing an I / O expansion card, and more particularly to an upper limit operation frequency of an I / O expansion card and an I / O expansion card. Slot for inserting card and I / O
Information that enables switching of the line length of the I / O bus in accordance with the number of expansion cards and selection of an optimal bus operating frequency for the configuration of the I / O expansion card without imposing a burden on the user. The present invention relates to a processing device and a bus operating frequency control method.

[0002]

2. Description of the Related Art In recent years, continuous operation of a PC (Personal Computer) server has become common, and techniques that have been used in high-end machines such as a workstation server and the like, such as insertion and removal of an I / O board and a hard disk, have been used. , P
It is also being applied to C servers. As a part of this, a technology (PCI Hot Plug) for inserting and removing an expansion card during operation of a PC server is also used in a widely used PCI (Peripheral Component Interconnect) bus as an I / O bus for a PC. . Details of the technology for inserting and removing the expansion card are described in, for example, PCI
Specification "PCI Ho" by Special Industry Group
t Plug Specification REV 1.0 ”, October 6, 1997
It is described in. Hereinafter, this technique is referred to as a PCI hot plug.

On the other hand, with the improvement in the processing capacity of PC servers, I / O expansion cards having higher data transfer capacity (throughput) are becoming widespread. For example, in a PCI bus, the operating frequency is increased from 33.3 MHz to 66.
6MHz and bus width from 32bit to 64bi
An I / O expansion card denoted by t has appeared. For the technology related to the details of the PCI bus, for example, see PCI Spec
Specification by PCI ial Interest Group "PCI Local B
us Specification Revision 2.1 "JUNE 1, 1995.

The upper limit operating frequency is 66.6 as described above.
The MHz PCI expansion card has upward compatibility with the conventional PCI expansion card whose upper limit operating frequency is 33.3 MHz, and can be used by connecting to a slot operating at 33.3 MHz. On the other hand, when the upper limit operating frequency is 33.
Although a PCI expansion card operating at 3 MHz can be connected to a slot operating at 66.6 MHz, it cannot operate normally, adversely affect bus signals and may cause a system failure.

Therefore, an information processing apparatus capable of inserting and removing an I / O expansion card according to the prior art determines the upper limit operating frequency of the expansion card when power is turned on or when a hot line is inserted or removed.
A bus operating at 6.6 MHz has an upper limit operating frequency of 33.
When a 3 MHz card is inserted, a warning is given to the user, and the operating frequency of the PCI bus can be changed. For details of this type of technology, see, for example, "PCI Ho," published by Anna Books.
t-Plug Application & Design "Alan Gooodrum, 1
998 and the like.

By the way, the propagation delay and the waveform distortion of the bus signal occur due to the capacitance component of the bus line and the expansion card. Therefore, in general, as the operating frequency of the bus increases, the number of expansion cards that can be connected simultaneously decreases.

For this reason, generally, the PCI bus has a 33.
When operating at 3 MHz, about four expansion cards can be connected, while when operating at 66.6 MHz, only about two expansion cards can be connected. As a technique for adding slots, two methods are generally known. The first is to bridge the bus.
The second method is to connect chips and add slots on the secondary side. The second method is to lower the operating frequency of the PCI bus clock to secure a timing margin and increase the number of slots per bus. That is. As a conventional technique relating to the second method, for example, a technique described in JP-A-10-74177 is known.

[0008]

As described above, in general, a PCI bus operating at 33.3 MHz can connect about four expansion cards in one bus section. A PCI bus operating at 6 MHz can connect only about two expansion cards. For this reason, the operating frequency of the prior art is 33.3 MH.
The PCI bus that switches between z and 66.6 MHz is
The number of expansion slots is configured as two expansion cards, and 3
When using an expansion card that operates at 3.3 MHz,
There is a problem that only two sheets can be used.

In the prior art in which the number of slots is increased by using a bridge chip, the bridge chip needs to have a function of analyzing a PCI bus transaction.
There is a problem that it is relatively expensive, and when the primary side PCI bus is set to 66.6 MHz, there is a problem that the number of additional slots in the primary side bus section is limited to two.

The prior art described in Japanese Patent Application Laid-Open No. Hei 10-74177 is to reduce the bus operating frequency of the entire PCI bus system. It is not a switching technology.

Further, the expansion card operating at 33.3 MHz and the expansion card operating at 66.6 MHz have the same card edge shape, and are stamped by a manufacturer or the like to determine the operation speed of the expansion card. Confirm the identified identification information visually or after turning on the power of the PC server,
The hardware or software of the PC server must identify the signal level by detecting the signal level, and thus there is a problem that the user may be confused when the card is added.

An object of the present invention is to solve the above-mentioned problems of the prior art and to increase the operating frequency of a PCI bus to 66.6 MHz.
And 33.3 MHz.
When the bus operates at 66.6 MHz, the expansion card
The present invention provides an information processing apparatus and a bus operating frequency control method in which up to four cards can be mounted, expansion cards can be used up to four slots when the PCI bus operates at 33.3 MHz, and the degree of freedom in system configuration by a user is improved. It is in.

It is still another object of the present invention to provide an information processing apparatus and a bus operating frequency control method capable of supporting a user to add a card by a user interface when switching between 33.3 MHz and 66.6 MHz. It is in.

[0014]

According to the present invention, there is provided an information processing apparatus capable of inserting and removing a plurality of I / O expansion cards having different upper-limit operating frequencies. Connecting means, card mounting detecting means for detecting whether or not an expansion card is mounted on expansion card connecting means provided corresponding to each of the plurality of expansion card connecting means, and mounted on the expansion card connecting means. Card frequency information detecting means for detecting the upper limit operating frequency of the expanded card, and frequency switching control means for determining and switching the bus operating frequency based on the number of installed expansion cards and the upper limit operating frequency. Is achieved by

[0015] The object is that the bus connecting the plurality of expansion card connecting means is first and second by a bus switch.
The second bus section is divided into two bus sections, and the frequency switching control means determines which of the first and second bus sections the expansion card is connected to the expansion card connection means. This is also achieved by determining the operating frequency of the bus as a condition.

Further, the object is to provide a method of controlling an operating frequency of a bus in an information processing device capable of inserting and removing a plurality of I / O expansion cards having different upper limit operating frequencies, wherein the information processing device is firstly controlled by a bus switch. A bus divided into a second bus section, a plurality of expansion card connecting means connected to each of the first bus section and the second bus section, and a plurality of expansion card connecting means are provided respectively. Card attachment detection means for detecting whether an expansion card is attached to the expansion card connection means, card frequency information detection means for detecting an upper limit operating frequency of the expansion card attached to the expansion card connection means, and bus clock supply Means, and a frequency switching control means, wherein the bus clock supply means has a first frequency and a second frequency lower than the first frequency. A bus clock of any frequency of the wave number is supplied to the expansion card connection unit, and the frequency switching control unit detects the bus by the detection result of the card attachment detection unit and the detection result of the card frequency information detection unit. When the operating frequency is determined, and when the information processing apparatus is powered on, all the expansion card connection means connected to the second bus section are not mounted, and the expansion card connection connected to the first bus section is connected. An expansion card is attached to any of the means, and when the upper limit operating frequency of all the attached expansion cards is equal to or higher than the first frequency, a first identification value is output. When the processing apparatus is powered on, if an expansion card is attached to any of the expansion card connection means connected to the second bus section, a second identification value is output and the first identification value is output. Ri, wherein the output clock from the bus clock supply means to said first frequency, and a disconnected state the bus switch, whereas,
The second identification value is achieved by setting the output clock from the bus clock supply unit to the second frequency and connecting the bus switch.

According to the present invention, when the PCI bus operates at 66.6 MHz, up to two expansion cards can be installed, and the PCI bus has a capacity of 33.3.
When operating at MHz, the expansion card can be used up to 4 slots, and the operating frequency of the PCI bus is set to 66.6 MHz.
z and 33.3 MHz can be switched,
The degree of freedom of the system configuration by the user can be improved.

Further, the present invention provides 33.3 MHz and 66.
When switching to 6 MHz, the user interface can assist the user in increasing the number of cards.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention.

FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to one embodiment of the present invention, and FIG. 2 is a diagram for explaining the arrangement of main components and the bus wiring shape of the information processing apparatus according to one embodiment of the present invention. , FIG. 3 is a block diagram showing the configuration of the control unit in FIG. 1, FIG.
FIG. 5 is a block diagram showing the relationship between the frequency information holding means and the frequency switching control means, and FIG. 5 is a diagram for explaining the register means in FIG. 1 to 5, 11 is a printed circuit board, 20 is a CPU, 21 is a memory / I / O controller, 22 is a memory, 24 is a CRT controller,
25 is a KB (keyboard) controller, 26 is an HDD
(Hard Disk) Controller, 27 is BIOS-R
OM, 31 are clock generating means, 32 is a clock buffer, 71 is a control unit, 79, 611 to 614 are bus switches, 92 is a frequency judging means, 93 is a frequency switching control means, 94 is a frequency information holding means, 95, 96 Is a register, 97 is a PCI expansion card, 241 is a monitor, 251
Is a keyboard, 261 is a hard disk, 401 to 40
4 is a PCI slot, 621 to 624, 631 to 63
4, 641 to 644 are switches, 721 to 724 are frequency information detecting means, 731 to 734 are hot plug control means, 751 is holding means, 761 is selecting means, 911 to 9
Reference numeral 14 denotes a register, and reference numerals 985 and 991 to 994 denote display lamps.

In the following description, for convenience of explanation, the configuration and function according to the prior art are denoted by headings starting with “Z”, and the configuration and function according to the present invention are denoted by “a” to “a”.
It is indicated by a heading starting with “h”.

The information processing apparatus according to the embodiment of the present invention shown in FIG. 1 has a CPU 20, a memory / I / O controller 2
1, a CRT controller 24 to which a memory 22 and a monitor 241 are connected, a KB controller 25 to which a keyboard 251 is connected, and an HD to which a hard disk 261 is connected.
A D-controller 26, a boot-up BIOS-ROM 27,
It comprises a clock generation means 31, a clock buffer 31, and a PCI bus system according to the present invention. The PCI bus system according to the present invention includes the PCI buses 210, 2
Each of the bus sections 211 and 212 includes two PCI slots 401 to 404 connected thereto, a control unit 71, and display lamps 985 and 991 to 994 as main components.

In the above description, the memory / I / O controller 21 has two I / O systems, a PCI bus 210 composed of two bus sections 211 and 212, and a bus 213.
The bus is connected. Then, the memory / I / O controller 21 constitutes a bus control unit of the information processing apparatus according to the present invention.

The information processing apparatus according to the embodiment of the present invention shown in FIG. 1 has a general PC I / O device,
3, a CRT controller 24, a keyboard controller 25, a hard disk controller 26, and a boot-up BIOS-ROM 27 are connected. The clock generating means 31 and the clock buffer 32 supply the PCI bus clocks 321 to 325, and constitute a bus clock supplying means of the information processing apparatus according to the present invention. Further, although not shown in FIG. 1 because it is not the essence of the present invention, the CP
U20 and memory / I / O controller 21 have separate C
A PU clock is supplied.

The PCI bus 210 is divided into a section 211 and a section 212 for the function of an embodiment of the present invention described later, and the bus section 211 is a first bus section of the information processing apparatus according to the present invention. , And the bus section 212 forms a second bus section of the information processing apparatus according to the present invention.
Each of the bus sections 211 and 212 includes a 32-bit or 64-bit data signal and a control signal.
In this case, a single bold line is used for simplification. Bus section 21
1 and the bus section 212 are connected via a bus switch 79. The bus switch 79 constitutes first switch means in the information processing device according to the present invention. The bus switch 79 is constituted by, for example, a MOS switch or the like,
As many as the number of bit widths of the PCI bus signal are arranged, FIG. 1 shows one circuit for simplification.

In the following description, the high level state of the signal is "1" and the low level state is "0". When the bus section connection control signal 712 is “1”, the bus switch 79 is turned on, and the section 211 and the section 212 are electrically connected. Also, a bus section connection control signal 712
Is "0", the bus switch 79 is turned off, and the section 211 and the section 212 are electrically disconnected.

Each of the PCI slots 401 to 404 is a PCI slot.
This is a slot into which an expansion card conforming to the specifications is inserted. To cope with hot-swapping of the expansion card, a configuration [Z0] based on a known PCI specification described below is used.
1] to [Z04].

Known configuration [Z01] Power supply 491-494 of PCI slots 401-404
Are connected to a main power supply 990 via switches 631 to 634. Each of the PCI slots 401 to 404 has +5 V, +3.3 V, +12 V, -12
Although four power supplies of V are required, FIG. 1 shows only one power supply for simplification.

The switch 631 is turned on when the control signal 831 is "1", and the slot 401 is turned on. When the control signal 831 is “0”, the switch 631 is turned off, and the slot 401 is turned off. Control signals 832 to 834, switch 6
The same applies to 32-342 and slots 402-404.

Known configuration [Z02] The PCI slots 401 to 404 are respectively connected to PCI bus sections 211 and 2 via bus switches 611 to 614.
12 is connected. The bus switches 611 to 614 are M
It is composed of OS switches and the like, and is arranged by the number of signals corresponding to the bit width of the PCI bus, but FIG. 1 simply shows one circuit.

The bus switch 611 is turned on when the control signal 811 is "1", and the PCI slot 401 is in the bus connection state. The bus switch 611 is turned off when the control signal 811 is “0”, and
The slot 401 enters the bus cutoff state. Control signal 812
To 814, bus switches 612 to 614 and slot 4
The same applies to 02 to 404.

Known Configuration [Z03] The clock signals of the PCI slots 401 to 404 are connected to outputs 321 to 324 of the clock buffer 32 via switches 621 to 624.

The switch 621 is turned on when the control signal 821 is "1", and the PCI slot 401 is in a clock supply state. The switch 621 is turned off when the control signal 821 is “0”,
The slot 401 enters the clock stop state. Control signal 8
22-824, switches 622-624 and slot 4
The same applies to 02 to 404.

Known configuration [Z04] Reset signals 441-441 of PCI slots 401-404
444 is individually provided to each of the PCI slots 401-404.

In the embodiment of the present invention, the aforementioned PCI slots 401 to 404 are divided into two groups and connected to the bus sections 211 and 212. That is, the PCI slots 401 and 402 are
1, 612 are connected to the bus section 211. The PCI slots 403 and 404 are connected to the bus section 212 via bus switches 613 and 614, respectively. The PCI slots 401 to 404 and the switches 611 to 614 constitute slot connection means in the information processing apparatus according to the present invention. The memory / I / O controller 21 and the control unit 71 are connected to a bus section 211.

Next, referring to FIG. 2 for explaining the arrangement of the main components and the wiring configuration of the bus of the information processing apparatus according to an embodiment of the present invention, the PCI slots 401 to 404 and the memory / I / O controller 21 will be described. Parts arrangement and bus section 21
1 and 212 will be described.

The PCI slots 401 to 404 are
Due to the shape of the expansion card 97, it is generally arranged in a row at the end of the printed circuit board. The embodiment of the present invention further includes the following configurations [a1] to [a4] according to the present invention.
The components are arranged according to the formula (1), and the bus sections 211 and 212 are wired.

Configuration [a1] The bus section 211 includes the memory / I / O controller 21,
Control unit 71, bus switch 611, bus switch 61
2. Wire in the shortest path in the order of the bus switch 79. The wiring length from the memory / I / O controller 21 to the bus switch 79 is approximately 150 to 250 mm or less.

Configuration [a2] The bus section 221 includes a bus switch 79, a bus switch 6
13 and the bus switch 614 in the shortest order. The wiring length from the bus switch 79 to the bus switch 614 is
It should be about 150 mm or less.

Configuration [a3] From the bus switches 611 to 614, each PCI slot 4
The wiring section connecting 01 to 404 is wired so as to be the shortest. For this reason, as shown in FIG.
It may be located in the board space between the slots 401-404.

Configuration [a4] The control unit 71 is arranged along a PCI bus section 211 connecting the memory / I / O controller 21 and the bus switch 611, and minimizes the connection with the bus section 211.

The paths of the wiring patterns according to the above-described configurations [a1] to [a4] are shown by thick lines in FIG. The wiring patterns indicated by the thick lines, the bus switches 611 to 6
14. The bus switch 79 is required for the number of signal lines constituting the bus, but one circuit is shown in the figure.

With the wiring as shown in FIG. 2,
When the bus switch 79 is in the ON state, the memory / I / O controller 21, the control unit 71, and the slots 401 to 40
4 are connected with the shortest line length. Also, the bus switch 7
When the bus 9 is in the OFF state, the bus sections 211 and 21
2 is electrically disconnected and is not affected by the wiring pattern of the bus section 212 or the capacitive load of the connectors 403 and 404, so that the signal propagation delay time in the bus section 211 can be improved.

Next, an example of the configuration of the control unit 71 shown in FIG. 1 will be described with reference to FIGS. 3 to 5
Of the input / output signals of FIG. 1 are denoted by the same symbols.

As shown in FIG. 3, the controller 71 includes card detecting means 51 to 54 and card frequency information detecting means 72.
1 to 724 and control means 731 to 734 for performing hot plug control based on the PCI specification as main components. Further, the frequency determination means 92 shown in FIG. 4 corresponds to the output signal line 51 of the card detection means shown in FIG.
1 to 514, and an output signal line 521 of the frequency information detecting means.
524, and the frequency judging means 92 is connected to a frequency switching control means 93 and a frequency information holding means 94 as shown in FIG.

Card mounting detecting means 51 to 54 shown in FIG.
Is a PCI specification PRS as an expansion card detection mechanism.
NT1 # and PRSNT2 # signals are used. These signals are not connected to a bus, but are wired for each slot. FIG. 3 shows PRSNT1 of slots 401 to 404.
The # signal is shown as signals 411 to 414, and the PRSNT2 # signal is shown as signals 421 to 424. Then, even when a card is not inserted, a normal logical level is indicated,
The signals 411 to 414 and 421 to 424 are pulled up by the main power supply 990.

The slot 401 will be described as an example.
According to the specifications of the CI, the signals 411 and 421 for the insertion state of the expansion card are in the following states [Z11] to [Z11].
12]. Signal 4 for slots 402-404
The same applies to 12 to 414 and signals 422 to 424.

State [Z11] When an expansion card is installed in the slot 401, either the PRSNT1 # signal pin or the PRSNT2 # signal pin of the expansion card is connected to GND. Therefore, any one of the signals 411 and 421 becomes “0”.

State [Z12] If no card is present, pull-up causes signal 41
1 and 421 are both “1”.

Card mounting detecting means 51 of slot 401
Needs to have a function [b1] described below, and is therefore realized by a NOR gate or the like that receives signals 411 and 421 as inputs. The same applies to the slots 402 to 404, the detecting means 52 to 54, and the card detection signals 512 to 514.

Function [b1] The card installation detecting means 51 sets the card detection signal 511 to "1" when an expansion card is installed in the slot 401, and detects the card when no expansion card is installed. The signal 511 is set to “0”.

The frequency information detecting means 721 to 724 output signals for detecting frequency information as M66 of PCI specification.
The EN # signal is used. These signals are provided by wiring for each slot without connecting to the bus. Slot 40
The M66EN # signals corresponding to 1-404 are shown as signals 431-434 in FIG. Note that this signal 43
1 to 434 may be pulled down to GND by a resistor so as to indicate a normal logic level even when a card is not inserted.

The signal 431 corresponding to the slot 401 is
According to the PCI specifications, for example, the state [Z
21] to [Z23]. Slots 402-404,
The same applies to the signals 432 to 434.

State [Z21] When an expansion card is not mounted in the slot 401, the signal 431 =
It becomes “0”.

State [Z22] When the upper limit operating frequency of the expansion card installed in the slot 401 is 33.3 MHz, M66EN # of the expansion card
Since the pin is connected to GND, the signal 431 becomes “0”.

State [Z23] When the upper limit operating frequency of the expansion card installed in the slot 401 is 66.6 MHz, M66EN # of the expansion card
Since the pin is pulled up on the expansion card, the signal 43
1 = “1”.

Incidentally, the M66EN # signals 431 to 43
4 not only indicates the upper limit operating frequency of the expansion card,
The specification is such that the operating frequency of the PCI bus is notified from the slot to the expansion card. Therefore, the information processing device according to the embodiment of the present invention has a function [c1] described later.

According to the PCI specification and a function [c1] described later, the PCI reset signals 441 to 444 become "1", and the signals 431 to 434 are activated when the expansion card is operated.
Does not necessarily correspond to the upper limit operating frequency of the expansion card. In order to always output constant card frequency information 521 when an expansion card is inserted, the card frequency information detecting means 721 in the configuration example of the control unit 71 shown in FIG. 3 has the following configurations [b2] and [b3]. . Slots 402 to 404 and card frequency information detecting means 721
741, detection signals 432 to 434, card frequency information 522 to 524, hot plug control means 732 to 73
4. The same applies to signals 842 to 844.

Configuration [b2] The frequency information detecting means 721 includes the hot plug controlling means 7
31, and the signal 841 changes from “0” to “1”.
The level of the signal 431 at the time of transition to
Hold at 1.

Configuration [b3] The frequency information detecting means 721 has a selecting means 761
According to the level of the PCI reset signal 441, the signal 43
1 and the output of the holding means 751 are output as card frequency information 521.

The hot plug control means 731 to 734
The following functions [Z31], [Z32], [Z32-
1] to [Z32-4]. The functions of the hot plug control units 731 to 734 are an example of a design conforming to the PCI specification. Since the same applies to the hot plug means 732 to 734, the hot plug control means 731 corresponding to the slot 401 will be described as an example.

Function [Z31] When the power is turned on, the signals 811, 821 and 831 are set to "1", the reset signal 441 is changed from "0" to "1", and the expansion card mounted in the slot 401 is initialized.

Function [Z32] A register 911 that can be accessed from software is provided. By writing a command, signals 811 and 821,
831, 841 and 441 are controlled. The command has functions [Z32-1] to [Z32-4] described below. The control procedure and switching timing conform to the PCI specification.

Function [Z32-1] Plug-in command: The signal 811 is set to “1” and the bus switch 611 is connected, so that the slot 4
01 is connected to the bus section 211. Further, the signal 821 is set to “1”, and the PCI clock 321 is supplied to the slot 401. Further, the reset signal 441 is changed from “0” to “1” to initialize the expansion card installed in the slot 401.

Function [Z32-2] Plug-off command: The signal 811 is set to “0”, and the bus switch 611 is turned off, so that the slot 4
01 is disconnected from the bus section 211. Also, the signal 821
Is set to “0”, and the PCI clock 321 supplied to the slot 401 is stopped. Further, the reset signal 441 is changed from “1” to “0”.

Function [Z32-3] Power-on command: The signal 831 is changed from "0" to "1", and the slot power supply 491 is turned on.

Function [Z32-4] Power-off command: The signal 831 is changed from "1" to "0", and the slot power 491 is turned off.

Further, hot plug means 732 to 734
Are functions [c1] to [c] described below for the present invention.
2].

Function [c1] When the power is turned on and when the plug-in command [Z32-1] is executed, the switches 641-6 are controlled by the control signals 841-844.
44, and the frequency identification information 711 is 33.3 MH.
In the case of “0” indicating the z operation, the signals 431 to 434 that are the M66EN # signals are connected to GND via the switches 641 to 644 to be “0”, and then the PCI reset signals 441 to 444 are set to “1”. And When the frequency identification information 711 is “1” indicating a 66.6 MHz operation, the switches 641 to 644 are turned off, and thereafter,
The PCI reset signals 441 to 444 are set to “1”.

Function [c2] The processing of the function [c1] described above is performed by the clock generation means 31.
After the frequency switching, the output 9 of the frequency switching means 93 is output.
A pulse is output to 31 to indicate that the clock has been stabilized.

Next, a mechanism for determining the operating frequency and switching the bus frequency according to the configuration of the expansion card will be described.

The frequency judging means 92 shown in FIG. 4 includes card detection signals 511 to 514 and card frequency information 521 to 5.
According to 24, the operating frequency of the PCI bus 201 having the bus sections 211 and 212 is determined. In particular, 66.6 MH
During the z operation, the number of expansion cards connected to the PCI bus is limited to about two,
1. Considering minimizing the waveform distortion of the PCI bus signal by limiting to slot 402, the condition [d
01] and [d02] at the same time, the frequency determination result 921 is set to “1” indicating a 66.6 MHz operation, otherwise “0” indicating a 33.3 MHz operation
And

Condition [d01] An expansion card is installed in either slot 401 or slot 402, and slot 403 or slot 404
No expansion card is installed in both.

Condition [d02] The upper limit operation frequency of the card inserted in the slots 401 and 402 is 66.6 MHz.

The above-mentioned conditions [d01] and [d02] represented by logical expressions are expressed by the following conditional expressions [d11] and [d11].
12]. Only when the conditional expressions [d11] and [d12] are simultaneously satisfied, the frequency determination result 921 is set to “1”.

Conditional expression [d11] {(card detection signal 511 = "1") OR (card detection signal 512 = "1") {AND} (card detection signal 513 =
"0") AND (card detection signal 514 = "0")}

Conditional expression [d12] {(card frequency information 521 = "1") AND (card detection signal 511 = "1")} AND {(card frequency information 522
= “1”) AND (card detection signal 512 = “1”)}

The above-described condition is obtained by converting a logical expression.
Other equivalent conditions can be used, but specifically, the conditions shown in Table 1 can be used. "X" in the table
Indicates that the logical value of the signal may be either "0" or "1".

[0079]

[Table 1]

The frequency information holding means 94 shown in FIG. 4 holds the frequency judgment result 921 at the time indicated by the output signal 931 of the frequency switching control means 93. The frequency switching control unit 93 compares the frequency determination result 921 with the content 941 of the frequency information held in the holding unit 94 according to the command written in the register 930 accessible by software. Is performed. Only once when the main power supply 990 is turned on, the frequency switching means 93
The switching of the frequency is determined without depending on the access.

The frequency switching control means 93 outputs a timing pulse to the signal 931 to notify the hot plug means 731 to 734 and the frequency information holding means 94 that the frequency switching processing has been completed.

Signals 711 and 7 corresponding to determination result 921
No. 12 is in the state [e1] or [e2] as shown below. Details of the switching process will be described later with reference to FIGS.

State [e1] When the determination result 921 = "1", the frequency information 711 is
It becomes “1” indicating 66.6 MHz operation, and the signal 712
Becomes “0” indicating disconnection between the bus section 211 and the bus section 212.

State [e2] When the determination result 921 = "0", the frequency information 711 is
It becomes “0” indicating 33.3 MHz operation, and the signal 712 is output.
Becomes “1” indicating the connection between the bus section 211 and the bus section 212.

The clock generating means 31 shown in FIG. 1 switches the operating frequency according to the frequency identification information 711.
When the frequency identification information 711 is “1”, the output 311 is set to 6
6.6 MHz, and when "0", output 311 is 33.3.
MHz. The bus section connection control signal 712 controls the bus switch 79.

The register 95 shown in FIG. 5 is a register that can be accessed by software.
14. A register that stores the levels of the signals 521 to 524 and is read from the CPU. The register 96
Is a register that stores the levels of the signals 921 and 941 and is read from the CPU. Note that these registers 95 and 96 are provided in the control unit 71 so as to be readable from the CPU.

The display lamps 991 to 991 as the lighting means in FIG.
Reference numeral 994 corresponds to the slots 401 to 404 and lights up when the following conditional expressions [f1] to [f4] are satisfied, respectively, indicating that an expansion card having an upper limit frequency of 66.6 MHz is mounted.

Conditional expression [f1] {(card detection signal 511 = "1") AND (card frequency information 521 = "1")} Conditional expression [f2] {(card detection signal 512 = "1") AND (card (Frequency information 522 = “1”)｝ conditional expression [f3] {(card detection signal 513 = “1”) AND (card frequency information 523 = “1”)} conditional expression [f4] {(card detection signal 514 = “ 1 ") AND (card frequency information 524 =" 1 ")}

The display lamp 98 as the lighting means shown in FIG.
5 is lit when the frequency identification information 711 is “1”,
The operating frequency of the CI bus 201 (section 211) is 66.6
MHz to the user.

FIG. 6 is a timing chart for explaining an operation example during power-on processing in the information processing apparatus according to one embodiment of the present invention, and FIG. 7 is another timing chart during power-on processing in the information processing apparatus according to the embodiment of the present invention. 5 is a timing chart illustrating an operation example. Next, according to these timing charts, the power supply is turned on and the PCI bus 201 (section 2) is turned on.
11, 212) will be described. First, FIG.
A case in which an expansion card having an upper limit operation frequency of 66.6 MHz is inserted into the slot 401 and the slots 402 to 404 are not mounted will be described with reference to FIG.

At time T0, the main power supply 9
When 90 is inserted, at time T01 immediately after the insertion,
Hereinafter, the initial state will be described as states [g1] to [g7]. The initial state does not use the hot plug function,
Slots 401 to 404 are assigned to bus sections (211 and 212)
Connected. Note that FIG.
Only the signal corresponding to 01 is described.

State [g1] The frequency switching means 93 shown in FIG. 4 sets the frequency identification information 711 to “0” and indicates an operation at 33.3 MHz. The frequency switching means 93 sets the bus section connection control signal 712 to “1”. As a result, the bus switch 79 in FIG. 1 is turned on, and the PCI bus section 211 and the section 212 are connected.

State [g2] The hot plug control means 731 to 734 shown in FIG. 3 sets the control signals 811 to 814 to "1". As a result, the bus switches 611 to 614 shown in FIG.
212.

State [g3] The hot plug control means 731 to 734 shown in FIG. 3 sets the signals 821 to 824 to "1". Thus, the switches 621 to 624 shown in FIG. 1 are turned on, and the clock signals 321 to 324 are supplied to the slots 401 to 404.

State [g4] The hot plug control means 731 to 734 shown in FIG. 3 sets the control signals 831 to 834 to "1". Thereby, the switches 621 to 624 shown in FIG. 1 are turned on, and the slot power supplies 491 to 494 are turned on.

State [g5] The hot plug control means 731 to 734 output the control signal 84
1 to 844 are set to “0”, and the switches 641 to 64 in FIG.
4 is turned off.

State [g6] The hot plug control means 731 to 734 set the reset signals 441 to 444 to "0".

State [g7] The holding means 94 shown in FIG.
It is set to “0” corresponding to Hz.

Time point T0 when the initial state is set as described above.
1, since the card is inserted into the slot 401 of FIG. 1, the PRSNT1, 2 # signal 411,
421 is determined. In the example shown in FIG. 6, the values of these signals are “0” and “0” due to the current consumption value of the card. As a result, the card detection signal 511 shown in FIG.
Changes from “0” to “1” at time T02.

Although not shown in FIG. 6, the PRSNT1, 2 # signals 412-414, 422-424 corresponding to the slots 402-404 shown in FIG. 1 are "1" because the card is not mounted. . Therefore, at the same time as the time point T02, the card detection signals 512 to 514 become “0” indicating that the card is not mounted.

The upper limit operating frequency of the expansion card inserted into the slot 401 is 66.6 MHz.
Since the switch 641 is OFF in the initial state [g5], the M66EN # signal 431 corresponding to the slot 401 becomes “1”.

On the other hand, since the reset signal 441 is "0" in the initial state [g6], the selecting means 751 of the card frequency information detecting means 721 shown in FIG.
# The level "1" of the signal 431 is set to the card frequency information 521
521. Therefore, at the time T03, the card frequency information 521 changes from “0” to “1”.

When the main power supply 990 is turned on, the frequency switching means 93 shown in FIG. In the example described, the frequency identification information 921 is “1”, and the output 941 of the holding unit 94 is “0”, which indicates that the operating frequency is switched from 33.3 MHz to 66.6 MHz. . Therefore, at time T05, the frequency switching unit 93 changes the frequency identification information 711 from “0” to “1”. As a result, at time T06, the output 311 of the frequency generation unit 31 becomes 33.3 MHz.
To 66.6 MHz.

At the time T05, the frequency switching means 93 changes the bus section connection control signal 712 from "1" to "0". As a result, the bus switch 79 shown in FIG. 1 is turned off, and the PCI bus sections 211 and 212 shown in FIG. 1 are cut off.

At time T07, which is a fixed period after time T05, frequency switching means 93 in FIG.
, A pulse notifying that the frequency switching has been completed is generated, and the signal 931 changes from “0” to “1”. The width of the pulse is set to a sufficiently long interval with respect to the subsequent time points T08 to T09 and is set to about 1 to 5 seconds. As a result, the holding unit 94 holds the level “1” of the signal 921, and the output 941 of the holding unit changes from “0” to “1” as shown in FIG.

At time T07 shown in FIG.
Since 1 has changed from “0” to “1”, the hot plug control unit 731 shown in FIG. 3 executes the function [c1] described above. And the frequency identification information 711 is 66.6 MH
Since it is “1” indicating the z operation, the time T08 shown in FIG.
, The signal 841 is set to “0”. As a result, the switch 641 is turned off and the M6 of the slot 401 is turned off.
The 6EN # signal 431 becomes “1” corresponding to the operation frequency of 66.6... MHz in the PCI bus section 211.

At time T09, hot plug control means 731 changes reset signal 413 from "0" to "1".

After time T03, the display lamp 991 as the lighting means shown in FIG. 1 is turned on to indicate that the card inserted into the slot 401 is a 66.6 MHz card.
, And the display lamps 992 to 994 are turned off.
Further, after time T05, the display lamp 985, which is the lighting means shown in FIG. 1, becomes "lit" indicating the operation of 66.6 MHz. Thus, the upper limit operating frequency of the expansion card installed in the slot 401 is 66.6 MHz, and the PCI
The operating frequency of the bus 201 (section 211) is 66.6 MH
The user is notified that it is z.

Thereafter, the CPU 20 shown in FIG.
The initialization code loaded from S28 is executed, the OS is started from the hard disk 26, and the information processing apparatus is brought into an operating state.

Next, an operation example different from that described above will be described with reference to FIG. The example shown in FIG. 7 is an operation example in which an expansion card having an upper limit operation frequency of 66.6 MHz is inserted into the slots 401 and 403 when the power is turned on, and the slots 402 and 404 are not mounted.

At time T0, the main power supply 9
When the power switch 90 is turned on, at a time point T11 immediately after the power is turned on, the startup states [g1] to [g7] similar to those described above.
Becomes Also, at this time T11, PRSNT
1, 2 # signals 411, 421, 413, and 423 are determined. In the example shown in FIG. 7, the values of these signals are “0”, “0”, “0”, “0” due to the current consumption value of the card. As a result, at time T12 shown in FIG. 7, the card detection signals 511 and 513 shown in FIG. 3 become "1" indicating the mounting. Although not shown in FIG. 7, at time T11, the values of the mounting information 412, 414, 422, and 424 corresponding to the slots 402 and 404 are "1" and "1" because the card is not mounted. , “1”,
It is "1". Therefore, at time T12, the values of the card detection signals 512 and 514 shown in FIG. 3 are “0” and “0” indicating that the card is not mounted.

The upper limit operation frequency of the expansion card installed in the slots 401 and 403 is 66.6 MHz, and the switches 641 and 6 are set according to the initial state [g5].
43 is in the OFF state, the M66EN corresponding to the slots 401 and 403 at time T11 shown in FIG.
The # signals 431 and 433 are "1" and "1".

On the other hand, since the reset signals 441 and 443 are "0" in the initial state [g6], the card frequency information detecting means 721 and 723 shown in FIG.
The levels “1” and “1” of the # signals 431 and 433 are output to the card frequency information 521 and 523. Therefore, FIG.
At time T13 shown in FIG.
523 changes from “0” to “1”.

The frequency selecting means 92 shown in FIG.
From the signals 11 to 514 and the signals 521 to 524, the frequency information 921 is determined according to the rule shown in Table 1 already described. In this case, to correspond to the number 10 in Table 1, at time T14 shown in FIG.
It becomes "0" indicating 3.3 MHz operation.

When the main power supply 990 is turned on, the frequency switching means 93 of FIG.
The switching of the frequency is determined without depending on the access of the T.30. In this case, since the frequency identification information 921 is “0” and the output 941 of the holding unit 94 is “0”, 33.3 MH
This corresponds to switching from z to 33.3 MHz, and switching of the bus frequency is not performed. Therefore, at time T15 shown in FIG. 7, the frequency identification information 711 is “0”, and the level of the bus section connection control signal 712 is “1”.

At the subsequent time point T16, the frequency switching means 93 shown in FIG. 4 generates a pulse for notifying the signal 931 that the frequency switching has been completed. In the example shown in FIG. 7, only the timing T16 is described, and the signal 93
1 is not described. As a result, the holding unit 94 holds the level “0” of the signal 921, and the holding unit output 941 shown in FIG. 7 becomes “0”.

At time T16 shown in FIG.
1, the hot plug control means 731 and 733 of FIG. 3 execute the function [b1] described above. Since the frequency identification information 711 is “0”, the hot plug control units 731 and 733 determine at time T17
The signals 841 and 843 are changed from “0” to “1”. As a result, the switches 641 and 643 are turned on, and the M66EN # signal 431 of the slot 401 and the slot 403
The M66EN # signal 433 becomes “0” corresponding to the operating frequency of 33.3 MHz in the PCI bus section 211.

At time T18, the hot plug control means 731 and 733 change the reset signals 431 and 433 from "0" to "1".

After the time T13, the display lamps 981 and 983 as the lighting means shown in FIG. 1 are turned on to indicate the 66.6 MHz card, and the display lamp 98 as the lighting means is turned on.
2, 984 is "lights out". After time T11,
The display lamp 985 which is the lighting means shown in FIG.
It turns "off" indicating 3 MHz operation. As a result, despite the fact that the upper limit operating frequency of the expansion cards installed in the slots 401 and 403 is 66.6 MHz, the PCI
The operating frequency of the bus 201 (sections 211 and 212) is 3
At 3.3 MHz, the user is notified that the expansion card in use is not operating at the upper limit operating frequency.

When an upper limit operation frequency 66.6 MHz card is used in the slot 403 due to a user's erroneous operation,
As described above, the user can know the erroneous operation, and the user can shut off the main power supply 990 and change the configuration of the expansion card. When the user wants to install the expansion card as described above, the PCI bus 201 (sections 211 and 212) operates at 33.3 MHz, and then the CPU 20 shown in FIG. Execute the conversion code and
Activate S, and the information processing apparatus enters an operating state.

The operation of the embodiment of the present invention described with reference to FIG. 6 and FIG. 7 detects the card mounting state of the slots 401 to 404 when the power is turned on, and determines the PCI bus operating frequency and the PC bus operating frequency.
Although the switching between the I bus sections 211 and 212 is performed,
The above-described function is also effective when hot-swapping the PCI bus during system startup.

The hot-swap function of the PCI bus (PCI hot-plug function) requires dynamic management of hardware resources such as initialization of an inserted expansion card and allocation of memory and I / O space. . Usually, these processes are performed by a service, a driver, or the like on an OS (operating system).

In order to realize the above-mentioned functions of the present invention,
Although the change of the PCI hot plug processing procedure by these software is involved, in recent years, the function of the OS is modularized, and the service for managing the PCI hot plug function is partially changed, and the control unit 71 is controlled. Addition of a driver and the like can be realized relatively easily.

FIGS. 8 and 9 are flow charts for explaining the processing operation of the OS at the time of PCI hot insertion and removal, FIGS. 10 and 11 are timing charts for explaining a processing example at the time of hot insertion, and FIG. FIG. 13 is a flowchart for explaining a processing operation at the time of addition, and FIG. 13 is a flowchart for explaining a processing operation at the time of removing an expansion card. These will be described below. It should be noted that in FIGS. 8, 9, 12, and 13,
The dotted line indicates the processing by the hardware shown in FIGS. 1 to 5 instead of the processing of the OS, and the processing of the driver and the service on the OS is collectively described as the processing of the OS.

The hot-swap controller is a CPU 2 shown in FIG.
0, the aforementioned OS, hot plug control means 73 shown in FIG.
1 to 734. Also, the CPU 2 of FIG.
0, the OS, the CRT controller 24 and the CRT monitor 241 constitute a warning display unit in the information processing apparatus of the present invention.

Expansion card addition processing FB0 shown in FIG.
0 and the processing operations of FIGS. 8 and 9 included in this processing will be described below.

(1) The user can use the slots 401 to 404
The new expansion card is inserted into the non-installed slot, and the slot is notified to the OS of the added card. In the following description, the slots 401 to 401
Of the 404, the slot to which the user has added the expansion card is called a group 971, and the slot already in the installed state and the expansion card is in operation is called a group 972. In addition, in the expansion card addition process, the group 9
The mounting state in which the group 71 and the group 972 are combined is called a new card mounting state. The instruction of the group 971 by the user is performed by input from the keyboard 251 shown in FIG. 1, but the method of notifying the CPU 20 of FIG. 1 of the results by the card attachment detecting means 51 to 54 shown in FIG. (Step FB01).

(2) The OS responds to the command registers 911 to 914 of FIG.
The power-on command [Z32-3] is written (step FB02).

(3) The hot plug control means 731 to 31 in which the command register in the control unit 71 shown in FIG.
734 turns on the power supply 491 to 494 of the corresponding slot (step FB03).

(4) Next, a subroutine FA shown in FIG.
Execute 00. This subroutine FA00 is for switching the PCI bus frequency according to the present invention,
Switch. In the aforementioned step FB03,
When the power supply of the group 971 is turned on, the card detection units 51 to 54 and the card frequency information detection units 721 to 724 of FIG. 3 change the card detection signals 511 to 514 and the card frequency information 521 to 524
And the frequency determination means 92 of FIG.
The frequency determination result 921 according to the newly attached state is output (step FB04).

(5) The OS reads the register 96 shown in FIG. 5, and compares the level of the signal 921 read from the register 96 with the level of the signal 941. As a result of this comparison, if the two match, in the newly mounted state, the PC
This indicates that the switching of the I bus frequency is unnecessary. At this time, the subroutine process FA00 ends, and the process proceeds to the process of step FB05 shown in FIG. 12 described later (steps FA01, FA02, and FA31).

(6) If the two do not match in the comparison process in step FA02, it indicates that the PCI bus frequency needs to be switched, and the OS sends the message in the message list shown in Table 2. 1. Display "Change the operating frequency of the PCI bus." And notify the user that the PCI bus frequency needs to be switched. FA
At 04, the OS notifies the user of the current operating frequency and the frequency of the newly mounted state (after switching). The display contents are, for example, as shown in Table 3 (steps FA03 and FA04).

[0133]

[Table 2]

[0134]

[Table 3]

(7) Next, the OS proceeds to step FA0
In step 1, the level of the signal 921 is determined from the register 96 read. As a result, when the level of the signal 921 is “1”, the operating frequency of the PCI bus is 33.3 MH.
z corresponds to switching to 66.6 MHz.
S is message 2 in the message list shown in Table 2.
"When the PCI bus operates at 66 MHz, the slot 403,
404 cannot be used. Is displayed, the flow branches to the processing of step FA11 described later (steps FA05 and FA05).
A06).

(8) In step FA05, the signal 9
When the level of the PCI bus 21 is “0”, the operating frequency of the PCI bus in the newly mounted state is changed from 66.6 MHz to 3
Since this corresponds to 3.3 MHz switching, the OS
Is read (step FA0).
7).

(9) Next, the OS sets the slots 401-4
04, a card corresponding to 33.3 MHz is detected.
Specifically, the following logical expression [h1] is evaluated based on the levels of the card mounted state detection signals 513 to 514 in the register 95, and whether a 33.3 MHz compatible card is inserted in the slots 401 to 404 is determined. It is detected whether or not it is (step FA08).

Logical expression [h1] {(card frequency information 521 = "0") AND (card detection signal 511 = "1")} OR {(card frequency information 522 =
"0") AND (card detection signal 512 = "1")} OR
{(Card frequency information 523 = "0") AND (card detection signal 513 = "1")} OR {(card frequency information 524 =
"0") AND (card detection signal 514 = "1")}

(10) The logical expression [h] at step FA08
1], when the evaluation value is “1”, the slots 401 to 401
Reference numeral 404 indicates that a card having an upper limit operating frequency of 33.3 MHz is inserted. In this case, message 3 in the message list shown in Table 2 "A 33 MHz compatible card is used. If a PCI bus 66 MHz operation is desired, 66M is set in slots 401 and 402.
Hz expansion card is inserted, and slots 403 and 40 are inserted.
4 must not be mounted. Is displayed, and it is confirmed whether or not the switching from the operating frequency of the PCI bus from 66.6 MHz to 33.3 MHz is intended by the user (step FA09).

(11) The logical expression [h] at step FA08
When the evaluation value is “0” in the evaluation of [1], the slots 401 to 401
All expansion cards of 404 have an upper limit operating frequency of 66.6M.
Hz. Also, signal 9 shown in Table 1
Referring to the determination rule 21, this corresponds to a state where an expansion card is inserted into either the slot 403 or the slot 404. Therefore, in this case, message 4 “slots 403 and 404
6MHz compatible card is inserted. PCI bus 6
If a 6 MHz operation is desired, slots 401, 4
Please insert a 66MHz compatible expansion card in 02 and do not mount the slots 403 and 404. Is displayed and P
CI bus operating frequency from 66.6 MHz to 33.3 ... M
It is confirmed whether the switching of Hz is intended by the user (step FA10).

(12) Steps FA06, FA09, FA
In step 10, after displaying messages 1, 3, and 4, message 5 "Change the insertion position of the expansion card?" In the message list shown in Table 2 is displayed, and the user accepts the newly installed state. Inquire whether to do. O
In S, the input from the keyboard 261 shown in FIG. 1 is determined, and if the user accepts the new mounting state, the process proceeds to step FA32 to go to the subroutine FA00.
(Steps FA11, FA12, FA
32).

(13) If it is determined in step FA12 that the user has not accepted the newly mounted state, the flow shifts to the processing of the flow shown in FIG. Steps FA12 to FA12 in FIG.
In the process of the FA 18, the group 972 is temporarily disconnected from the PCI bus sections 211 and 212 to switch the bus frequency to a reset state. As a result, the group 97
Since all the volatile information of the card connected to 2 is lost, the OS first saves the volatile information in the main memory or the hard disk. This process is the same as the conventional plug-off process. Specifically, it is to save the data of the RAM mounted on the expansion card and the register information of the LSI (step FA13).

(14) The OS writes the plug-off command [Z32-2] to the command registers 911 to 914 shown in FIG. 3 corresponding to the group 972. Then, the hot plug control means 731 to 734 into which the command register in the control unit 71 shown in FIG. 3 is written performs a plug-off operation for the corresponding slot (steps FA14 and FA15).

(15) Next, the OS writes to the register 930 shown in FIG.
Of the PCI bus operating frequency. Thereby, the frequency switching control unit 93 shown in FIG. 4 switches the frequency identification information 711 and the signal 712 according to the level of the determination result 921. This rule is based on [e1],
It is the same as [e2]. Thereby, the output frequency of the clock generating means 31 is changed (steps FA16, FA16).
A17).

(16) After the clock signal is stabilized, the OS
Writes the plug-on command [Z32-1] into the command registers 911 to 914 shown in FIG. 3 corresponding to the group 972. The hot plug control means 731 to 734 having written into the command register in the control unit 71 shown in FIG. 3 perform a plug-on operation for the corresponding slot (steps FA18 and FA19).

(17) For the expansion card inserted into the group 972, the OS again sets the information saved at step FA13. Also, the expansion card is initialized as necessary. Thus, the subroutine FA00 ends (steps FA20 and FA31).

(18) The processing of the subroutine FA00 in step FB04 in FIG.
It has an end path to 32. In the case of termination via the path FA32, the card inserted into the group 971 does not perform the PCI bus plug-on processing, and the power of the slot is cut off so that the user can insert and remove the card again. Therefore, the OS writes the power shutdown command [Z32-4] to the command registers 911 to 914 shown in FIG. 3 corresponding to the group 971. Then, the hot plug control means 731 to 734 in which the command register in the control unit 71 shown in FIG. 3 has been written shuts off the power supplies 491 to 494 of the corresponding slot, and enables the user to remove the card ( Steps FB06 and FB07).

(19) On the other hand, when the processing is terminated by the route FA31, the plug-on processing according to the prior art is performed for the group 971. The OS writes the plug-on command [Z32-1] into the command registers 911 to 914 shown in FIG. Then, the hot plug control means 731 to 734 having written in the command register in the control unit 71 shown in FIG. 3 perform the plug-on operation for the corresponding slot. Then the OS
Performs initialization of the expansion card inserted into the group 971, and allocation of resources such as a memory and an interrupt in order to cooperate with the OS.

Next, the processing operation of the processing FC00 when removing the expansion card will be described with reference to the flow shown in FIG.

(1) The user can use the slots 401 to 404
The OS is notified which of the slots is to be removed. In the following description, the slots 401 to 401
Of the slots 404, the slot from which the user desires to remove the card is called a group 971, and the slot from which the card is not removed is called a group 972. In the expansion card removal process FC00, the mounted state of the group 972 is referred to as a new card mounted state (step FC01).

(2) Next, plug-off processing according to the prior art is performed on the group 971. Although a detailed description is omitted because of a known technique, the OS writes the plug-off command [Z32-2] to the command registers 911 to 914 illustrated in FIG.
The hot plug control means 731 to 734 in which the command register in the control unit 71 shown in FIG. 3 has been written performs a plug-off operation for the corresponding slot. Also, prior to the plug-off operation, the OS does not hinder the operation of the OS by removing the expansion card, such as saving the data of the RAM mounted on the expansion card inserted into the group 971 and the register information of the LSI to the hard disk. (Step FC02).

(3) The OS writes the power shutdown command [Z32-4] to the command registers 911 to 914 shown in FIG. 3 corresponding to the group 971. Then, the hot plug control means 731 to 734 in which the command register in the control unit 71 shown in FIG. 3 has been written performs power cutoff for the corresponding slot (step FC0).
3, FC04).

(4) Thereafter, the card can be removed by the user. When the card is removed, the subroutine FA00 described above is executed. The process is the same,
Description is omitted. Unlike the process FB00 at the time of card addition, the process FC00 at the time of card removal is 66.6M
There is no branch that switches from Hz to 33.3 MHz. Therefore, the processing of steps FA07 to FA10 in subroutine FA00 is not executed.
When the user branches from the step FA12 to the end path FA32 and the change of the PCI operating frequency is not permitted by the user, the bus section (201, 202) operates at 33.3 MHz (steps FC05, FC06).

Next, an example of the operation in the process at the time of hot-line insertion will be described with reference to FIGS. FIG. 10, FIG.
In the example shown in FIG.
This is an example in which a 6 MHz expansion card is inserted and a user inserts a card having an upper limit operation frequency of 33.3 MHz into the slot 403, and the slots 402 and 404 are not mounted. Also, the correspondence between FIGS. 8, 9 and 12 will be described together. The slot 403 corresponds to the group 971 in the slot insertion processing FA00 described above.
The slot 401 corresponds to the group 972.

In FIG. 10, the signal state at time T30 in the initial state is such that the frequency identification information 711 is 66.6M.
Hz indicating “1”, and the slot 401 has 66.6.
MHz bus clock is supplied. The output 941 of the holding means is “1”, the bus section control signal 712 is “0”, and the PCI bus sections 211 and 212 are electrically disconnected. Further, the signal of the slot 401 has the same signal level after the time T09 described with reference to FIG.

At time T31, when the user
It is assumed that an expansion card is inserted into the 03. The OS performs processing according to steps FB01 to FB03 of the flow shown in FIG. Although not shown in FIG. 10, at time T31, the hot plug unit 731 of FIG. 3 changes the signal 833 from “0” to “1” and the switch 633 is connected, so the slot power supply 493 is turned on. .

Immediately after the time point T31, since the signal 813 is "0", the bus switch 613 is in the cut-off state.
The slot 401 is not connected to the bus section 212. Further, since the signal 823 is “0”, the switch 633 is in the cut-off connection state, and the clock of the slot 403 is in the stop state. The reset signal 443 of the slot signal is “0”. In the examples shown in FIGS. 10 and 11, the PRSNT1, 2 # signals 413 and 423 are "0" and "0" due to the current consumption of the card. Also, the signal 843 is “0”, so that the M66EN # signal 433
03, the upper limit operating frequency of the expansion card inserted in 33.3
The level becomes "0" according to MHz.

At the subsequent time point T32, the above-mentioned function [b
1], the signal 511 shown in FIG. 3 becomes “1”, and the signal 521 becomes “1” by the function [b2] described above. On the other hand, although not shown in FIG.
4 are signals 512 and 51 because the card is not mounted.
4 is "0".

At time T33, the frequency selecting means 92 shown in FIG. 4 outputs signals 511-514 and signals 521-52.
4, frequency information 921 is determined according to the rules shown in Table 1. In this case, in order to correspond to the number 11 in Table 1, at time T33, the frequency identification information 921 is 66.6M.
The frequency changes from "1" indicating the Hz operation to "0" indicating the 33.3 MHz operation.

On the other hand, the OS executes a subroutine FA00 shown in FIGS. The OS proceeds to step FA01,
The register 96 is read by the processing of FA02. The level of the signal 921 is “0”, and the level of the signal 941 is “1”.
Therefore, the result of determination in step FA02 does not match, and the flow branches to the subsequent steps FA03 and FA04.

The OS displays message 1 in the message list shown in Table 2, and further displays message 1 in Table 3 to indicate that the user needs to change the operating frequency of the PCI bus. Notice. Step FA0
At 5, since the signal level 921 is "0", the process branches to the subsequent process of step FA08.

In the evaluation process of the evaluation formula in step FA08,
Since the evaluation expression [h1] is “1”, steps FA09 to FA09
The process branches to A11 to sequentially display the messages 3 and 5 in the message list shown in Table 2.

In the example described, since the user has inserted a card having an upper limit operating frequency of 33.3 MHz into the slot 403, the user inputs in the processing of step FA12 that he does not wish to change the card insertion. . Therefore, the processing shifts to the flow shown in FIG.

The OS executes the processing of steps FA13 to FA15.
The plug-off command is written in the register 911 corresponding to “1”. As a result, in the section T34 shown in FIG. 10, the signals 811 to 841 become “0”. Signal 811
The switching from to 841 is performed at a timing based on the PCI specification.

In the processing of step FA16, the OS
Writes to the register 930. For this reason, in step FA17, the frequency switching control means 93
According to the states [e1] and [e2] described above, the signal 711,
712 is output. As a result, at time T35 in FIG. 11, the signal 711 changes from “1” to “0”, and the signal 712 changes from “0” to “1”. At time T36,
The operating frequency switches from 66.6 MHz to 33.3 MHz.

At the subsequent time point T37, the frequency switching means 93 shown in FIG. 4 generates a pulse for notifying the signal 931 that the frequency switching has been completed. In the drawing, only the timing T37 is shown, and the signal 931 is not shown. Thereby, the frequency switching control means 93
Changes the signal 941 from “1” to “0”. Also, at time T38, the hot plug control means 731 and 733
Since the level of the signal 711 is "0", the signal 841,
842 is set to “0”. As a result, the switches 641, 6
43 is in the ON state, and M66EN # of the slot 401
Signal 431 and M66EN # signal 43 in slot 403
3 is the operating frequency of the PCI bus section 211 of 33.3 MH.
It becomes "0" corresponding to the z operation.

The OS executes step FA in the flow shown in FIG.
18 to FA 20 are executed to perform the plug-in processing of the slot 401. As a result, at time T39 shown in FIG. 11, the signals 811, 821, 841 become "1". Switching of the signals 811 to 841 is performed at a timing based on the PCI specification.

The OS transfers the subroutine FA00 to the route FA
Then, the plug-in processing of the slot 403 is performed by the processing of step FB05 in the flow shown in FIG. As a result, at time T39, signal 8
31, 832 and 834 become "1". Signals 831 to 8
The switching of 34 is performed at a timing based on the PCI specification.

According to the above-described embodiment of the present invention, the PCI bus is divided into two bus sections, and the upper limit operating frequency of the expansion card inserted in the slot connected to these buses;
The operating frequency of the bus is switched depending on the number of expansion cards (the number of loads) and the mounting position of the card.
The essence of the present invention is to switch the operating frequency of the bus depending on the upper limit operating frequency of the expansion card electrically connected to the single-segment bus, the number of expansion cards mounted (the number of loads), and the card mounting position. It is in.

The frequency determining means used in the present invention permits the operation at the higher bus operating frequency only when the combination of the number of expansion cards and the card mounting position is in a specific state. This combination is set in advance so as to minimize electrical signal delay and waveform distortion when designing the information processing apparatus.

FIG. 14 is a block diagram showing the configuration of an information processing apparatus according to another embodiment of the present invention, and FIG. 15 illustrates the arrangement of main components and the bus wiring shape of the information processing apparatus according to another embodiment of the present invention. FIG. In FIGS. 14 and 15, reference numeral 213 ′ denotes a PCI bus, and other reference numerals are used in FIG.
This is the same as in FIG.

The information processing apparatus described with reference to FIG.
The bus switch 79 is inserted between the I bus sections 211 and 212, and when the PCI bus operates at 66.6 MHz, the bus switch 79 is turned off, and the influence of the capacitive load of the bus section 212 and the slots 403 and 404 is provided. Was minimized.

An information processing apparatus according to another embodiment of the present invention shown in FIG. 14 is applied to a case where the total line length of a bus is relatively short. Slots 401 to 404 correspond to a single bus section 213 '. It is connected. As shown in FIG. 15, the memory / I / O controller 21, the control unit 71, the bus switch 611, the bus switch 612, the bus switch 613, and the bus switch 614 are provided on the bus 213 '.
Are wired in the shortest order in this order. The wiring length from the memory / I / O controller 21 to the bus switch 612 is approximately 200 mm or less, and preferably 150 mm or less. Also, the bus switch 612 to the bus switch 61
The wiring length reaching 4 is set to about 60 mm or less.

The embodiment of the present invention thus configured has a bus operating frequency of 33.3 MHz when the power is turned on and when a hot-plug is inserted / removed, similarly to the information processing apparatus described with reference to FIG.
Switching between z and 66.6 MHz is performed. The functions of each part,
Detailed processing procedures are the same as those shown in FIGS. 3 to 1 except that the bus switch 79 and the control signal 712 shown in FIG. 1 are not used.
3, the same as described in Tables 1 to 3.

That is, the embodiment of the present invention shown in FIG. 14 uses the slots 401 and 402 close to the memory / I / O controller when the PCI bus operates at 66.6 MHz, while the slots 403 and 404 Leave unconnected. As a result, the total value of the capacitive loads connected to the bus section 213 'is limited, and the slots in which expansion cards are mounted are limited, so that signal delay and waveform distortion can be minimized.

As described above, the present invention has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and may be modified without departing from the scope of the invention.
Various changes can be made without departing from the spirit and scope defined in the claims. Hereinafter, the above-mentioned changed items will be disclosed.

(1) At least one or more expansion cards, a bus, at least two or more expansion card connecting means connected to the bus, and at least two for detecting the presence or absence of an expansion card of the expansion card connecting means. At least two or more card mounting detecting means, at least two or more card frequency information detecting means for detecting an upper limit operating frequency of an expansion card mounted on the expansion card connecting means, a bus clock supplying means, a frequency determining means, An information processing apparatus comprising frequency switching control means.

(2) In the information processing apparatus according to the item (1), the bus clock supply means connects the bus clock of one of a first frequency and a second frequency lower than the first frequency to an expansion card. Supply means, the expansion card connection means is divided into first and second groups, and the frequency determination means determines frequency identification information based on a detection result of the card detection means and a detection result of the card frequency information detection means. Output, when the information processing apparatus is powered on, all the expansion card connection means of the second group are not mounted, and expansion cards are mounted on any of the expansion card connection means of the first group. The first identification value is output when the upper limit operation frequencies of all the expansion cards are equal to or higher than the first frequency, and the second identification value is output when the information processing apparatus is powered on. When an expansion card is attached to any of the expansion card connection units connected to the bus section, the second identification value is output, and the frequency switching control unit determines that the frequency identification information is the first identification value. When the output clock from the bus clock supply unit is the first frequency, when the frequency identification information is the second identification value, the output clock from the bus clock supply unit is the second frequency. An information processing apparatus, comprising:

(3) In the information processing apparatus according to the item (2), the expansion card connecting means is constituted by a slot conforming to the PCI specification, the first frequency is approximately 66 MHz, and the second frequency is approximately 33 MHz. An information processing apparatus characterized by the following.

(4) At least one or more expansion cards, a bus, at least two or more expansion card connecting means connected to the bus, and at least two for detecting the presence or absence of an expansion card of the expansion card connecting means. At least two or more card mounting detecting means, at least two or more card frequency information detecting means for detecting an upper limit operating frequency of an expansion card mounted on the expansion card connecting means, a bus clock supplying means, a frequency determining means, An information processing apparatus comprising: frequency switching control means; hot-plug insertion / extraction control means; and display means.

(5) In the information processing apparatus according to the item (4), the bus clock supply means may include a bus clock having one of a first frequency and a second frequency lower than the first frequency. Supply to the connection means, the expansion card connection means is divided into a first group and a second group, and the stopcock insertion / removal control means sets the first point in time when the expansion card is inserted while the information processing apparatus is energized. , The switch means of the expansion card connection means in which the expansion card is newly inserted is turned off, and at the fourth time point following the third time point described later, the expansion card in which the expansion card is newly inserted is set. The switch means of the connection means is set to the connection state, and the frequency determination means determines the detection result of the card detection means and the detection result of the card frequency information detection means at a second time following the first time. The frequency identification information is output according to the output result, and after the expansion card is inserted by the user, all the expansion card connection means connected to the second group are not mounted, and are connected to the first group. When an expansion card is attached to any of the expansion card connection means and the upper limit operating frequencies of all the expansion cards are equal to or higher than the first frequency, a first identification value is output. When an expansion card is attached to any of the expansion card connection units connected to the second bus section after the expansion card is inserted, the second identification value is output, and the frequency switching control unit outputs the second identification value. At a third point in time following when the frequency identification information is a first identification value,
An output clock from the bus clock supply unit is set to the first frequency, and when the frequency identification information is a second identification value, an output clock from the bus clock supply unit is set to the second frequency. An information processing apparatus characterized by the above-mentioned.

(6) In the information processing apparatus as set forth in (5), the expansion card connection means comprises a slot conforming to the PCI specification, and a switch means for connecting the card slot to the first bus section. The frequency of 1 is about 6
An information information processing apparatus characterized in that 6 MHz and the second frequency are approximately 33 MHz.

(7) At least one or more expansion cards, a first bus section, a second bus section, bus control means connected to the first bus section, and the first bus section First switch means for connecting the first bus to the second bus section, at least one or more expansion card connection means connected to the first bus, and at least one expansion card connection means connected to the second bus The above expansion card connection means, at least two or more card installation detection means for detecting the presence or absence of an expansion card in the expansion card connection means, and detecting the upper limit operation frequency of the expansion card mounted on the expansion card connection means An information processing apparatus comprising at least two or more card frequency information detecting means, a bus clock supplying means, a frequency determining means, and a frequency switching control means.

(8) In the information processing apparatus according to the item (7), the bus clock supply means may supply the bus clock having any one of a first frequency and a second frequency lower than the first frequency. Supply to the expansion card connection means,
The frequency determination unit outputs frequency identification information based on the detection result of the card detection unit and the detection result of the card frequency information detection unit.
All expansion card connection means connected to the second bus section are not mounted, and expansion cards are mounted to any of the expansion card connection means connected to the first bus section; and Outputting a first identification value when the upper limit operating frequencies of all expansion cards are equal to or higher than the first frequency;
On the other hand, when the information processing apparatus is powered on, if an expansion card is attached to any of the expansion card connection means connected to the second bus section, the second identification value is output and the frequency switching control is performed. The means may be configured such that the frequency identification information is a first
In the case of the identification value, the output clock from the bus clock supply unit is set to the first frequency, and the first switch unit is turned off. On the other hand, when the frequency identification information is the second identification value, An information processing apparatus, wherein an output clock from the bus clock supply unit is set to the second frequency, and the first switch unit is connected.

(9) In the information processing apparatus according to the item (8), the expansion card connecting means is constituted by a slot conforming to a PCI specification, and the first frequency is approximately 66 MHz.
z, and the second frequency is approximately 33 MHz.

(10) At least one or more expansion cards, a first bus section, a second bus section, bus control means connected to the first bus section, and the first bus section. First switch means for connecting to the second bus section;
At least one or more expansion card connection means connected to the first bus, at least one or more expansion card connection means connected to the second bus, and an expansion card of the expansion card connection means At least two to detect the presence
At least two or more card mounting detecting means, at least two or more card frequency information detecting means for detecting an upper limit operating frequency of an expansion card mounted on the expansion card connecting means, a bus clock supplying means, a frequency determining means, An information processing apparatus comprising: frequency switching control means; hot-plug insertion / extraction control means; and display means.

(11) In the information processing apparatus according to the item (10), the bus clock supply means may supply the bus clock having any one of a first frequency and a second frequency lower than the first frequency. Supply to the expansion card connection means,
When the expansion card is inserted while the information processing apparatus is energized, the stopcock insertion / removal control means sets the switch means of the expansion card connection means into which the expansion card is newly inserted at the first point in time, and At a fourth point in time following a third point described later, the switch of the expansion card connecting unit in which the expansion card is newly inserted is set to the connection state, and the frequency determination unit determines the second point following the first point in time. At the point of time, the frequency identification information is output based on the detection result of the card detection means and the detection result of the card frequency information detection means, and after the user inserts the expansion card, all expansion cards connected to the second bus section The connection means is not mounted, and an expansion card is mounted on any of the expansion card connection means connected to the first bus section. When the upper limit operating frequency of the memory card is equal to or higher than the first frequency, a first identification value is output. On the other hand, after the expansion card is inserted by the user, any one of the expansion card connection means connected to the second bus section is output. When an expansion card is installed, a second identification value is output, and the frequency switching control unit determines whether the frequency identification information is a first identification value at a third time point following the second time point. Setting the output clock from the bus clock supply means to the first frequency, and setting the first switch means to a disconnected state;
On the other hand, when the frequency identification information is a second identification value, an output clock from the bus clock supply unit is set to the second frequency, and the first switch unit is connected. Processing equipment.

(12) In the information processing apparatus according to the eleventh aspect, the expansion card connection means includes a slot compliant with the PCI specification and the card slot, and a switch means for connecting to the first or second bus section. Wherein the first frequency is approximately 66 MHz and the second frequency is
The information processing apparatus characterized in that the frequency of the information is approximately 33 MHz.

(13) In the information processing apparatus according to item 8, in the first bus section, the first bus section is connected to the first bus section via at least one or more bus connecting sections connected to the first bus section. The shortest wiring in the order of the switch means
Bus sections are wired in the shortest order from the first switch means to at least one or more second bus connection means.
An information processing apparatus for shutting off the influence of an electrical load in a second bus section and reducing a propagation delay time of a bus signal in the first bus section when the switch means is in a disconnected state. .

(14) In the information processing apparatus according to the eleventh aspect, the first bus section may include at least one or more bus connection sections connected to the first bus section from the bus control section, and the first switch section. The second bus section is wired in the shortest order in order from the first switch means to at least one or more second bus connection means. When the first switch means is in the disconnected state, the second bus section is An information processing apparatus, wherein an influence of an electric load in a second bus section is cut off, and a propagation delay time of a bus signal in the first bus section is reduced.

(15) In the information processing apparatus as set forth in (6), when the expansion card is inserted while the information processing apparatus is energized, all the expansion cards inserted into the first group may be displayed. An information processing apparatus for notifying a user that the first bus operates at about 66 MHz when the upper limit operation frequency of the first bus is about 66 MHz or more and there is no expansion card in the second group.

(16) In the information processing apparatus according to item 12, when the expansion card is inserted while the information processing apparatus is energized, all the expansion cards inserted into the first group are displayed. An information processing apparatus for notifying a user that the first bus operates at about 66 MHz when the upper limit operation frequency of the first bus is about 66 MHz or more and there is no expansion card in the second group.

According to the embodiment of the present invention described above,
The following effects can be obtained.

(1) The operating frequency of the PCI bus of the information processing device is switched between 66.6 MHz and 33.3 MHz, and when the PCI bus operates at 66.6 MHz, up to two expansion cards can be installed. 33.3M
At the time of the Hz operation, the expansion card can be installed in up to four slots.

(2) When the PCI bus of the information processing device is 66.
When operating at 6 MHz, some bus routes and slots are disconnected from the bus section, so that the propagation delay time of the bus signal and the distortion of the signal waveform can be minimized.

(3) The configuration of the expansion card inserted into the PCI slot of the information processing apparatus is automatically determined, and when the power is turned on and when a live line is inserted, the user can operate the upper limit operation in any of the four slots. Even if a PCI expansion card having a frequency of 33.3 MHz is inserted, the operating frequency of the PCI bus is always set to 33.3 MHz, so that the information processing apparatus does not malfunction.

(4) The configuration of the expansion card installed in the PCI slot of the information processing apparatus is automatically determined, and the PCI bus is inserted even though the user has inserted the PCI expansion card having the upper limit operation frequency of 66.6 MHz. When operating at 33.3 MHz, a warning is displayed to assist the user in increasing the number of cards.

[0198]

As described above, according to the present invention, P
The operating frequency of the CI bus is 66.6 MHz and 33.3 MH
z and the PCI bus is 66.6.
When operating at 1 MHz, up to two expansion cards can be installed, and when operating at 33.3 MHz on the PCI bus, up to 4 expansion cards can be used, thereby improving the degree of freedom of the user's system configuration. .

Further, according to the present invention, at the time of switching between 33.3 MHz and 66.6 MHz, it is possible to support the user to add a card by using the user interface.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an arrangement of main components and a bus wiring shape of the information processing apparatus according to the embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a control unit in FIG. 1;

FIG. 4 is a block diagram illustrating a relationship among a frequency determination unit, a frequency information holding unit, and a frequency switching control unit in FIG. 3;

FIG. 5 is a diagram illustrating register means in FIG. 3;

FIG. 6 is a timing chart illustrating an operation example during power-on processing in the information processing apparatus according to the embodiment of the present invention.

FIG. 7 is a timing chart illustrating another operation example during power-on processing in the information processing apparatus according to the embodiment of the present invention.

FIG. 8 is a flowchart (part 1) illustrating a processing operation in the OS at the time of PCI hot swapping.

FIG. 9 is a flowchart (part 2) illustrating a processing operation in the OS at the time of PCI hot swapping.

FIG. 10 is a timing chart (part 1) for explaining a processing example when a live line is inserted;

FIG. 11 is a timing chart (part 2) for explaining a processing example when a live line is inserted.

FIG. 12 is a flowchart illustrating a processing operation when an expansion card is added.

FIG. 13 is a flowchart illustrating a processing operation when an expansion card is removed.

FIG. 14 is a block diagram illustrating a configuration of an information processing apparatus according to another embodiment of the present invention.

FIG. 15 is a diagram illustrating an arrangement of main components and a bus wiring shape of an information processing apparatus according to another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Printed circuit board 20 CPU 21 Memory / I / O controller 22 Memory 24 CRT controller 25 KB (keyboard) controller 26 HDD (hard disk) controller 27 BIOS-ROM 31 Clock generation means 32 Clock buffer 71 Control part 79, 611-614 Bus switch 92 Frequency determination means 93 Frequency switching control means 94 Frequency information holding means 95, 96 Register 97 PCI expansion card 210, 213 'PCI bus 211, 212 Bus section 241 Monitor 251 Keyboard 261 Hard disk 401-404 PCI slot 621-624, 631- 634, 641 to 644 switches 721 to 724 frequency information detecting means 731 to 734 hot plug control means 751 holding means 761 Selection means 911-914 Register 985, 991-994 Indicator lamp

Claims (3)

[Claims] In an information processing apparatus capable of inserting and removing a plurality of I / O expansion cards having different upper limit operating frequencies, a plurality of expansion card connection means connected to the same bus, and each of the plurality of expansion card connection means are provided. Card installation detecting means for detecting whether or not an expansion card is mounted on expansion card connection means provided corresponding to the above, and card frequency information for detecting an upper limit operating frequency of the expansion card mounted on the expansion card connection means An information processing apparatus comprising: a detecting unit; and a frequency switching control unit that determines and switches an operating frequency of a bus based on the number of expansion cards in an installed state and an upper limit operating frequency. 2. A bus to which a plurality of expansion card connecting means are connected is divided into two bus sections, a first bus section and a second bus section, by a bus switch. 2. The information processing apparatus according to claim 1, wherein the operating frequency of the bus is determined on the basis of which of the second bus sections the expansion card is connected to the expansion card connection means. 3. A bus operating frequency control method in an information processing device capable of inserting and removing a plurality of I / O expansion cards having different upper limit operating frequencies, wherein the information processing device includes a first switch and a second bus. Bus divided into sections, a plurality of expansion card connecting means connected to each of the first bus section and the second bus section, and expansion card connecting means provided corresponding to each of the expansion card connecting means Card mounting detecting means for detecting whether or not an expansion card is mounted on the expansion card, card frequency information detecting means for detecting an upper limit operating frequency of the expansion card mounted on the expansion card connecting means, bus clock supply means, Switching control means, wherein the bus clock supply means is configured to switch between one of a first frequency and a second frequency lower than the first frequency. A bus clock having a wave number is supplied to the expansion card connection unit, and the frequency switching control unit includes:
The operating frequency of the bus is determined based on the detection result of the card attachment detection unit and the detection result of the card frequency information detection unit, and when the power of the information processing apparatus is turned on, all of the expansions connected to the second bus section are determined. The card connection means is not mounted, and an expansion card is mounted on any of the expansion card connection means connected to the first bus section;
When the upper limit operating frequencies of all the installed expansion cards are equal to or higher than the first frequency, the first identification value is output. On the other hand, when the information processing apparatus is powered on, the first identification value is output. When an expansion card is attached to any of the connected expansion card connection means, a second identification value is output,
According to a first identification value, an output clock from the bus clock supply unit is set to the first frequency, and the bus switch is turned off. On the other hand, according to a second identification value,
A bus operating frequency control method, wherein an output clock from the bus clock supply unit is set to the second frequency and a bus switch is connected.