JP2001036735A - Device and method for enlarging and reducing image - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an image enlargement device capable of enlarging/reducing an image at a low cost. SOLUTION: A reduction interpolation circuit 1 interpolates the reduction of parallel two-phase picture data. A selection/rearrangement circuit 4 selects and rearranges picture data obtained from the circuit 1 and writes the rearranged data in a FIFO memory 2 again as parallel two-phase picture data. A selection/rearrangement circuit 5 selects and rearranges picture data outputted from the memory 2 and outputs the rearranged data as parallel four-phase picture data. An enlargement interpolation circuit 3 interpolates the enlargement of the parallel four-phase picture data and outputs the interpolated data as parallel two-phase picture data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image scaling device for scaling a digital video image.

[0002]

2. Description of the Related Art In an image display device such as a television receiver or a projector device, an image enlargement / reduction device using pixel density conversion is used to display an image enlarged or reduced. As shown in FIG. 14, for example, a general image enlargement / reduction apparatus based on pixel density conversion has a reduction interpolation circuit 1 provided before a FIFO memory 2 which is a frame memory, and an expansion interpolation circuit 3 provided after the FIFO memory 2. Is provided. A general image enlargement / reduction apparatus using pixel density conversion is described in, for example, the magazine “Interface” published by CQ Publishing, January, 1993, No. 1
Pages 83 to 191, "Principle of Pixel Number Conversion and Realization by C", March 1997, p. 215 to 222
It is described on page "Digital Signal Processing Exercises Learned by CAD".

[0003] F in the image scaling device shown in FIG.
The role of the IFO memory 2 is to write out only valid pixel data by thinning out (down-sampling) invalid pixel data from among the pixel data generated by interpolation in the reduction interpolation circuit 1 and to write image data consisting of the pixel data. The conversion of the time axis for continuous reading in accordance with the scanning and the supply of image data continuously with the same pixel data or zero data inserted (up-sampled) according to the request of the enlargement interpolation circuit 3 That is.

[0004]

By the way, the personal computer signal is enlarged or reduced by the image enlargement / reduction device, and the rate (frequency) of the image data to be enlarged or reduced is recently increasing. It is getting higher. Since the operating speed of the circuit elements constituting the image enlargement / reduction device, for example, the writing and reading speed of the FIFO memory 2, is limited, it is impossible to directly process image data having a high data rate.

Therefore, as a practical means, first, FI
For the FO memory 2, a high-speed data rate image data sequence is converted into a plurality of phases (for example, two phases) by a multiplexer.
And converts the data rate to a fraction of an integer
It is conceivable to reduce it to (1/2). Further, since the reduction interpolation circuit 1 and the enlargement interpolation circuit 3 are also formed in a plurality of parallel phases (two phases), the data rate can be reduced, which is effective for circuit integration. In this case, the image data is stored in the FIFO memory 2 (line memory).
Since the data rate can be reduced by writing and reading data at a speed of 1 / (1/2), the low-speed FIFO memory 2 can be used.

However, in this case, not only an image enlarging / reducing device is required for each of a plurality of phases, but also a plurality of FIFO memories 2 (line memories) for horizontal processing are required. Would. Therefore,
The circuit scale increases, and a low-cost image scaling device cannot be realized. In the pixel density conversion processing, as described above, the output data sequence from the reduction interpolation circuit 1 and the input data sequence to the enlargement interpolation circuit 3 become discontinuous due to thinning out or insertion of valid pixel data.
Conventionally, there has been no practical image enlargement / reduction apparatus with a small circuit scale that can handle such discontinuous data of multiple parallel phases with one image enlargement / reduction apparatus.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and an object of the present invention is to provide an image enlarging / reducing apparatus capable of enlarging / reducing image data of a plurality of parallel phases while maintaining a plurality of parallel phases. It is another object of the present invention to provide an image scaling device capable of scaling image data at a high data rate with a single FIFO memory as an image memory for downsampling and upsampling, and realizing at low cost. Aim.

[0008]

According to the present invention, there is provided an image enlarging apparatus for enlarging an image, comprising the steps of: An image memory (2) to be read out as image data; and a selection / arrangement circuit (5) to select and rearrange parallel plural-phase image data read from the image memory and to output again as parallel plural-phase image data. When,
An image enlargement device comprising: an enlargement interpolation circuit (3) that enlarges and interpolates parallel plural-phase image data output from the selection / rearrangement circuit and outputs the result as parallel plural-phase image data. (B) an image reduction device for reducing an image, a reduction interpolation circuit (1) for reducing and interpolating parallel plural-phase image data and outputting as parallel multiple-phase image data, and an output from the reduction interpolation circuit Selecting and rearranging circuit (4) for selecting and rearranging the selected multi-phase image data and outputting again as parallel multi-phase image data
And a FIFO memory (2) for writing and reading the image data of the multiple parallel phases output from the selection / rearrangement circuit, thereby outputting the image data as the multiple parallel image data.
(C) In an image scaling device for scaling an image, a plurality of parallel image data is reduced and interpolated to obtain a plurality of parallel image data. A reduced interpolation circuit (1) for outputting,
A first selection / rearrangement circuit (4) for selecting and rearranging the multi-phase image data output from the reduction interpolation circuit and outputting again as parallel multi-phase image data;
The FIFO memory (2) which outputs the parallel plural-phase image data by writing and reading the parallel plural-phase image data output from the selection / rearrangement circuit, and the parallel plural-phase image data output from the FIFO memory A second selection / rearrangement circuit (5) for selecting and rearranging the image data and outputting again as parallel multi-phase image data, and a parallel multi-phase image output from the second selection / rearrangement circuit An image enlargement / reduction apparatus characterized by comprising an enlargement interpolation circuit (3) for enlarging and interpolating data and outputting it as image data of a plurality of parallel phases. further,
(D) In an image enlarging method for enlarging an image, a first step of writing image data of a plurality of parallel phases and reading it as image data of a plurality of parallel phases; A second step of selecting and rearranging the image data, and outputting again as parallel multi-phase image data; and enlarging and interpolating the parallel multi-phase image data output in the second step. And a third step of outputting as enlarged image data.
(E) In an image reduction method for reducing an image, a first step of reducing and interpolating image data of a plurality of parallel phases and outputting it as image data of a plurality of parallel phases, and a parallel step output by the first step. A second step of selecting and rearranging the image data of the plurality of phases and outputting the image data of the plurality of parallel phases again as image data of the plurality of parallel phases; and writing and reading out the image data of the plurality of parallel phases output in the second step, And a third step of outputting as parallel multiple-phase reduced image data. (F) In the image scaling method for scaling an image, A first step of reducing and interpolating data and outputting as parallel multi-phase image data; and a parallel multi-phase image data output in the first step. A second step of selecting, rearranging, and outputting again as parallel plural-phase image data; and writing and reading the parallel plural-phase image data output in the second step to reduce the parallel plural phase. A third step of outputting as parallel image data, a fourth step of selecting and rearranging the parallel plural-phase image data output in the third step, and outputting again as parallel plural-phase image data; And a fifth step of enlarging and interpolating the parallel plural-phase image data output in the fourth step and outputting the same as parallel plural-phase enlarged image data.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an apparatus and a method for enlarging / reducing an image according to the present invention. FIG.
1 is a block diagram showing a first embodiment of the image enlargement / reduction device of the present invention, FIG. 2 is a block diagram showing a specific configuration of the reduction interpolation circuit 1 in FIG. 1, and FIG. FIG. 4 is a block diagram showing a specific configuration, FIG. 4 is a diagram for explaining the principle of the reduction operation according to the first embodiment of the image enlargement / reduction apparatus and method of the present invention, and FIG. FIG. 6 is a diagram for explaining the principle of the enlargement operation according to the first embodiment, FIG. 6 is a partial block diagram showing a second embodiment of the image enlargement / reduction apparatus of the present invention, and FIG. FIG. 8 is a block diagram showing a specific configuration of the reduction interpolation circuit 1 in FIG. 7, and FIG. 9 is a block diagram showing a specific configuration of the enlargement interpolation circuit 3 in FIG. 10 is a third embodiment of the image scaling device and method according to the present invention.
FIG. 1 is a diagram for explaining the principle of the reduction operation according to the embodiment.
FIG. 1 is a view for explaining the principle of an enlargement operation according to a third embodiment of the image enlargement / reduction apparatus and method of the present invention. FIGS. 12 and 13 show the case where the image enlargement / reduction apparatus of the present invention is developed in the vertical direction. 3 is a block diagram illustrating a configuration example. In FIGS. 1 to 3 and FIGS. 7 to 9, the same parts as those in FIG. 14 are denoted by the same reference numerals.

<First Embodiment> In the first embodiment, in order to simplify the description, parallel two-phase image data is
The case of outputting as phase image data will be described. The present invention is not limited to two parallel phases, but can be image data of any multiple phases. Note that, for convenience of signal processing, it is preferable to use an even number of multiple phases, such as 2-phase, 4-phase, 8-phase, and so on.

First, the operation of the reduction processing by the image enlargement / reduction apparatus of the present invention will be described. In FIG. 1, parallel two-phase image data is input to a reduction interpolation circuit 1. If the pixels of the frame are 1, 2, 3, 4,... In order, pixels 1, 3, 5,... , 6 ... are pixels (1, 2),
(3, 4), (5, 6)... Are input in pairs. Here, for the sake of convenience, the reduced interpolation circuit 1 is shown as one block, but actually, as shown in FIG. 2, two reduced interpolation filters 12 and 13 for performing a reduction process are provided.
Consisting of Here, the case of the simplest bilinear interpolation (two-point interpolation) is shown.

In FIG. 2, one of parallel two-phase image data is input to a reduction interpolation filter 12 via a D flip-flop 11 which is an example of a delay circuit, and the other is input as it is. The reduction interpolation filter 13 includes:
The parallel two-phase image data is input as it is. The reduction interpolation filters 12 and 13 perform predetermined arithmetic processing in accordance with the reduction ratio and the pixel coordinates, respectively, and output the result. Each one-phase data output from the reduction interpolation filters 12 and 13 is output from the reduction interpolation circuit 1 as two-phase data. The reduction interpolation circuit 1 is controlled by a control signal CTLi from the control circuit 10.

Returning to FIG. 1, the two-phase data output from the reduction interpolation circuit 1 is input to a selection / reordering circuit 4. The selection and rearrangement circuit 4 includes, for example, three cascade-connected D flip-flops 411, 412, and 413.
And a selection circuit 42.
How many D flip-flops are provided in the memory circuit 41 depends on the interpolation method and the reduction ratio in the reduction interpolation circuit 1 or how many types of reduction ratios are realized.
That is, the number of D flip-flops depends on the interpolation method, reduction ratio,
Alternatively, the number is set appropriately depending on how many types of reduction ratios are realized, so that the number is one or more.

Further, since the memory circuit 41 is for temporarily storing input data, it is not limited to a D flip-flop which is a register.
It may be a memory such as a buffer. In FIG. 1,
Although the D flip-flops 411 to 413 are shown as one block for convenience, a D flip-flop is provided for each phase in practice.

The two-phase data output from the reduction interpolation circuit 1 and the two-phase data stored and delayed by the D flip-flops 411 to 413 are input to the selection circuit 42. The selection control signal SELi is input from the control circuit 10 to the selection circuit 42, and the selection circuit 42 appropriately selects the input data and inputs the data to the FIFO memory 2. A frame memory is used as the FIFO memory 2 if the image data is scaled up and down in the horizontal and vertical directions, and a line memory is used as the FIFO memory 2 if the image data is scaled up and down only in the horizontal direction. .

The selection circuit 42 may select the two-phase data from the reduction interpolation circuit 1 and the D flip-flops 411 to 413 as a pair and input the pair to the FIFO memory 2, or may select one of the two-phase data. And the other two
In some cases, one of the phase data is selected and input to the FIFO memory 2 as new two-phase data. Selection circuit 42
, Appropriately selects and rearranges the input data according to the reduction ratio and outputs the data.

The FIFO memory 2 is supplied with a write enable WE and a read enable RE from the control circuit 10 in addition to the clock and the reset signal. As a result, the enable processing of the pixel data is executed for each pixel pair. When changing the reduction ratio, the control circuit 1
0 also controls the reduction interpolation circuit 1 by the control signal CTLi.

As will be described in detail later, the selection circuit 42 outputs two-phase valid data pairs and two-phase invalid data pairs in a temporally mixed manner. When writing the two-phase data pair from the selection circuit 42 to the FIFO memory 2, the write enable WE is enabled only for the valid data pair to
Control is performed so as to write data into the FIFO memory 2 and invalidate the write enable WE for an invalid data pair so as not to write data into the FIFO memory 2. Then, the read enable RE is made valid, and the written valid data pairs are sequentially read, thereby continuously outputting the reduced two-phase data.

Here, referring to FIG.
The principle by which the selection / rearrangement circuit 4 can directly perform reduction processing on data of a plurality of phases will be described. FIG. 4 shows the case of two phases, but the principle is the same in other plural phases. FIG. 4 shows 3/5 as an example.
The operation at the time of double reduction is shown. In FIG.
(A) shows the principle for multiplying one-phase data by 3/5. The upper part is input data, and the lower part is output data.
Here, the simplest bilinear interpolation is shown. Since three output data can be obtained for five input data, the input data is sequentially denoted by i1, i2, i3, i
4, i5, i1 ', i2', i3 ', i4', i5 ',
i1 "..., and output data in order of o1, o2, o3, o
1 ′, o2 ′, o3 ′, o1 ″...

In FIG. 4, (B) shows a reduced interpolation circuit 1
2 shows two-phase data input to. In FIG. 4B, the data in the upper row corresponds to the data of the upper phase in the figure input to the reduction interpolation circuit 1, and the data in the lower row corresponds to the data of the lower phase in the figure. As shown in FIG. 4B, (i1, i2), (i3, i
4), data is input in pairs, such as (i5, i1 ').

FIG. 4C shows two sets of two-phase data input to the reduction interpolation filters 12 and 13 shown in FIG. In FIG. 4C, the upper two-phase data corresponds to data input to the reduction interpolation filter 12, and the lower data corresponds to data input to the reduction interpolation filter 13. One data input to the reduction interpolation filter 12 is data delayed by the D flip-flop 11. Therefore, the upper data in FIG. 4C of the data input to the reduction interpolation filter 12 is one of the lower data in FIG. 4C input to the reduction interpolation filter 13.
The data at the immediately preceding timing (that is, one clock before) is obtained.

In FIG. 4, (D) shows output data of reduced interpolation filters 12 and 13 obtained from the data set shown in FIG. 4 (C) (ie, two-phase output data output from reduced interpolation circuit 1). Is shown. In FIG. 4D, a circle indicated by a broken line indicates invalid data. As an example, consider the second data set from the left in FIG. 4C. As can be seen from FIG. 4A, since the output data o2 is obtained from the data (i2, i3) input to the reduction interpolation filter 12, the data generated by the data (i2, i3) is valid data. On the other hand, FIG.
As can be seen from (A), in principle, no output data is generated from the data (i3, i4) input to the reduction interpolation filter 13, so the data generated by the data (i3, i4) is invalid data. As described above, the reduced interpolation circuit 1 outputs valid data and invalid data in a mixed manner.

FIG. 4E shows a part of the data input to the selection circuit 42. As described above, the two-phase data shown in FIG. 4D is input to the selection circuit 42, and is input to the selection circuit 42 after being delayed by the D flip-flops 411 to 413. Here, the data required at the time of the 3/5 reduction is delayed by one clock by one D flip-flop 411 in the D flip-flops 411 to 413, so that two sets of two-phase data input to the selection circuit 42 are output. Is as shown in FIG.

The selection circuit 42 includes two sets 2 shown in FIG.
Data is selected from the data of the phases (that is, four phases) so as to generate a data set including only valid data. FIG. 4 (A)
Since it is necessary to output the output data shown in the lower stage as two-phase data, (o1, o2), (o3, o
i ′), (o2 ′, o3 ′)... For example, consider the second data set from the left in FIG. These four phase data include:
Since the data (o1, o2) is included, the selection circuit 4
2 selects and outputs data (o1, o2).

Next, the third data set from the left in FIG. 4E is considered. Although the four-phase data includes valid data o2 and o3, the data (o
There is no point in selecting 2,2). Therefore, in this case, a set of invalid data and data o3 is output with the option selected in the second data set from the left in FIG. 4E as it is, or 1
The data set at the previous timing is output as it is. Therefore, at the time of the third data set from the left in FIG. 4E, an invalid data set is output.

As described above, the selection circuit 42 operates as shown in FIG.
By selecting a data set as shown in FIG. 4 and supplying only a valid data set to the FIFO memory 2, the two-phase data shown in FIG. Become. As described above, the FIFO memory 2
In FIG. 4 (F), reduction processing is realized by writing and sequentially reading only the data set of valid data shown in FIG.

Next, the operation of the enlargement processing by the image enlargement / reduction apparatus of the present invention will be described. A memory circuit 51 for temporarily storing the output data of the FIFO memory 2 and a selection circuit 52 for selecting the output data of the FIFO memory 2 or the memory circuit 51 are also provided between the FIFO memory 2 and the enlargement interpolation circuit 3. A selection / rearrangement circuit 5 is provided. The memory circuit 51 includes D flip-flops 511 to 5
It consists of 12. By providing the selection / rearrangement circuit 5, the data is supplied to the expansion interpolation circuit 3 as it is in a plurality of phases, and the expansion interpolation circuit 3 can directly perform the expansion interpolation processing on the data of the plurality of phases. . Also here, since bilinear interpolation is used as the interpolation method in the enlargement interpolation circuit 3, four image data are supplied to the enlargement interpolation circuit 3. The number of image data output from the selection circuit 52 depends on the interpolation method.

Before explaining the circuit operation after the FIFO memory 2, the principle that the enlargement interpolation circuit 3 can apply enlargement processing to data of a plurality of phases as it is will be described with reference to FIG. FIG. 5 shows the case of two phases, but the principle is the same in other plural phases. FIG. 5 shows an operation at the time of 5/3 magnification as an example. In FIG. 5, (A) shows the principle for multiplying one-phase data by 5/3. The upper part shows input data and the lower part shows output data. Here, the simplest bilinear interpolation is shown. Since five output data are obtained for three input data, the input data is sequentially denoted by i1, i
2, i3, i1 ', i2', i3 ', i1 "..., And the output data is o1, o2, o3, o4, o5, o
1 ′, o2 ′, o3 ′, o4 ′, o5 ′, o1 ″.

In FIG. 5, (B) shows from which input data the one-phase output data o1, o2, o3... Shown in the lower part of FIG. As shown in FIG. 5A, for example, output data o1 and o2 are generated from input data i1 and i2, and output data o3 and o4 are
Generated from input data i2, i3. As described above,
From the FIFO memory 2, pixels are output in pairs. The output data of the FIFO memory 2 is two-phase data as shown in FIG. In FIG. 5B, the upper data corresponds to data from the upper phase of the FIFO memory 2 in the figure, and the lower data corresponds to data from the lower phase in the figure. However, as described later, FIG.
Is not used as it is.

Now, since the pixels are also output as a pair from the enlargement interpolation circuit 3, the enlargement interpolation circuit 3 outputs the pixels shown in FIG.
(A) Instead of one-phase data as shown in the lower part of FIG.
Two-phase data as shown in (D) must be output. In FIG. 5D, the upper data corresponds to the data from the upper phase in the drawing of the enlargement interpolation circuit 3, and the lower data corresponds to the data from the lower phase in the drawing.

For example, in order to obtain output data o1, FIG.
As shown in FIG. 5B, two-phase input data i1 and i2 are required. To obtain output data o2, two-phase input data i1 and i2 are required as shown in FIG. 5B. That is, to obtain two-phase output data o1 and o2,
As indicated by the arrows, two-phase input data i1, i2
Is required. That is, FIG.
2D required to obtain the two-phase output data shown in FIG.
The set of input data for a phase is shown.

Next, FIG.
In order to obtain the two-phase output data shown in (D), which input data is newly required at that timing is shown. For example, consider two-phase output data o3 and o4 shown in FIG. In order to obtain two-phase output data o3 and o4, as shown in FIG.
2 and i3 are required. Among them, the input data i2 has already been used as the two-phase input data i1 and i2 at the previous timing (that is, one clock before), so it is not necessary to newly read out the data here. The data used at the previous timing may be held.
On the other hand, the input data i3 is two-phase output data o3, o4
Since this is the data that is required for the first time in obtaining the data, it is necessary to newly read the data here. Since the input data is paired in two phases, the data to be newly read out is the two-phase input data i3, as shown in FIG.
i1 '.

Further, in order to obtain two-phase output data o5 and o1 'shown in FIG. 5D, input data i3, i1' and i2 'are required as shown in FIG. 5C. . Among them, the input data i3 is data that has already been used at the immediately preceding timing (that is, one clock before), and the input data i1 ′ is the output data o3
o4 to obtain the two-phase input data i3
It is the input data i2 'that needs to be newly read out because it is included in i1'. Since the input data is paired in two phases, the data to be newly read out is two-phase input data i2′i3 ′ as shown in FIG.

Based on such a concept, data newly required at the timing to obtain the two-phase output data shown in FIG. 5D is as shown in FIG. In FIG. 5E, a blank indicates that it is not necessary to newly read data at that timing, and that data used at one or more previous timings may be used.

To summarize the above operations, in order to obtain the two-phase output data by performing the enlargement processing using the two-phase input data,
It can be seen that the relationship shown in FIG. Also in FIG. 5F, a blank column indicates that it is not necessary to newly read data at that timing, and it is sufficient to use data used at one or more previous timings. As can be seen from FIG. 5 (F), the two-phase input data necessary to obtain the two-phase output data output at a constant rate is read out from the FIFO memory 2 at a constant timing and is expanded. It is necessary to temporarily store the read data instead of supplying the data to the interpolation interpolation circuit 3, select and rearrange the data, and supply the data to the enlargement interpolation circuit 3. In addition, as shown in FIG. 5C, it is necessary to appropriately select necessary two-phase input data and supply it to the enlargement interpolation circuit 3. The selection and rearrangement circuit 5 in FIG. 1 is necessary for this purpose.

Here, returning to FIG. 1, the FIFO memory 2
The following describes the operation of the enlargement process. A read enable RE is supplied from the control circuit 10 to the FIFO memory 2 to control data reading. As described above,
When data is newly read at a certain timing, the read enable RE is made valid. When data is not newly read at a certain timing, the read enable RE is made invalid.

The two-phase data read from the FIFO memory 2 is input to the selection / reordering circuit 5. The selection and rearrangement circuit 5 includes, for example, three cascade-connected D
The memory circuit 51 includes flip-flops 511, 512, and 513, and a selection circuit 52. Memory circuit 5
How many D flip-flops are provided in 1 differs depending on the interpolation method and the enlargement ratio, or how many kinds of enlargement ratios are realized. That is, the number of D flip-flops is one or more, since it is appropriately set according to the interpolation method, the enlargement ratio, or how many types of enlargement ratios are realized.

Further, since the memory circuit 51 is for temporarily storing input data, it is not limited to a D flip-flop which is a register.
It may be a memory such as a buffer. In FIG. 1,
Although the D flip-flops 511 to 513 are shown as one block for convenience, a D flip-flop is provided for each phase in practice.

The two-phase data read out from the FIFO memory 2 and the two-phase data stored and delayed by the D flip-flops 511 to 513 are selected by the selection circuit 5.
2 is input. The selection control signal SELo is input from the control circuit 10 to the selection circuit 52, and the selection circuit 52 appropriately selects the input data and inputs the data to the enlargement interpolation circuit 3. The selection circuit 52 may select the two-phase data from the FIFO memory 2 or the D flip-flops 511 to 513 as a pair and input the pair to the enlargement interpolation circuit 3, or select one of the two-phase data. At the same time, one of the other two-phase data may be selected and input to the enlargement interpolation circuit 3 as new two-phase data. The selection circuit 52 appropriately selects the input data according to the magnification and the pixel coordinates. In the present embodiment, the output of the selection circuit 52 is as shown in FIG.
As described above, two sets of two-phase data (ie, four phases).

The two sets of two-phase data thus selected are input to the enlargement interpolation circuit 3. The upper part of FIG. 5F is an example of two-phase data output from the FIFO memory 2. The enlargement interpolation circuit 3 performs predetermined filtering based on the enlargement ratio and pixel coordinates on the input two sets of two-phase data to generate enlarged data. The enlargement interpolation circuit 3
It is controlled by a control signal CTLo from the control circuit 10. Here, for convenience, the enlargement interpolation circuit 3 is shown as one block, but in actuality, as shown in FIG. 3, enlargement processing is performed on one set of two sets of two-phase data. It comprises an enlargement interpolation filter 31 and an enlargement interpolation filter 32 for performing enlargement processing on the other set of data. Then, from the enlargement interpolation circuit 3, FIG.
As shown in the lower part, the two-phase data subjected to the enlargement processing is output. When changing the enlargement ratio, the control circuit 10 also controls the enlargement interpolation circuit 3 by the control signal CTLo.

As described above, in the image enlargement / reduction apparatus of the present invention, reduction processing is realized from the reduction interpolation circuit 1 to the FIFO memory 2, and expansion processing is realized from the FIFO memory 2 to the expansion interpolation circuit 3. . The input two-phase data is subjected to reduction or enlargement processing as it is, and is output as two-phase data. Note that, in FIG. 1, all operations from the reduction interpolation circuit 1 to the input of the FIFO memory 2 operate at the same clock frequency. Similarly, everything from the output of the FIFO memory 2 to the enlargement interpolation circuit 3 operates at the same clock frequency.

If the enlargement processing is unnecessary, the reduction interpolation circuit 1
The image reduction device from the FIFO memory 2 to the FIFO memory 2 may be used. If the reduction process is unnecessary, the image expansion device from the FIFO memory 2 to the enlargement interpolation circuit 3 may be used. Further, a reduction process is performed from the reduction interpolation circuit 1 to the FIFO memory 2, and the reduction processing is performed from the FIFO memory 2 to the expansion interpolation circuit 3.
By performing the enlargement processing up to, enlargement / reduction processing at an arbitrary magnification can also be performed.

According to the image enlarging / reducing apparatus of the present invention, even if the rate of input image data is increased, the FI which is an image memory for down-sampling and up-sampling is used.
Only one FO memory 2 is required. Furthermore, the operating frequency of each circuit from the reduction interpolation circuit 1 to the enlargement interpolation circuit 3 may be low. The fact that only one FIFO memory 2 is required means that the circuit scale (memory scale) is small and the cost is low, and that the operating frequency of the circuit is low and that the integrated circuit can be manufactured by a simple process. So
Very convenient. As the FIFO memory 2, a general-purpose DRAM can be used as a memory core, and it is possible to provide a low-cost image enlargement / reduction apparatus that enlarges / reduces image data at a high data rate.

The number of phases of the input data may be appropriately set according to the rate of the image data. In this embodiment, the input and output of the FIFO memory 2 are also two-phase.
The input to the IFO memory 2 is, for example, four-phase, and the selection circuit 5
Up to two may be processed in four phases. This way,
The operation speed of the FIFO memory 2 is further reduced. As described above, during the signal processing, the input data and the output data may have more phases than the phases.

In the first embodiment described above, the configuration in which the selection circuits 42 and 52 are provided after the memory circuits 41 and 51 as the selection and rearrangement circuits 4 and 5 has been described. , 5 are not limited to this. The selection / rearrangement circuits 4 and 5 perform a reduction ratio based on a plurality of timing image data pairs (parallel image data pairs) in a parallel multiphase image data set (image data pairs) sequentially output in time series from the reduction interpolation circuit 1 and the FIFO memory 2. Any image data may be used as long as the image data is appropriately selected and rearranged according to the magnification and the pixel coordinates and rearranged, and output again as a new parallel multiple-phase image data set (image data pair).

Representatively, the reduction process will be described.
The selection and rearrangement circuit 4 only needs to be able to obtain the data set shown in FIG. 4F from the data set shown in FIG. The data set shown in FIG. 4 (D) and the data set shown in FIG. 4 (F) have a relationship as shown by a dashed line. There is no change from FIG. Therefore, instead of the selection / rearrangement circuit 4 shown in FIG. 1, a selection / rearrangement circuit 4 'as shown in FIG. 6 can be used as the second embodiment.

<Second Embodiment> A selection / rearrangement circuit 4 'shown in FIG. 6 has a configuration in which a memory circuit 44 is provided at the subsequent stage of the switching circuit 43. The memory circuit 44 includes two FIFO memories 441 and 442, for example. The switching circuit 43 includes a selection control signal SEL from the control circuit 10.
i is input, and the switching circuit 43 switches and supplies the input data to one of the FIFO memories 441 and 442 as appropriate. A common clock CK is input from the control circuit 10 to the write side and the read side of the FIFO memories 441 and 442, and the FIFO memories 441 and 442 perform FIFO operations in synchronization.

Further, a common write reset WR, read reset RR and read enable RE are supplied from the control circuit 10 to the FIFO memories 441 and 442.
The write enable signals WE1 and WE2 are supplied from the control circuit 10 to the FIFO memories 441 and 442, respectively. By sequentially writing and reading the data set of the valid data shown in FIG. 4D to and from the FIFO memories 441 and 442, the output from the memory circuit 44 becomes the same as the output of the selection circuit 42 as shown in FIG. Line (however,
Unnecessary data is skipped). Switching circuit 43
It can be seen that the write control by the write enable WE1 and WE2 in the FIFO memories 441 and 442 performs the same function as the selection circuit 42. That is, it can be said that the selection / rearrangement circuit 4 'shown in FIG. 6 has a configuration in which a selection circuit is provided in a stage preceding the memory circuit.

Although FIG. 6 shows the configuration in which the switching circuit 43 is provided separately from the memory circuit 44, the switching circuit 43 is deleted and the switching circuit 43 is controlled by writing data to the FIFO memories 441 and 442. It may perform the same function as. Apparently, even if there is no switching circuit (selection circuit), all having the same function are included in the present invention. By the way, FIFO
The memories 441 and 442 include D flip-flops 411 to
Since it is used in place of 413, the capacity of the FIFO memories 441 and 442 may be small. Therefore,
6, the circuit scale does not increase.

Although not shown, the configuration of the selection / rearrangement circuit 4 'shown in FIG. 6 described above can also be used as the selection / rearrangement circuit 5. As the FIFO memories 441 and 442, a FIFO memory SN74ACT7801 manufactured by Texas Instruments Japan Limited can be used.

<Third Embodiment> In the third embodiment, a case will be described in which parallel four-phase image data is input and output as parallel four-phase image data. First, the operation of the reduction process will be described. In FIG. 7, parallel four-phase image data is input to the reduction interpolation circuit 1. Assuming that the pixels of the frame are 1, 2, 3, 4,... In the first phase from the top of the drawing, the pixels 1, 5, 9,.
.., The third phase from the top in the figure, the pixels 3, 7, 11,..., And the fourth phase from the top, the pixels 4, 8,. 12 are the pixels (1, 2, 3,
4), (5, 6, 7, 8), (9, 10, 11, 12)
… Is input in pairs. Here, for convenience, the reduced interpolation circuit 1 is shown as one block,
Actually, as shown in FIG. 8, it is composed of four reduction interpolation filters 12, 13, 13, and 14 for performing reduction processing. Here, the simplest bilinear interpolation (two-point interpolation)
It shows about the case of.

In FIG. 8, if the image data of the four-phase input to the reduction interpolation circuit 1 is referred to as an1 to an4, the reduction interpolation filter 12 stores the image data an4 in the D flip-flop 11 which is an example of the delay circuit. The image data a (n-1) 4 delayed by and the image data an1 are input.
The image data an1 and an2 are input to the reduction interpolation filter 13, and the image data
n2 and an3 are input, and the image data an3 and an4 are input to the reduction interpolation filter 15. Reduction interpolation filter 1
Nos. 2 to 15 perform predetermined arithmetic processing in accordance with the reduction ratio and the pixel coordinates, respectively, and output. Reduction interpolation filter 1
The one-phase data respectively output from 2 to 15 are output from the reduction interpolation circuit 1 as four-phase data. Note that the reduction interpolation circuit 1 receives the control signal CTLi from the control circuit 10.
Is controlled by

Returning to FIG. 7, the four-phase data output from the reduction interpolation circuit 1 is input to a selection / reordering circuit 4 ". The selection / reordering circuit 4" includes a selection circuit 45 and a D flip-flop. Memory circuit 46 composed of loops 461 and 462
And a selection circuit 47. The selection circuit 45 selects only valid pixel data from the input four-phase image data and distributes the data to one of the D flip-flops 461 and 462. The selection circuit 45 receives a selection control signal SELiW from the control circuit 10, and the selection circuit 45 appropriately selects the input pixel data, and
61 or 462.

The D flip-flops 461 and 462 have 4
It is possible to write, store, and read one pixel data. Writing of pixel data to the D flip-flops 461 and 462 is not always performed in a batch of four phases.
The reading of the pixel data is performed collectively for four phases. The memory circuit 46 is for temporarily storing input data, and is not limited to a D flip-flop, but may be a memory such as a buffer.

The four-phase image data output from the D flip-flops 461 and 462 is input to the selection circuit 47. The selection circuit 47 receives D flip-flops 461 and 46 in response to a selection control signal SELiR from the control circuit 10.
2 is alternately selected. When the selection circuit 47 is inputting the image data from the D flip-flop 461,
The D flip-flop 462 writes the image data from the selection circuit 45. On the other hand, when the selection circuit 47 receives the image data from the D flip-flop 462, the D flip-flop 461 outputs the image data from the selection circuit 45. Is written. That is, the D flip-flops 461 and 462 alternately write and read image data. The selection circuit 47 converts the selected image data into FI
Input to the FO memory 2. If the image data is scaled horizontally and vertically in a plane, a frame memory is used as the FIFO memory 2, and if the image data is scaled only in the horizontal direction, the FIFO memory 2 is
Line memory is sufficient.

As described above, the selection / rearrangement circuit 4 "
According to the reduction ratio, the input four-phase image data is appropriately selected, rearranged, and output. In the memory circuit 41 in the selection and rearrangement circuit 4 according to the first embodiment described above,
As described above, the number of D flip-flops is set according to an interpolation method, a reduction ratio, or how many types of reduction ratios are realized. However, the memory in the selection / rearrangement circuit 4 ″ according to the third embodiment is described. In the circuit 46, two memories such as D flip-flops may be provided.

The write enable WE and the read enable RE are supplied to the FIFO memory 2 from the control circuit 10 in addition to the clock and the reset signal. As a result, the enable processing of the pixel data is executed for each set of pixels. When changing the reduction ratio, the control circuit 1
0 also controls the reduction interpolation circuit 1 by the control signal CTLi.

As will be described later in detail, the four-phase valid data set and the four-phase invalid data set are temporally mixed and output from the selection / rearrangement circuit 4 ″. When writing a 4-phase data set from 4 ″ to the FIFO memory 2, the write enable WE is enabled only for the valid data set and written to the FIFO memory 2, and the write enable WE is disabled for the invalid data set. F
Control is performed so as not to write to the IFO memory 2. Then, by enabling the read enable RE and sequentially reading out the written valid data pairs, the reduced 4
The phase image data is continuously output.

Here, the principle that the reduction interpolation circuit 1 and the selection / rearrangement circuit 4 ″ can directly perform the reduction processing on the four-phase pixel data set will be described with reference to FIG. Fig. 10 shows the operation at the time of 3/5 reduction as an example, Fig. 10 (A) shows the principle for multiplying the data of one phase by 3/5, the upper part is the input data, and the lower part is the lower part. Here, the simplest bilinear interpolation is shown.Since three output data are obtained for five input data, the input data is sequentially denoted by i1, i2, i3, i4, i5.
i1 ', i2', i3 ', i4', i5 ', i1 "..., and the output data is o1, o2, o3, o1', o
2 ′, o3 ′, o1 ″...

FIG. 10B shows four-phase data input to the reduction interpolation circuit 1. As shown in FIG. 4B, (i1, i2, i
3, i4), (i5, i1 ', i2', i3 '), (i
4 ′, i5 ′, i1 ″, i2 ″).

In FIG. 10, (C) shows four pairs of eight data input to the reduction interpolation filters 12 to 15 shown in FIG. One data input to the reduction interpolation filter 12 is data delayed by the D flip-flop 11. Therefore, the uppermost data in FIG. 4C of the data input to the reduction interpolation filter 12 is the timing (1) immediately before the lowermost data in FIG. 4C input to the reduction interpolation filter 15. That is, the data is one clock before).

In FIG. 10, (D) corresponds to FIG.
Reduced interpolation filters 12-1 obtained from the data set shown in FIG.
5 (that is, four-phase output data output from the reduction interpolation circuit 1). In FIG. 10D, a circle indicated by a broken line indicates invalid data. As an example, consider the second data set from the left in FIG. 10C. As can be seen from FIG. 10A, the data (i4, i
Since the output data o3 is obtained from 5), the data (i)
The data generated by (4, i5) is valid data. On the other hand, as can be seen from FIG. 10A, since the output data is not generated in principle from the data (i5, i1 ′) input to the reduction interpolation filter 13, the data (i5, i5)
The data generated according to 1 ′) is invalid data. As described above, the reduced interpolation circuit 1 outputs valid data and invalid data in a mixed manner.

In FIG. 10, (E) shows a state in which pixel data is selected from the four-phase data set by the selection circuit 45 in the selection / rearrangement circuit 4 ″ and rearranged and written in the memory circuit 46. 10D, the pixel data is appropriately selected by the selection circuit 45 and distributed to the D flip-flops 461 and 462 of the memory circuit 46. The D flip-flops 461 and 462 are filled. The data is output by the selection circuit 47 as a four-phase data set.

The selection / rearrangement circuit 4 ″ is shown in FIG.
Are selected so as to generate a data set using only valid data from the four-phase data shown in FIG. Since the output data shown in the lower part of FIG. 10A needs to be output as four-phase data, (o1, o2, o3, oi '),
(O2 ', o3', o1 ", o2")... For example, FIG.
Consider the second data set from the left in the figure in (D).
The four-phase data includes data (o3, o1 ', o
2 ′), the selection circuit 45 selects the data (o3, o1 ′, o2 ′) and sends the data o3 as the third data to the D flip-flop 461.
Data o1 ′ is input as fourth data, and data o2 ′ is input to the D flip-flop 462 as first data.

The selection circuit 47 includes a D flip-flop 46
Since 1,462 are alternately selected, the four-phase data set output from the selection circuit 47 is as shown in FIG.

As described above, the selection / rearrangement circuit 4 ″ is
A data set as shown in FIG.
If only a valid data set is supplied to the memory 2, FIG.
Can be reduced with the four-phase data as it is. As mentioned above, FI
The FO memory 2 realizes a reduction process by writing and sequentially reading only the data set of valid data shown in FIG.

Next, the operation of the enlargement processing will be described.
A FIFO memory is provided between the FIFO memory 2 and the enlargement interpolation circuit 3.
Selection circuit 5 for selectively outputting output data of O memory 2
5, a memory circuit 56 including D flip-flops 561 and 562 for temporarily storing input data;
A selection circuit 57 for selecting and outputting data necessary for enlargement interpolation from the data from the flip-flops 561 and 562
The selection / rearrangement circuit 5 ″ is provided. By providing the selection / rearrangement circuit 5 ″, data is supplied to the enlargement interpolation circuit 3 in a plurality of phases, and the enlargement interpolation circuit 3 Enlargement interpolation processing can be directly applied to data of a plurality of phases. Also here, since the bilinear interpolation is used as the interpolation method in the enlargement interpolation circuit 3, eight image data are supplied to the enlargement interpolation circuit 3. The number of image data output from the selection circuit 57 is determined by
Depends on the interpolation method.

Before explaining the circuit operation after the FIFO memory 2, the principle that the enlargement interpolation circuit 3 can directly perform enlargement processing on four-phase data will be described with reference to FIG. FIG. 11 shows an operation at the time of 5/3 magnification as an example. In FIG. 11, (A)
Shows the principle for multiplying the data of one phase by 5/3. The upper part is the input data, and the lower part is the output data. Here, the simplest bilinear interpolation is shown.
Since five output data are obtained for three input data, the input data is sequentially denoted by i1, i2, i3, i
1 ′, i2 ′, i3 ′, i1 ″..., And output data in order, o1, o2, o3, o4, o5, o1 ′, o2 ′, o
3 ', o4', o5 ', o1 "...

FIG. 11B shows four-phase input data i1, i2, i read from the FIFO memory 2.
3 ... How are the D flip-flops 561 and 562
Is written.

The pixel data is also output from the enlargement interpolation circuit 3 in a 4-phase parallel manner.
Instead of one-phase data as shown in the lower part of FIG. 11A, four-phase data as shown in FIG. 11D must be output. In FIG. 11D, the first data from the top corresponds to the first data from the top of the enlarged interpolation circuit 3, and the second data from the top corresponds to the second data from the top of the enlarged interpolation circuit 3. The third output data corresponds to the
The third data corresponds to the third output data from the top of the enlarged interpolation circuit 3 in the figure, and the fourth data from the top corresponds to the fourth output data from the top of the enlarged interpolation circuit 3 in the figure.

For example, as shown in FIG. 11A, two input data i1 and i2 are necessary to obtain output data o1, and two input data i1 and i2 are required to obtain output data o2. Is necessary, two input data i2 and i3 are necessary to obtain the output data o3, and two input data i2 and i3 are necessary to obtain the output data o4. Output data o1, o2
In order to obtain o3 and o4, four-phase input data i1, i2,
This means that three data of input data i1, i2 and i3 are required among i3 and i4. That is, FIG.
FIG. 11C shows a set of eight input data of two sets and four phases required to obtain the output data of four phases shown in FIG.

For example, consider the four-phase output data o5, o1 ', o2', and o3 'shown in FIG. To obtain the four-phase output data o5, o1 ', o2', o3 ', as shown in FIG. 11C, the input data i3, i
1 ′,... I2 ′, i3 ′ are required. Among them, the input data i3, i1 'is the timing before (i.e.,
Four clocks of input data i1, i
2, i3, i1 ', it is not necessary to newly read out data here, but it is sufficient to hold the data used at the previous timing. On the other hand, input data i2 ', i3' is output data o1 ', o2', o3 '.
Since this is the data that is required for the first time in obtaining the data, it is necessary to newly read the data here. Since the input data is grouped in four phases, the data to be newly read is the four-phase input data i as shown in FIG.
2 ′, i3 ′, i1 ″, i2 ″.

Based on such a concept, FIG.
The data newly required at that timing in order to obtain the four-phase output data shown in FIG. In FIG. 11B, a circle indicated by a broken line indicates that it is not necessary to newly read data at that timing, and that data used at one or more previous timings may be used.

To summarize the above operation, in order to perform the enlargement process using the four-phase input data and obtain the four-phase output data,
It can be seen that the relationship shown in FIGS. As can be seen from FIG. 11B, the four-phase input data necessary to obtain the four-phase output data output at a constant rate is read out from the FIFO memory 2 at a constant timing and is expanded. It is necessary to temporarily store the read data instead of supplying the data to the interpolation interpolation circuit 3, select and rearrange the data, and supply the data to the enlargement interpolation circuit 3. Also, as shown in FIG. 11C, necessary four-phase input data is appropriately selected, and the same pixel data is supplied to the enlargement interpolation circuit 3 as a plurality of output data as necessary. is necessary. The selection and rearrangement circuit 5 ″ in FIG. 7 is necessary for this purpose.

Here, returning to FIG. 7, the FIFO memory 2
The following describes the operation of the enlargement process. A read enable RE is supplied from the control circuit 10 to the FIFO memory 2 to control data reading. As described above,
When data is newly read at a certain timing, the read enable RE is made valid. When data is not newly read at a certain timing, the read enable RE is made invalid.

The four-phase data read from the FIFO memory 2 is input to the selection / reordering circuit 5 ″.
The sorting circuit 5 ″ includes, for example, a selection circuit 55 and a D
Memory circuit 5 including flip-flops 561 and 562
6 and a selection circuit 57. The selection circuit 52 is controlled by a selection control signal SELoW from the control circuit 10, and the selection circuit 57 is controlled by a selection control signal SELoR from the control circuit 10. The memory circuit 56 is for temporarily storing input data, and is not limited to a D flip-flop, but may be a memory such as a buffer. Although the D flip-flops 561 and 562 are shown as one block in FIG. 1 for convenience, a D flip-flop is provided for each phase in practice. The configuration of the selection / rearrangement circuit 5 ″ is such that the input / output of the selection / rearrangement circuit 4 ″ is inverted, and both can be realized with substantially the same circuit configuration.

The two sets of four-phase data selected as described above are input to the enlargement interpolation circuit 3. Expansion interpolation circuit 3
Performs predetermined filtering based on the enlargement ratio and pixel coordinates on the input two sets of four-phase data to generate enlarged data. The enlargement interpolation circuit 3 is controlled by a control signal CTLo from the control circuit 10. Here, the enlarged interpolation circuit 3 is shown as one block for convenience.
Actually, as shown in FIG. 9, it is composed of enlargement interpolation filters 31, 32, 33, and 34 that perform enlargement processing on each set of data in two sets of four-phase data. Then, the enlargement interpolation circuit 3 outputs enlarged four-phase data as shown in FIG. When changing the enlargement ratio, the control circuit 10 outputs the control signal C
The expansion interpolation circuit 3 is also controlled by TLo.

As described above, in the image enlargement / reduction apparatus of the present invention, reduction processing is realized from the reduction interpolation circuit 1 to the FIFO memory 2, and enlargement processing is realized from the FIFO memory 2 to the expansion interpolation circuit 3. . The input four-phase data is subjected to reduction or enlargement processing as it is, and is output as four-phase data. Note that, in FIG. 7, from the reduction interpolation circuit 1 to the input of the FIFO memory 2, all operate at the same clock frequency. Similarly, everything from the output of the FIFO memory 2 to the enlargement interpolation circuit 3 operates at the same clock frequency.

If the enlargement processing is unnecessary, the reduction interpolation circuit 1
The image reduction device from the FIFO memory 2 to the FIFO memory 2 may be used. If the reduction process is unnecessary, the image expansion device from the FIFO memory 2 to the enlargement interpolation circuit 3 may be used. Further, a reduction process is performed from the reduction interpolation circuit 1 to the FIFO memory 2, and the reduction processing is performed from the FIFO memory 2 to the expansion interpolation circuit 3.
By performing the enlargement processing up to, enlargement / reduction processing at an arbitrary magnification can also be performed.

According to the image enlarging / reducing apparatus of the present invention, even if the rate of the input image data is increased, the FIFO memory 2 which is an image memory and the respective circuits of the reduction interpolating circuit 1 and the enlarging interpolating circuit 3 are used. The operating frequency may be low.
The fact that the operating frequency of the circuit may be low is extremely convenient because it can be manufactured by a simple process when an integrated circuit is formed. As the FIFO memory 2, a general-purpose DRA
M can be used as a memory core, and it is possible to provide a low-cost image enlargement / reduction apparatus that enlarges / reduces image data at a high data rate.

The number of phases of the input data may be appropriately set according to the rate of the image data. Further, in this embodiment, the input / output of the FIFO memory 2 is also four phases.
The input to the FIFO memory 2 may be, for example, eight phases, and the processing up to the selection / reordering circuit 5 ″ may be processed in eight phases. In this case, the operation speed of the FIFO memory 2 is further reduced. Alternatively, in the course of signal processing, the number of phases may be more than that of input data or output data.

Here, in the first to third embodiments described above, how the control circuit 10 determines valid data and invalid data and controls the selection / rearrangement circuits 4, 4 ', 4 ". The following describes how to determine the pixel data required for enlargement interpolation and control the selection / rearrangement circuits 5, 5 ', 5 ".

First, in the reduction process, the reduction ratio is set to S / D
Then, the pixel interval of input data is S, and the pixel interval of output data is D. Let m be the number of input pixel data.
Whether the data is valid data or invalid data is determined by the following processing. In the following equations (1) and (2),
n and n ′ are integers resulting from the division, that is, numbers of output pixel data, and... d ′ and.

S × (m−2) ÷ D = n ′ ·· d ′ (1) S × (m−1) ÷ D = n ··· d (2) IF n ′ = n THEN IF d ′ = 0 THEN n (valid) ELSE n (invalid) ELSE n (valid) IF (d '= 0 and d = 0) or (d' ≠ 0 and d ≠ 0) THEN n (valid) ELSE n (invalid) m The value of −2 and m−1 is for convenience in calculation, and is not limited to this. The above (1),
Equation (2) corresponds to two data input to the reduction interpolation filter 12 and the like in FIGS. 2 and 8.

As an example, the case of four phases of the third embodiment will be described. The numbers of the pixel data input to the reduction interpolation filters 12 to 15 in FIG. 8 are (4, 5), (5, 6),
Assuming (6, 7) and (7, 8), the reduced interpolation filter 1
In the case of 2, 4 → 3 × 3/5 = 1... 45 5 → 3 × 4/5 = 2... 2 and 2 is effective, and in the reduction interpolation filter 13, 5 → 3 × 4/5 = 2. 3 × 5/5 = 3... 0, and 3 becomes invalid.

In the reduction interpolation filter 14, 6 → 3 × 5/5 = 3... 07 → 3 × 6/5 = 3. /5=3...38→3×7/5=4...1 and 4 is valid.

Further, in the enlargement processing, the enlargement ratio is set to S /
If D, the pixel interval of input data is S, and the pixel interval of output data is D. Let n be the number of output pixel data and m be the number of input pixel data. Input pixel data that needs enlargement interpolation is determined as follows. In the following equation (3),... D means a remainder. D × (n−1) ÷ S = (m−1)... D (3)

As another example, consider the case of four phases of the third embodiment. If the number of the input pixel data is (5, 6,
7, 8), 5 → 3 × 4/5 = (3-1)... 2, interpolation with input pixel data 3, 4 and 6 → 3 × 5/5 = (4-1). , 3 → 6 × 5/5 = (4-1)... 3, and interpolation with input pixel data 4,5, 8 → 3 × 7/5 = (5-1) ... 1 and interpolation is determined by the input pixel data 5 and 6.

In the above description, only the operation of enlarging or reducing an image in the horizontal direction has been described. As can be seen from the above description, since the image data rate has already been reduced, if the image is to be scaled up and down in the vertical direction, the block corresponding to the conventional image scaling device can be used as it is. Good. That is, the selection and rearrangement circuits 4 and 5 are not required as in the case of horizontal enlargement / reduction. However, by using the image scaling device of the present invention, the length of one line memory in the vertical image scaling device can be reduced.

FIG. 12 shows an example of a configuration in which an image is reduced in the vertical direction. In FIG. 12, the horizontal reduction interpolation circuit 1
H corresponds to the reduction interpolation circuit 1 in FIG. When the image is reduced in both the horizontal and vertical directions, as an example, FIG.
As shown in (1), the vertical reduction interpolation circuit 1V first performs the vertical reduction processing for each phase, and then the horizontal reduction interpolation circuit 1H performs the horizontal reduction processing. The vertical reduction interpolation circuit 1V includes line memories 11V and 12V and vertical reduction interpolation filters 13V and 14V.
When the image data has two phases as in the present embodiment, the lengths of the line memories 11V and 12V are halved for one line. Although the required total capacity of the line memory does not change, the length of one line memory is shortened, so that the vertical reduction interpolation circuit 1V is also reduced in cost. For four phases, 1 /
It becomes 4 and becomes 1/8 if it is 8 phases.

FIG. 13 shows an example of the configuration when an image is enlarged in the vertical direction. In FIG. 13, the horizontal expansion interpolation circuit 3
H corresponds to the enlargement interpolation circuit 3 in FIG. When the image is enlarged both horizontally and vertically, as an example, FIG.
As shown in (5), the horizontal enlargement interpolation circuit 3H first performs horizontal enlargement processing, and then the vertical enlargement interpolation circuit 3V first performs vertical enlargement processing. The vertical expansion interpolation circuit 3V includes line memories 31V and 32V and vertical expansion interpolation filters 33V and 34V. When the image data has two phases as in the present embodiment, the capacity of the line memories 31V and 32V is half of one line. Therefore, the vertical enlargement interpolation circuit 3V is also reduced in cost.
If it is four phases, it becomes 1/4, and if it is eight phases, it becomes 1/8.

[0092]

As described above in detail, the image enlarging / reducing apparatus of the present invention reduces and interpolates parallel plural-phase image data and outputs the result as parallel plural-phase image data. A first selection / rearrangement circuit for selecting and rearranging the parallel multi-phase image data output from the circuit and outputting the same again as parallel multi-phase image data; and an output from the first selection / rearrangement circuit. By writing and reading the image data of the parallel plural phases, the image memory for outputting as reduced image data of the parallel plural phases, and the image data of the parallel plural phases outputted from this image memory are selected, rearranged and parallelized again. A second selection / rearrangement circuit for outputting as multi-phase image data;
And an enlargement interpolation circuit that enlarges and interpolates the parallel and multi-phase image data output from the rearranging circuit and outputs the result as parallel and multi-phase enlarged image data. It can be scaled as it is. At this time, image data of a high data rate can be scaled up and down with one image memory, and the operation speed of the circuit is reduced, so that the image scaling up device can be realized at low cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of a reduction interpolation circuit 1 in FIG.

FIG. 3 is a block diagram showing a specific configuration of an enlargement interpolation circuit 3 in FIG.

FIG. 4 is a diagram for explaining the principle of the reduction operation according to the first embodiment of the present invention.

FIG. 5 is a diagram for explaining the principle of the enlargement operation according to the first embodiment of the present invention.

FIG. 6 is a partial block diagram showing a second embodiment of the present invention.

FIG. 7 is a block diagram showing a third embodiment of the present invention.

8 is a block diagram showing a specific configuration of a reduction interpolation circuit 1 in FIG.

9 is a block diagram showing a specific configuration of the enlargement interpolation circuit 3 in FIG.

FIG. 10 is a diagram for explaining the principle of a reducing operation according to a third embodiment of the present invention.

FIG. 11 is a diagram for explaining the principle of an enlarging operation according to a third embodiment of the present invention.

FIG. 12 is a block diagram illustrating a configuration example when the present invention is developed in the vertical direction.

FIG. 13 is a block diagram illustrating a configuration example when the present invention is developed in the vertical direction.

FIG. 14 is a block diagram showing a conventional example.

[Explanation of symbols]

Reference Signs List 1 reduction interpolation circuit 1H horizontal reduction interpolation circuit 1V vertical reduction interpolation circuit 2 FIFO memory (image memory) 3 expansion interpolation circuit 3H horizontal expansion interpolation circuit 3V horizontal expansion interpolation circuit 4, 4 ', 4 ", 5, 5', 5" Selection / rearrangement circuit 10 Control circuit 41,44,46,51,56 Memory circuit 42,45,47,52,55,57 Selection circuit 43 Switching circuit 411-413,511-513,461,462,5
61,562 D flip-flop (memory)

Claims (15)

[Claims] 1. An image enlarging apparatus for enlarging an image, comprising: an image memory for writing image data of a plurality of parallel phases and reading the image data as the image data of the parallel plurality of phases; A selection and rearrangement circuit for selecting and rearranging and outputting again as parallel multi-phase image data; and a parallel and multi-phase enlarged image obtained by expanding and interpolating the parallel and multi-phase image data output from the selection and rearrangement circuit. An image enlargement device comprising: an enlargement interpolation circuit that outputs data. 2. An image reducing apparatus for reducing an image, comprising: a reducing interpolator for reducing and interpolating image data of a plurality of parallel phases to output as image data of a plurality of parallel phases; A selection and rearrangement circuit that selects and rearranges the image data and outputs again as parallel multi-phase image data, by writing and reading the parallel multi-phase image data output from the selection and rearrangement circuit, An image reducing device comprising: an image memory that outputs reduced image data of a plurality of parallel phases. 3. An image enlargement / reduction apparatus for enlarging / reducing an image, comprising: a reduction interpolation circuit for reducing and interpolating image data of a plurality of parallel phases and outputting the same as image data of a plurality of parallel phases; A first selection / rearrangement circuit for selecting and rearranging the image data of a plurality of phases and outputting again as parallel multi-phase image data; and an image of the parallel multi-phase output from the first selection / rearrangement circuit. By writing and reading the data, an image memory that outputs as parallel multi-phase reduced image data, and the parallel multi-phase image data output from the image memory are selected and rearranged as parallel multi-phase image data again. A second selecting / rearranging circuit to be output; and a parallel plural-phase image data obtained by enlarging and interpolating the parallel plural-phase image data output from the second selecting / rearranging circuit. Image scaling apparatus characterized by being configured a scale-up interpolation circuit which outputs as a large image data. 4. The image processing apparatus according to claim 1, wherein the selecting / rearranging circuit includes at least one memory circuit for temporarily storing the image data of the plurality of parallel phases, and the image data of the plurality of parallel phases output from the memory circuit or the image memory. 2. The image enlarging apparatus according to claim 1, further comprising a selection circuit that selects image data from the image data and newly outputs the image data as parallel multi-phase image data. 5. The at least one memory circuit for temporarily storing image data of a plurality of parallel phases, and selectively writing the image data of the plurality of parallel phases into the memory circuit. The image enlargement device according to claim 1, further comprising a selection circuit. 6. The memory according to claim 1, wherein the selection / rearrangement circuit includes a memory circuit having two memories for temporarily storing the image data of the parallel plural phases, and a memory circuit for storing the image data of the parallel plural phases in one of the two memories. A first selection circuit for supplying;
And a second selection circuit for selecting and outputting image data necessary for enlargement interpolation by the enlargement interpolation circuit from the image data output from the two memories.
The image enlargement device as described in the above. 7. The selecting / rearranging circuit includes at least one memory circuit for temporarily storing parallel multi-phase image data, and the parallel multi-phase image data output from the memory circuit or the reduction interpolation circuit. 3. The image reduction apparatus according to claim 2, further comprising a selection circuit that selects image data from among the image data and newly outputs the image data as parallel multi-phase image data. 8. The selecting / rearranging circuit includes at least one memory circuit for temporarily storing image data of a plurality of parallel phases, and selectively writes the image data of the plurality of parallel phases to the memory circuit. 3. The image reduction device according to claim 2, further comprising a selection circuit. 9. The selecting / rearranging circuit selects a memory circuit having two memories for temporarily storing image data of a plurality of parallel phases, and selects only valid image data from the image data of the plurality of parallel phases. And a second selection circuit that selects one of the two memories and outputs the parallel multi-phase image data. Item 3. The image reduction device according to Item 2. 10. The first selection / rearrangement circuit includes at least one memory circuit for temporarily storing image data of a plurality of parallel phases, and a plurality of parallel phase signals output from the memory circuit or the reduction interpolation circuit. A selection circuit for selecting image data from among the image data and outputting the new image data as parallel multi-phase image data. The second selection / reordering circuit temporarily stores the parallel multi-phase image data. At least one memory circuit for storing, and a selection circuit for selecting image data from the parallel multi-phase image data output from the memory circuit or the image memory and newly outputting the same as parallel multi-phase image data 4. The image enlargement / reduction apparatus according to claim 3, wherein: 11. The first and second selecting / rearranging circuits include at least one memory circuit for temporarily storing parallel multi-phase image data, and the parallel multi-phase image data for the memory circuit. 4. The image enlargement / reduction apparatus according to claim 3, further comprising a selection circuit for selectively writing data. 12. The first selection / rearrangement circuit includes a first memory circuit having two memories for temporarily storing parallel multi-phase image data, and a first memory circuit having more effective than the parallel multi-phase image data. A first selection circuit that selects only image data and supplies it to one of the two memories in the first memory circuit, and a second selection circuit that selects the two memories in the first memory circuit and A second selection circuit that outputs two image data, the second selection and reordering circuit includes a second memory circuit that has two memories that temporarily store the image data of the parallel multiple phases, A third selection circuit that supplies the parallel plural-phase image data to one of the two memories in the second memory circuit, and an image output from the two memories in the second memory circuit. 4. The image enlargement / reduction apparatus according to claim 3, further comprising a fourth selection circuit for selecting and outputting image data necessary for enlargement interpolation in the enlargement interpolation circuit from the image data. 13. An image enlarging method for enlarging an image, comprising: a first step of writing image data of a plurality of parallel phases and reading it as image data of a plurality of parallel phases; A second step of selecting and rearranging the image data of a plurality of phases and outputting the image data again as parallel multi-phases; And a third step of outputting as phase enlarged image data. 14. An image reduction method for reducing an image, comprising: a first step of reducing and interpolating image data of a plurality of parallel phases to output as image data of a plurality of parallel phases; A second step of selecting and rearranging the parallel plural-phase image data and outputting the same again as the parallel plural-phase image data; and writing and reading the parallel plural-phase image data output in the second step. And outputting the reduced image data as parallel multi-phase reduced image data. 15. An image enlargement / reduction method for enlarging / reducing an image, comprising: a first step of reducing / interpolating parallel plural-phase image data and outputting as parallel plural-phase image data; A second step of selecting and rearranging the outputted parallel plural-phase image data and outputting the same again as the parallel plural-phase image data; and writing the parallel plural-phase image data outputted in the second step. A third step of outputting as parallel multiple-phase reduced image data by reading the image data; and selecting and rearranging the parallel multiple-phase image data output in the third step to obtain parallel multiple-phase image data again. A fourth step of outputting, and expanding the parallel plural phases by enlarging and interpolating the image data of the parallel plural phases outputted in the fourth step. Image scaling method characterized by comprising a fifth step of outputting the image data.