JP2001036501A - Interference canceller device and method for detecting path timing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interference canceller device having enhanced reception characteristic. SOLUTION: The multi-stage type interference canceller device is provided with an interference canceller unit to eliminate an interference noise included in a received signal adopting a code division multiple address system to each stage. The device consists of an SIR (signal to interference noise ratio) level measurement section 15 that decides number of data of preceding path timing to be summed by the SIR measured in a pre-stage, adder means 16, 17, 18, 19, 20, 22 that sum the data of the preceding path timing of the data number decided by the SIR level measurement section 15 to the data of the path timing of the received signal, and a multiplier 23 that divides the sum result by the adder means by the data number of the path timing summed by the adder means. Thus, the path timing and the reception characteristic are enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interference canceller apparatus which has been studied as one of technical elements for realizing high quality and large capacity in CDMA mobile communication, and a path timing used in the interference canceller apparatus. It relates to the detection method.

[0002]

2. Description of the Related Art In recent years, an interference canceller has been studied as one of the technical elements for realizing high quality and large capacity in CDMA mobile communication.

FIG. 6 shows a configuration of a conventional interference canceller apparatus. The interference canceller shown in FIG. 6 is an M-stage N-user parallel type multi-stage interference canceller. As shown in FIG. 6, this interference canceller apparatus includes N path search function units 30 provided for N users and m × N interference estimation units (hereinafter referred to as IEU). ) Unit 33, and a delay unit 31 and an adder 32 provided in each stage of m stages up to m-1.

[0004] The interference canceller apparatus having the above configuration converts the received signal into an IEU unit 33 and a path search function unit 3 for each user.
0, input to the delay unit 31. Then, the path search function unit 30 searches for path timing using the spreading code of each user. The path timing detected by the path search function unit 30 is input to the IEU unit 33 of each stage.

FIG. 7 shows the configuration of the IEU unit 33. As shown in FIG. 7, the IEU unit 33 despreads the input received signal for each path branch using the path timing transferred from the path search function unit 30, Perform replica addition and transmission path estimation. Thereafter, RAKE combining section 35 sets RA
The KE combining and diversity combining unit 36 performs diversity combining, and the SIR level measuring unit 37 performs SIR (Si
gnal to Interference Ratio).

[0006] The result of RAKE combining and diversity combining is determined, and a symbol replica is generated in a symbol replica generating section 38 and transferred to the IEU section 33 in the next stage. The chip replica generator 39 respreads the symbol replica generated earlier, outputs a chip replica, and transfers the chip replica to the adder 32.

Further, a chip replica output from each IEU unit is subtracted by an adder 32 from a received signal (residual signal) obtained by delaying the processing delay of the IEU unit 33 by a delay unit 31, and the residual signal is converted to the next signal. Is transferred to the stage. The same operation is repeated until the final stage (stage M). At stage M, each IEU unit performs RAKE combining and diversity combining, and outputs a demodulated signal.

[0008]

However, in the conventional interference canceller having the above configuration, the first path timing obtained by the path search function unit 30 is transmitted to the IEU unit 33 of each stage as shown in FIG. Is entered. Therefore, in the case of a user who receives a large amount of interference and has a weak reception electric field, if the first path search function unit erroneously detects the path timing, it affects the final stage. This causes a problem that the reception performance for the user is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide an interference canceller apparatus and a path timing detection method which improve reception characteristics by obtaining an optimum path timing for each stage. I do.

[0010]

In order to achieve the above object, an interference canceller apparatus according to the present invention comprises an interference canceller unit for removing interference noise contained in a received code division multiple access (CDMA) signal. A multi-stage interference canceller device including a plurality of stages connected to a stage, wherein a predetermined number of past paths determined by a signal-to-interference ratio (SIR) measured at a preceding stage. A predetermined process is performed by using a value obtained by adding the timing data to the path timing of the received signal as the path timing of the stage.

The above-mentioned interference canceller unit comprises a control means for determining the number of data of the past path timing to be added to the path timing of the received signal based on the SIR measured in the previous stage, and a data number determined by the control means. A moving average comprising: adding means for adding the data of the past path timing and the path timing of the received signal; and dividing means for dividing the addition result by the adding means by the number of data of the path timing added by the adding means. It is desirable to have processing means.

The above-mentioned interference canceller apparatus is provided for each of different paths with path timing detecting means for detecting a path timing of a received signal using a spreading code set for each user, and is provided with a moving average processing means. A despreading unit that despreads a received signal in the first stage using the detected path timing and despreads a received signal that has been subjected to predetermined processing in the previous stage in the other stages is different from the despreading unit. A symbol replica adding means for adding a symbol replica of the previous stage to a signal despread by the despreading means provided for each path, and a signal provided for each of different paths and received after symbol replica addition using the symbol replica adding means. Each of the above-described units including a transmission line estimation unit that measures a delay profile of a transmission line received by a signal is provided for each of a plurality of branches. Rake combining is performed by using the signals processed by the above-described means provided for each path. Using the rake combining means provided for each branch, and the signal after rake combining output for each branch. Diversity combining means for combining the diversity, symbol replica generating means for generating a symbol replica using the signal after the diversity combining, and a symbol replica obtained by the symbol replica generating means to respread to generate a chip replica. Chip replica generation means, delay means for delaying a signal subjected to predetermined processing in the previous stage in the first stage, and a reception signal delayed in the other stage, or Subtraction means for subtracting a chip replica from a signal subjected to predetermined processing and performing predetermined processing; It may have.

The above-described interference canceller device may be a parallel type interference canceller device in which an interference canceller unit corresponding to a user is connected in parallel to each stage.

The above-described interference canceller device is preferably a series-connected interference canceller device in which an interference canceller unit corresponding to a user is connected in series to each stage.

When the SIR calculated in the preceding stage is better than a predetermined threshold, the control means reduces the number of past path timing data to be added to the received signal path timing, and When the SIR calculated at the stage is lower than a predetermined threshold, the number of past path timing data to be added to the reception signal path timing may be increased.

A path timing detecting method according to the present invention is provided in each stage with an interference canceller unit for removing interference noise included in a received code division multiple access (CDMA) signal, and a multistage in which a plurality of stages are connected. Is a path timing detection method in an interference canceller device of the type, wherein the SIR (Si
gnal to Interference Ratio) is a value obtained by adding a predetermined number of past path timing data determined by the signal to interference noise ratio to the reception signal path timing.
A predetermined process is performed as the pass timing of the stage.

The above-described interference canceller unit includes an additional data number calculating step of determining the number of past path timing data to be added to the path timing of the received signal based on the SIR measured in the preceding stage, and an additional data number calculating step. An adding step of adding the past path timing data of the number of data determined by the above and the reception signal path timing, and a dividing step of dividing the addition result by the adding step by the number of past path timing data. It is preferable to have a moving average processing step.

[0018]

Embodiments of the present invention will be described in detail with reference to the accompanying drawings. Referring to FIGS. 1 to 5, an embodiment according to the present invention is shown.

First, the configuration of the first embodiment according to the present invention will be described with reference to FIG. FIG. 1 shows, as a first embodiment according to the present invention, a configuration of a parallel type multi-stage interference canceller apparatus for m stages and N users. Note that m and N are arbitrary natural numbers.

As shown in FIG. 1, the interference canceller apparatus includes N path search function units 1 provided for N users, m × N IEU units 4, and m × N
The moving average processing unit 5 includes delay units 2 and adders 3 provided for m stages up to m-1 stages.

The received signal includes a path search function unit 1
The signal is input to the delay unit 2 and the IEU unit 4. The path search function unit 1 searches for a path timing using a despreading code assigned to each user. The path timing obtained by the path search function unit 1 is input to a moving average processing unit 5 provided in each stage.

FIG. 2 shows the configuration of the moving average processing unit 5. As shown in FIG. 2, the moving average processing unit 5
Is a SIR level measuring unit 15, a buffer 16, shift registers 17 and 18, an adder 19, and a delay unit 20.
, Shift counter 21, buffer 22, multiplier 2
And 3.

The SIR level measuring section 15 determines how many points of past path timing data should be integrated based on the SIR level of the previous stage, and notifies the shift register 18 of the shift amount.

The buffer 16 holds the path timing data from the path search function section 1 during the integration calculation, and after the integration calculation, the shift register 17 for the next integration calculation.
To transfer the path timing data.

The buffer 22 stores the result of addition (integration result) by the adder 19, overwrites the data during the integration calculation, and transfers the data to the multiplier 23 after the completion of the integration calculation.

The shift register 17 is a register for preparing the next integral, holds data during the integration calculation, and after receiving the new path timing data from the buffer 16 after the integration calculation, stores the path timing data in the shift register 18. Copy

The shift register 18 is a register for integration, and shifts the data of the pass timing during the integration calculation. The number of shifts is determined by the SIR level measurement unit 1.
According to the measurement result of No. 5.

The shift counter 21 counts the number of shifts of the shift register 18 to perform the averaging process, and sends the reciprocal of (the number of shifts + 1) to the multiplier 20.

The multiplier 23 multiplies the reciprocal of (the number of shifts + 1) from the shift counter 21 by the addition result from the buffer 22, and transfers the multiplication result to the IEU unit 4 as stage path timing data.

Next, the configuration of the IEU unit 4 will be described with reference to FIGS. 3 and 4, FIG.
The configuration of an IEU unit having a two-branch four-path structure is shown.

The IEU unit 4 includes a despreading unit 6, a symbol replica adding unit 7, a transmission channel estimating unit 8 as shown in FIG. 3, and a RAKE combining unit 9 and a diversity combining unit as shown in FIG. 10, a SIR measurement unit 11, a symbol replica generation unit 12, and a chip replica generation unit 13. With this configuration, RAKE combining is performed by despreading for four paths, adding a preceding-stage symbol replica, and estimating a transmission path, and diversity combining is performed using signals after RAKE combining from two branches.

The despreading section 6 performs despreading processing on the input received signal (residual signal) using the path timing data calculated by the moving average processing section 5.

The symbol replica adding section 7 includes a despreading section 6
And the symbol replica calculated in the previous stage is added to the signal despread. The stage a shown in FIG.
, Symbol replica addition is not performed.

The transmission channel estimator 8 uses the signal to which the symbol replica has been added by the symbol replica adder 7 to
The delay profile of the transmission path on which the received signal was received is measured. The signal whose transmission path is estimated is transferred to the RAKE combining section 9 and the symbol replica generating section 12.

The RAKE combining section 9 performs RAKE combining using the signal transferred from the transmission path estimating section 8, and the diversity combining section 10 performs diversity combining using the RAKE combined signal.

The SIR measuring section 11 uses the signal after the diversity synthesis to generate an SIR (Signal to Interference Rat).
io) is measured. In the SIR measurement method, the transmission power of a received signal (residual signal) in a certain section (such as a pilot symbol section) is integrated to obtain S + I, and the power after despreading by the next transferred path timing is the same. S is obtained by integrating over the interval. Then, the power I of the interference signal is calculated, and the ratio of S and I, that is, SIR is obtained.

The symbol replica generation unit 12 generates a symbol replica using the signal whose transmission path has been estimated. The generated symbol replica is input to the symbol replica adding section 7 in the next stage.

The chip replica generator 13 respreads the symbol replica generated by the symbol replica generator 12, outputs a chip replica, and outputs the chip replica to the adder 3.

In the first embodiment according to the interference canceller apparatus of the present invention, the SIR measured in the previous stage is used, and in the moving average processing of the path timing, the integration interval is varied by controlling the number of shifts of the shift register. In addition, the receiving characteristic is improved by obtaining an optimal path timing for each stage.

A method of calculating an optimal path timing by the moving average processing unit 5 for achieving this object and a processing operation performed using the detected path timing will be described in detail.

The received signal is input to a path search function unit 1, a delay unit 2, and an IEU unit 4. The path search function unit 1 performs a path search using the spreading code of each user. The data of the path timing detected by the path search function unit 1 is held in the buffer 16. The buffer 16 transfers the held data to the shift register 17 for integration calculation.

In the shift register 17, data of past path timings from the path search function unit 1 are arranged in order. The shift register 17 copies the data of the pass timing to the shift register 18.

On the other hand, the SIR of the previous stage is measured by the SIR level measuring section 15 and the shift register 18
Is determined (shift interval). When the number of shifts is determined, the data of the path timing is added by the adder 19 and the integral calculation is performed. During the integration calculation, the buffer 16 and the shift register 17 keep the data held.

The buffer 22 overwrites the data sent from the adder 19 during the integration calculation.

The shift counter 21 counts the number of shifts of the shift register 18 in order to perform an averaging process.

When the integration calculation is completed, the integration result held in the buffer 22 and the count number of the shift counter 21 +
The reciprocal of 1 (for example, 1/5 if the shift number is 4) is transferred to the multiplier 23. Then, the data subjected to the moving average processing, which is the result of the multiplication, is transferred to the IEU unit 4 for use as the data of the path timing of the stage.

At the same time as the completion of the integration calculation, the shift register 17 receives the data of the new path timing from the buffer 16 and copies it to the shift register 18 for the next calculation. Further, the SIR level measuring unit 1
The information of the number of shifts from 5 is received, and integral calculation is performed.
By repeating the above operation, the path timing of the stage is obtained.

The shift number of the shift register 18 controlled by the SIR level measuring section 15 is controlled as follows. When the SIR of the previous stage is lower than a predetermined threshold value, it is considered that the path timing is not good, and the accuracy of the path timing is improved by increasing the number of shifts and increasing the integration section. Also, SIR of the previous stage
Is higher than a predetermined threshold value, it is considered that the path timing is good, and a certain default value is used as the number of shifts.

Since there is no SIR input at stage a, the number of shifts (integration section) of the shift register 18 for moving average processing is set to an appropriate value, and the primary path timing is transferred to the IEU unit 4.

The IEU unit 4 performs despreading for each path / branch, addition of the symbol replica of the previous stage, and transmission path estimation for the input received signal using the path timing transferred from the moving average processing. Do. Then RAK
E combining and diversity combining are performed, and the SIR level is measured by the SIR measuring unit.

In the SIR measurement method, S + I is obtained by integrating transmission power of a received signal (residual signal) in a certain section (eg, a pilot section). Next, the power after despreading by the transferred path timing is integrated to obtain S, the power I of the interference signal is calculated, and the ratio of S to I, ie, S
Find IR.

The result of RAKE combining and diversity combining is determined, and a symbol replica is generated in the symbol replica generating section 12 and transferred to the IEU section 4 in the next stage. Further, the chip replica generation unit 13 re-spreads the symbol replica generated previously, outputs a chip replica, and transfers the chip replica to the adder 3.

The same operation is performed in the final stage (stage M).
Repeatedly, in stage M, each IEU unit
A demodulated signal after AKE combining and diversity combining is output.

In the above-described embodiment, the optimal path timing for each stage is obtained by performing the moving average processing of the integral section variable type using the SIR of the previous stage for each stage, thereby improving the path timing. And
Reception characteristics can be improved.

Next, a second embodiment according to the present invention will be described with reference to FIG. In the first embodiment described above, each stage includes an interference canceller unit for removing interference noise, and a plurality of stages are connected in parallel.
This is a multi-stage interference canceller device having a stage N user structure. On the other hand, the present embodiment is a multi-stage interference canceller apparatus having an m-stage N user structure in which the interference canceller units are connected in series.

In the second embodiment shown in FIG. 5, the path search function section 1, m × N IEU sections 4, m × N moving average processing sections 5, and m stages It is composed of each stage up to m-1 and a delay unit 2 and an adder 3 provided up to m-1 N-1 users.

In the first embodiment, a path search is performed for a plurality of users (N) at a time, the path timing data is collectively transferred to the IEU unit, and a chip replica is calculated for each user. The data and symbol replica were transferred to the next stage by subtracting the chip replica. That is, the processing is performed with a delay for each stage.

On the other hand, in the present embodiment, as shown in FIG. 5, a path search is performed by the path search function unit 1 with a time lag for each user, and when processing is performed up to the user N at that stage, Processing is performed from the user 1 in the next stage.

Even in the interference canceller having such a configuration, the SIR of the previous stage is used for each stage,
By performing the moving average processing of the integral section variable type, an optimal path timing is obtained for each stage, so that the path timing can be improved and the reception characteristics can be improved.

[0060]

As apparent from the above description, the present invention is obtained by adding a predetermined number of past path timing data determined by the SIR measured in the preceding stage to the path timing of the received signal. By performing a predetermined process using the value as the path timing of the stage, the path timing can be improved, and the reception characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a first exemplary embodiment according to the present invention.

FIG. 2 is a diagram illustrating a configuration of a moving average processing unit.

FIG. 3 is a diagram illustrating a configuration of an IEU unit.

FIG. 4 is a diagram illustrating a configuration of an IEU unit.

FIG. 5 is a diagram illustrating a configuration of a second embodiment according to the present invention.

FIG. 6 is a diagram illustrating a configuration of a conventional interference canceller device.

FIG. 7 is a diagram illustrating a configuration of an IEU unit used in a conventional canceller device.

[Explanation of symbols]

 Reference Signs List 1 path search function unit 2 delay unit 3 adder 4 IEU unit 5 moving average processing unit

Claims (8)

[Claims] 1. Received code division multiple access (CDMA)
A multi-stage interference canceller device having an interference canceller unit for removing interference noise included in a signal of each system in each stage, and a plurality of stages connected to each other, wherein an SIR (Signal to Interf
erence Ratio: a predetermined number of past path timing data determined by the signal-to-interference-noise ratio) is added to the path timing of the received signal, and a value obtained by performing the predetermined processing is set as the path timing of the stage. A featured interference canceller device. 2. The interference canceller unit, comprising: a control unit that determines the number of past path timing data to be added to the path timing of a received signal based on the SIR measured in the preceding stage; Adding means for adding the data of the past path timing of the received data number and the path timing of the received signal; and dividing the result of addition by the adding means by the number of data of the path timing added by the adding means. 2. The interference canceller apparatus according to claim 1, further comprising a moving average processing unit comprising: 3. A path timing detecting means for detecting a path timing of a received signal by a spreading code set for each user, and a path provided for each different path and detected by said moving average processing means. Despreading means for despreading a received signal in a first stage using a timing, and despreading a received signal subjected to a predetermined process in a previous stage in other stages; And a symbol replica adding means for adding a symbol replica of the previous stage to the signal despread by the despreading means, and a received signal provided by using the signal after the symbol replica addition provided for each of the different paths. Each of the above-mentioned means including a transmission path estimating means for measuring a delay profile of a received transmission path is provided for each of a plurality of branches, and for each of different paths. Rake combining means for performing rake combining using the signals processed by the above-described respective means, and a rake combining means provided for each branch, and diversity output using the rake combined signal output for each branch. Diversity combining means for combining, symbol replica generating means for generating a symbol replica using the signal after the diversity combining, and re-spreading of the symbol replica obtained by the symbol replica generating means to generate a chip replica Chip replica generation means; delay means for delaying a received signal in the first stage, and a signal subjected to predetermined processing in the previous stage in other stages; and a reception signal delayed by the delay means Or subtracting the chip replica from the signal subjected to the predetermined processing, 3. The interference canceller device according to claim 2, further comprising a subtraction unit for performing a predetermined process. 4. The interference canceller according to claim 1, wherein the interference canceller is a parallel type interference canceler in which an interference canceller unit corresponding to a user is connected to each stage in parallel. An interference canceller device as described. 5. The interference canceller device according to claim 1, wherein the interference canceller device is a series connection type interference canceller device in which an interference canceller unit corresponding to a user is connected in series to each stage. 2. The interference canceller device according to item 1. 6. The control means, when the SIR calculated in the preceding stage is better than a predetermined threshold, reduces the number of past path timing data to be added to the reception signal path timing. 3. The interference canceller according to claim 2, wherein when the SIR calculated in the previous stage is lower than a predetermined threshold, the number of past path timing data to be added to the reception signal path timing is increased. apparatus. 7. Received code division multiple access (CDMA)
A method for detecting a path timing in a multi-stage interference canceller device comprising an interference canceller unit for removing interference noise included in a signal of a system in each stage, and connecting a plurality of stages, wherein the measurement is performed in a previous stage. SIR (Signal to Interf
erence Ratio: a predetermined number of past path timing data determined by the signal-to-interference-noise ratio) is added to the path timing of the received signal, and a value obtained by performing the predetermined processing is set as the path timing of the stage. Characteristic path timing detection method. 8. An additional data number calculating step of determining the number of past path timing data to be added to the received signal path timing based on the SIR measured in the preceding stage, the interference canceller unit comprising: An adding step of adding past path timing data of the number of data determined in the calculating step and a path timing of the received signal; and dividing an addition result by the adding step by the number of data of the past path timing. 8. The path timing detecting method according to claim 7, further comprising a moving average processing step including a dividing step.