JP2001036090A - Method for fabrication of electrooptical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of masks of patterning and to improve the yield of a TFT by performing the reverse exposure of a light-shielding film where each impurity region of gate wiring and an active layer is formed under the active layer and forming a pixel part and a drive circuit with n- and p- channel-type thin-film transistors on the same substrate. SOLUTION: Light-shielding films 102a-102f with a light-shielding property are formed on a surface at a side where the TFT of a substrate 101 is formed. An alignment marker is subjected to the first patterning by a conductive film. Then, the light-shielding film is covered and an underlying film that is made of an insulation film including silicon is formed by the plasma CVD method. An amorphous silicon film is formed on the underlying film and is formed by a semiconductor film containing amorphous structure as an active layer when a thin-film transistor is completed finally. A laser beam is applied to a polysilicon film 104 and a polysilicon film 105 for improving crystallizability is formed. Then, resist 106a-106e is eliminated, a p-type impurity element is added through a protection film 108 containing silicon, and resist 110a-100f is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electro-optical device having an element or a circuit composed of a thin film transistor (hereinafter, referred to as TFT) on a substrate having an insulating surface. Further, the present invention relates to an electronic device including an electro-optical device manufactured using the present invention.

[0002]

2. Description of the Related Art Electro-optical devices having integrated circuits formed of TFTs on a substrate have been developed. Liquid crystal display,
An EL display device or a contact image sensor is known as a typical example. In particular, a TFT having a polysilicon film (polycrystalline silicon film) as an active layer (hereinafter referred to as poly-SiTF)
T) is a T using a conventional amorphous silicon film.
Attention has been paid to the higher field-effect mobility than FT (hereinafter a-SiTFT).

As an electro-optical device using a poly-Si TFT, a liquid crystal display device has attracted a great deal of attention at present, and has already begun to appear on the market. However, although the poly-Si TFT has high performance, the manufacturing cost is higher than the a-Si TFT.
Therefore, reducing the manufacturing cost of the poly-Si TFT has become an important issue in securing a market for a liquid crystal display device using the poly-Si TFT.

[0004]

An object of the present invention is to reduce the number of masks required for patterning to reduce the number of masks.
It is an object to improve the manufacturing yield of T and reduce the manufacturing cost of an electro-optical device using a TFT. An object of the present invention is to provide a technique for reducing the manufacturing cost of an electro-optical device, thereby reducing the manufacturing cost of an electronic device including the electro-optical device.

[0005]

According to the present invention, the number of patterning steps (photolithography steps) used in the manufacturing process of a TFT is minimized to realize a high-yield manufacturing process which is not affected by patterning accuracy. Reduce the manufacturing cost of the device. In order to reduce the number of masks, each impurity region (source region, drain region or LDD region) of the gate wiring and the active layer is used.
Is formed in a self-aligned manner by back-surface exposure using a light-shielding film provided below the active layer.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to the following examples.

[Embodiment 1] An embodiment of the present invention is shown in FIGS.
This will be described with reference to FIG. Here, a method for simultaneously manufacturing a pixel portion and a driver circuit provided therearound is described. However, for the sake of simplicity, with respect to the driving circuit, a CMOS circuit which is a basic circuit such as a shift register circuit and a buffer circuit and a driving circuit which forms a sampling circuit
A channel type TFT is illustrated.

In FIG. 1A, it is desirable to use a glass substrate or a quartz substrate as the substrate 101, but any substrate may be used as long as it is translucent. If heat resistance permits, a plastic substrate can be used.

Next, on the surface of the substrate 101 on the side where the TFT is formed, light shielding films 102a to 102
102f is formed. As the thin film having a light-blocking property, a conductive film such as an aluminum film, a tantalum film, a tungsten film, a titanium film, an alloy film thereof, a silicide film, or an insulating film in which a pigment or a carbon material is dispersed can be used. .

The thickness of the light-shielding films 102a to 102f is preferably as small as possible, and is preferably from 100 to 200 nm.
Further, it is preferable that the edge portion of the light shielding film has a tapered shape. By doing so, the flatness of the thin film formed on the light shielding film is increased as much as possible.

Here, a first patterning step is performed. At this time, an alignment marker to be used for positioning at the time of patterning in the future is formed using the above conductive film. In the case of this embodiment, since the alignment marker can be formed simultaneously with the formation of the light shielding film, the trouble of separately forming the alignment marker (an increase in the number of patterning steps) can be prevented.

Next, an underlying film made of an insulating film containing silicon (in this specification, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film) covering the light shielding films 102a to 102f. 103 is formed to a thickness of 100 to 400 nm by a plasma CVD method or a sputtering method.

In this specification, silicon nitride oxide
An oxide film is an insulating film represented by SiOxNy,
Refers to an insulating film containing silicon and nitrogen at a predetermined ratio. In this embodiment
Means that the base film 102 contains 20 to 50 atomic% of nitrogen.
(Typically 20-30 atomic%) including 100nm thickness
Silicon oxynitride film and nitrogen at 1-20 atomic% (reference
200nm thick nitriding containing 5-10 atomic%
A stacked film with a silicon oxide film is used. The thickness is
There is no need to limit to values. In addition, silicon nitride oxide film
The content ratio (atomic% ratio) of nitrogen and oxygen contained is 3: 1 to 1
The ratio may be 1: 3 (typically 1: 1). Also, nitriding
The silicon oxide film is made of SiH_FourAnd N_TwoO and NH _ThreeThe raw material gas
What is necessary is just to manufacture.

Next, 30 to 120 nm is formed on the underlying film 103.
An amorphous silicon film (not shown) having a thickness of preferably 50 to 70 nm is formed by a known film forming method. Note that the present invention is not limited to an amorphous silicon film, and may be any semiconductor film having an amorphous structure. The semiconductor film including an amorphous structure includes an amorphous semiconductor film and a microcrystalline semiconductor film, and further includes a compound semiconductor film including an amorphous structure such as a silicon germanium film having an amorphous structure. Also, if the film is formed with the above film thickness, the TFT
Is completed, the active layer has a thickness of 10 to 100 nm (preferably 30 to 50 nm).

Then, a polysilicon film 104 is formed according to a technique described in Japanese Patent Application Laid-Open No. Hei 7-130652 (corresponding to US Pat. No. 5,643,826). The technique described in the publication discloses a catalyst element (nickel, cobalt,
This is a crystallization means using one or more elements selected from germanium, tin, lead, palladium, iron, and copper, typically nickel).

More specifically, a heat treatment is performed while a catalytic element is held on the surface of the amorphous silicon film to change the amorphous silicon film into a polysilicon film. In this embodiment, the technology described in the first embodiment of the publication is used, but the technology described in the second embodiment may be used. In this embodiment, the polysilicon film is used as an example. However, the present invention is not limited to the polysilicon film, and may be any semiconductor film including a crystalline structure (including a single crystal silicon film). (Fig. 1 (A))

Although the amorphous silicon film depends on the hydrogen content, it is preferably heated at 400 to 550 ° C. for several hours to perform a dehydrogenation treatment.
It is desirable to perform a crystallization step. Although an amorphous silicon film may be formed by another manufacturing method such as a sputtering method or an evaporation method, it is preferable that impurity elements such as oxygen and nitrogen contained in the film be sufficiently reduced.

Here, since the underlayer film and the amorphous silicon film can be formed by the same film forming method, both may be formed continuously. Once the base film is formed, it is possible to prevent the surface from being contaminated by not once exposing it to the atmosphere, thereby reducing the variation in the characteristics of the TFT to be manufactured.

Next, the polysilicon film 104 is irradiated with light (laser light) emitted from a laser light source (hereinafter, referred to as laser annealing) to form a polysilicon film 105 having improved crystallinity. As the laser beam, a pulse oscillation type or continuous oscillation type excimer laser beam is desirable, but a continuous oscillation type argon laser beam may be used. The beam shape of the laser beam may be linear or rectangular. (FIG. 1 (B))

Further, instead of laser light, light emitted from a lamp (hereinafter, referred to as lamp light) may be irradiated (hereinafter, referred to as lamp annealing). As the lamp light, lamp light emitted from a halogen lamp, an infrared lamp, or the like can be used. Further, furnace annealing using an electric heating furnace can be used in combination or as a substitute.

In this embodiment, a laser annealing step is performed by processing a pulse oscillation type excimer laser beam into a linear shape.
Laser annealing conditions were as follows: XeCl gas was used as the excitation gas, the processing temperature was room temperature, and the pulse oscillation frequency was 30 Hz.
And a laser energy density of 250 to 500 mJ / cm ²
(Typically 350 to 400 mJ / cm ² ).

The laser annealing step performed under the above conditions has the effect of completely crystallizing the amorphous region remaining after thermal crystallization and reducing defects in the already crystallized crystalline region. Such an effect can also be obtained by optimizing the lamp annealing conditions.

Next, resists 106a to 106f are formed by a back surface exposure method using the light shielding films 102a to 102f.
At this time, conditions are set such that the pattern shapes of the light-shielding film and the resist substantially match.

Then, using the resists 106a to 106f as a mask, an impurity element imparting n-type (hereinafter referred to as an n-type impurity element) is added to the impurity region 107 exhibiting n-type.
a to 107f are formed. Note that as the n-type impurity element, an element belonging to Group XV, typically, phosphorus or arsenic can be used.

In this embodiment, n-type impurity regions 107a to 107f are formed by ion doping using phosphine (PH ₃ ). The concentration of phosphorus in this region is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ (typically 2 × 10 ²¹ atoms / cm ³ ).
10 ^{20 to} 5 × 10 ²¹ atoms / cm ³ ). Note that in this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (a). (Fig. 1 (C))

The concentrations described in this specification are all S
It is a measured value when measured in the lowest concentration region by IMS (mass secondary ion analysis).

Next, after removing the resists 106a to 106f, a protective film 108 made of an insulating film containing silicon is formed. This protective film 108 has a meaning to prevent the polysilicon film from being directly exposed to plasma at the time of adding an impurity and to enable fine concentration control. In addition, the thickness of the protective film 108 plays a role in controlling the amount of light wraparound when performing a subsequent back surface exposure step.

The amount of light wrap around is determined by the n-channel TFT
Of the LDD region is determined. In this embodiment, the thickness of the protective film 108 is set to 0.2 to 1.0 μm in order to set the amount of light wrap around to 0.3 to 1.0 μm. However,
Since it is possible to control the amount of wraparound also by the exposure conditions, it is not necessary to limit to this film thickness.

Next, an impurity element imparting p-type (hereinafter, referred to as a p-type impurity element) is added through the protective film 108. As the p-type impurity element, an element belonging to Group 13 typically, typically, boron or gallium can be used. This step (referred to as a channel doping step)
This is a step for controlling the threshold voltage of the FT. Here, boron is added by an ion doping method using diborane (B ₂ H ₆ ).

Thus, 1 × 10 ¹⁵ to 1 × 10 ¹⁸ atoms / cm
Regions 109a to 109f to which a p-type impurity element (boron in this embodiment) is added at a concentration of ³ (typically 5 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm ³ ) are formed. Note that, in this specification, an impurity region containing a p-type impurity element in at least the above-described concentration range (however, an impurity element imparting n-type at a concentration of 1 × 10 ¹⁶ atoms / cm ³ , typically phosphorus or arsenic) is used. The region excluding the added region) is defined as a p-type impurity region (b). (Fig. 1 (D))

In this step, the p-channel type TF
Boron is also added to a region to be a T channel formation region (region indicated by 109a). However, if not necessary, the above process may be performed by concealing with a resist or the like. Alternatively, after adding boron to the entire surface, an element belonging to Group 15 (typically, phosphorus or arsenic) may be added only to the region indicated by 109a to further adjust the threshold voltage.

Next, resists 110a to 110f are formed by a backside exposure method using the light shielding films 102a to 102f.
At this time, the light enters the inside of the light shielding film so that the resist 110 has a reduced pattern inside the light shielding film.
a to 110f are formed. In this embodiment, the protective film 108
Is adjusted to 0.3 μm, and the amount of light wraparound is adjusted to 0.3 μm. That is, a resist having a pattern in which each light-shielding film is reduced by 0.3 μm inward is formed on each light-shielding film. (FIG. 1 (E))

Next, the protective film 108 is patterned using the resists 110a to 110f as a mask to form patterned protective films 111a to 111f. Then, an n-type impurity element is added as it is by the ion doping method to form n-type impurity regions 112a to 112k.
At this time, an impurity element may be added after removing the resists 110a to 110f. (Fig. 2 (A))

The low-concentration impurity regions 112a to 112k
Is an impurity which will later become an LDD region of an n-channel TFT.
In the region or the region that becomes part of the lower electrode of the storage capacitor
is there. The impurity region formed here has n-type impurities.
2 × 10¹⁶~ 5 × 10 ¹⁹atoms / cm^Three(Typically
Is 5 × 10¹⁷~ 5 × 10¹⁸atoms / cm^Three) Concentration
ing. In this specification, the n-type impurity element
Is defined as an n-type impurity region (b).

Next, the polysilicon film is patterned to form island-shaped semiconductor films (hereinafter referred to as active layers) 114 to 118.
To form Here, a second patterning step is performed. Reference numeral 114 denotes an active layer of a p-channel TFT, 11
Reference numerals 5 to 117 denote active layers of the n-channel TFT, and reference numeral 118 denotes a lower electrode of the storage capacitor. (FIG. 2 (B))

Before performing the patterning step of FIG. 2B, it is also effective to make the added n-type impurity element or p-type impurity element by laser annealing, furnace annealing or both. When such an activation step is introduced, the boundary between the n-type impurity regions (b) 112a to 112k, that is, the intrinsic region (p-type impurity region (b)) existing around the n-type impurity region (b) is also reduced. (Considered substantially intrinsic). This was later explained by TFT
Means that the LDD region and the channel forming region can form a very good junction.

Next, as shown in FIG.
A gate insulating film 119 is formed to cover 14 to 118.
The gate insulating film 119 may be formed to a thickness of 10 to 200 nm, preferably 50 to 150 nm. In this embodiment, a silicon nitride oxide film is formed to a thickness of 80 nm by plasma CVD using N ₂ O and SiH ₄ as raw materials.

Next, a conductive film (not shown) serving as a gate wiring (including a gate electrode) is formed. This conductive film is formed of a material that transmits light for exposure emitted from an exposure device. Specifically, from 0.71 nm (X-ray) to 43
It is desirable to transmit any one of the lights included in the wavelength range up to 6 nm (g-line).

In this embodiment, since a silicon film to which an n-type impurity element is added is used as the conductive film, the wavelength is 350 nm.
The above light, typically i-line (365 nm) and g-line (43
6 nm) or h-line (405 nm) enables backside exposure. Further, as a conductive film, an ITO (indium tin oxide) film, a tin oxide film, an ITO film to which zinc is added,
Alternatively, when using a tin oxide film to which zinc is added, a wavelength of 40
By using light of 0 nm or more (g-line or h-line), backside exposure becomes possible.

When an ITO film, a tin oxide film, an ITO film containing zinc, or a tin oxide film containing zinc is used, the resistivity can be reduced by adding fluorine during film formation.

Next, the conductive film is patterned by a backside exposure method to form a conductive film pattern 12 having a thickness of 400 nm.
0, a gate wiring 120 to 124 and a capacitance wiring 125 serving as an upper electrode of the storage capacitor are formed. At this time, the gate wirings 121 to 124 are n-type impurity regions (b) 112b to 112b.
2i is formed so as to overlap with part of the gate insulating film. This structure may be adjusted by exposure conditions, or may be adjusted by the thickness of the gate insulating film 119 or a conductive film serving as a gate wiring. (Fig. 2 (C))

Next, resists 126a and 126b are formed. Here, a third patterning step is performed. Next, the conductive film pattern 120 is etched using the resists 126a and 126b as a mask to form a gate wiring 127 of a p-channel TFT.

Further, the p-type impurity element (the actual
In this example, boron is added, and impurities containing boron in high concentration
Object regions 128a and 128b are formed. Here is diborane
(B _TwoH₆3) by ion doping method using
²⁰~ 3 × 10^{twenty one}atoms / cm^Three(Typically 5 × 10²⁰~ 1
× 10^{twenty one}atoms / cm^Three) Add boron in concentration. In addition,
In the present specification, the concentration of p-type impurity element
The pure region is defined as a p-type impurity region (a). (Figure 2
(D))

It should be noted that phosphorus is already added to a part of the impurity region 128b (the above-described n-type impurity region (b) 112a). Is done. Therefore, the n-type impurity region formed in advance is completely inverted to P-type and functions as a P-type impurity region.

Next, after removing the resist masks 126a and 126b, a first interlayer insulating film 129 is formed. The first interlayer insulating film 129 may be formed using an insulating film containing silicon, specifically, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film including a combination thereof. The thickness is 50 to 400 nm (preferably 100 to 400 nm).
２００200 nm).

In this embodiment, SiH is formed by plasma CVD.
₄ , 200 nm thick silicon oxynitride film using N ₂ O and NH ₃ as source gas (however, nitrogen concentration is 25-50 atomic%)
Is used. The first interlayer insulating film 129 has an effect of preventing the gate wirings 121 to 124, 127 and the capacitance wiring 125 made of a silicon film from being oxidized in a heat treatment step (activation step) performed next.

Thereafter, a heat treatment step (activation step) is performed to activate the n-type or p-type impurity element added at each concentration. This step can be performed by a furnace annealing method, a laser annealing method, or a rapid thermal annealing method (RTA method). Here, the activation step is performed by furnace annealing. In this heat treatment step, heat treatment is performed at 300 to 650 ° C., preferably 400 to 550 ° C., here 550 ° C., for 4 hours in a nitrogen atmosphere.

At this time, the catalytic element (nickel in the present embodiment) used for crystallization of the amorphous silicon film in the present embodiment moves and is captured (gettered) in a region containing phosphorus. This is a phenomenon caused by the gettering effect of the metal element by phosphorus. As a result, in all the TFTs, the channel forming region has a concentration of the catalyst element of 1 ×.
It is 10 ¹⁷ atoms / cm ³ or less. However, in the case of nickel,
Since 1 × 10 ¹⁷ atoms / cm ³ or less is the lower limit of SIMS measurement, it cannot be measured with the current technology.

On the other hand, in the region where the catalyst element is gettered, the concentration of the catalyst element is increased to 5 × 10 ¹⁸ atoms / cm
³ or more (typically 1 × 10 ^{19 to} 5 × 10 ²⁰ atoms / cm ³ )
Will be present in concentration. However, since the region serving as the gettering site only has to function as a source region or a drain region, the presence or absence of nickel is not considered to be a problem.

Next, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen,
A step of hydrogenating the active layer is performed. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

After the activation step, the first interlayer insulating film 1
A second interlayer insulating film 130 having a thickness of 500 nm to 2.0 μm is formed on the second interlayer insulating film 29. In this embodiment, the second interlayer insulating film 130
An insulating film made of a resin material (also referred to as an organic material) (hereinafter, referred to as a resin insulating film) is used. As the resin material, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used.

The advantages of using a resin insulating film are that the film forming method (typically, spin coating method) is simple, the relative dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. Points are raised. Note that a resin insulating film or an organic SiO compound other than those described above can also be used. Alternatively, the second interlayer insulating film 130 may have a laminated structure, and some layers may be colored with a pigment or the like and used as a color filter.

Next, a transparent conductive film (ITO film in this embodiment) is formed on the second interlayer insulating film 130, and a fourth patterning step is performed to form a pixel electrode 131. The thickness is 110 nm, but the thickness can be reduced by adding fluorine.

Thereafter, a contact hole reaching the source region or the drain region of each TFT is formed. Here, a fifth patterning step is performed. Then, the source wirings 132 to 135 and the drain wiring 136
To 138. Here, a sixth patterning step is performed. In the present embodiment, these wirings are connected to a Ti film by one.
00 nm, aluminum film containing Ti 300 nm, Ti
A film with a thickness of 150 nm is formed as a laminated film having a three-layer structure formed continuously by a sputtering method. Of course, it is not necessary to limit to this structure.

Although not shown in this embodiment, after that, an insulating film made of a resin material is provided on the source wiring and the drain wiring, and flattened by etching (called an etch-back step or the like). It is also effective to reduce a step at the pattern edge of the drain wiring and a step caused by the contact hole.

Thus, a substrate having a drive circuit and a pixel portion on the same substrate (hereinafter referred to as an active matrix substrate) is completed. The number of times of patterning required to complete so far is six, which can be said to be a very small number of methods for manufacturing an active matrix substrate having a top gate structure using a poly-Si TFT.

Further, as shown in FIG. 3, when the active matrix substrate is completed, an alignment film 139 is formed on the pixel electrode 131, and a rubbing process is performed. Although not shown, it is also possible to form the alignment film 139 after forming a spacer made of a resin material at a predetermined position in the pixel portion.

Next, the light shielding film 141 is formed on the light transmitting substrate 140.
a, a color filter 142, a flattening film (overcoat agent) 143, a counter electrode 144 made of a transparent conductive film, and an alignment film 145 are formed, and a rubbing process is performed to manufacture a counter substrate.

After a sealant (not shown) is formed on the active matrix substrate, the active matrix substrate and the opposing substrate are attached to each other, and the liquid crystal 146 is sealed in a region surrounded by the sealant. Thus, a liquid crystal display having a structure as shown in FIG. 3 is completed.

In FIG. 3, the driving circuit includes a p-channel TFT 301, an n-channel TFT 302,
03 are formed, and a pixel portion is formed with a pixel TFT 304 formed of an n-channel TFT and a storage capacitor 305.

The p-channel TFT 301 forming the CMOS circuit of the drive circuit has a channel formation region 201 and
A source region 202 and a drain region 203 made of a p-type impurity region (a) are formed. All of these impurity regions are formed in a self-aligned manner.

The n-channel type TFT 302 forming the CMOS circuit of the drive circuit has a channel formation region 20
4. LDD regions 207 and 208 partially overlapping the gate wiring are formed with the source region 205, the drain region 206, and the channel formation region interposed therebetween. At this time, LD
The D regions 207 and 208 are 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms /
It is formed so as to contain phosphorus at a concentration of cm ³ and partially overlap the gate wiring. All of these impurity regions are formed in a self-aligned manner.

Since a part of the LDD region overlaps with the gate wiring, the LDD region has a region overlapping with the gate wiring and a region not overlapping with the gate wiring. The LDD region overlapping with the gate wiring can reduce deterioration due to hot carrier injection. Although this is generally known, it has a disadvantage that an off current (a drain current that flows when the TFT is in an off operation) increases. However, when an LDD region that does not overlap with the gate wiring is provided adjacent to the LDD region that overlaps with the gate wiring as in this embodiment, an increase in off-state current can be effectively suppressed.

In the n-channel TFT 303 forming the sampling circuit, a channel forming region 209, a source region 210, a drain region 211, and LDD regions 212 and 213 are formed on both sides of the channel forming region. Also in this structure, parts of the LDD regions 212 and 213 are arranged so as to overlap the gate wiring. The effect is the same as that of the n-channel TFT 302. All of these impurity regions are formed in a self-aligned manner.

The pixel TFT 30 arranged in the pixel portion
4 includes channel forming regions 214 and 215, a source region 216, a drain region 217, and LDD regions 218 to 22.
1. An n-type impurity region (a) 222 in contact with the LDD regions 219 and 220 is formed. At this time, the source region 21
6, the drain region 217 is formed of an n-type impurity region (a), and the LDD regions 218 to 221 are formed of an n-type impurity region (b). Also, the LDD region 218
221 partially overlap the gate wiring. The effect is the same as that of the n-channel TFT 302. Also,
All of these impurity regions are formed in a self-aligned manner.

The drain region 217 is extended and connected to the semiconductor region 223. Then, the capacitor wiring 125 overlaps with the gate insulating film 119 interposed therebetween. At this time, a storage capacitor 305 including the semiconductor region 223, the gate insulating film 119, and the capacitor wiring 125 is formed.

Further, n-channel type TFTs 302 and 303
And 304 LDD regions 207, 208, 212, 12
3 and 218 to 221, the length (width) of the region overlapping the gate wiring is 0.3 to 1.0 μm, and the length (width) of the region not overlapping the gate wiring is 0.5 to 1.5 μm. Just do it.

[Embodiment 2] In this embodiment, the appearance of the liquid crystal display device manufactured in Embodiment 1 will be described. 4 is used for the description. The active matrix substrate includes a pixel portion 402, a gate signal side driver circuit 403, and a source signal side driver circuit 404 formed over a substrate 401. The pixel electrode 40 is provided in the pixel TFT 405 in the pixel portion.
6 and the storage capacitor 407 are connected. The storage capacitor 305 described in Embodiment 1 is used for the storage capacitor 407.

The peripheral driving circuit is a CMO
It is configured based on an S circuit. The gate signal side driver circuit 403 and the source signal side driver circuit 404 are connected to the pixel portion 402 through a gate wiring 408 and a source wiring 409, respectively. Also, input / output wirings (connection wirings) 411 for transmitting signals to the driving circuit are provided on the FPC 410,
412 are provided. 413 is a counter substrate.

Although the electro-optical device shown in FIG. 4 is referred to as a liquid crystal display device in this specification, a state in which the electro-optical device is mounted up to the FPC as shown in FIG. 4 is generally called a liquid crystal module. Therefore, the liquid crystal display device in this embodiment may be called a liquid crystal module.

[Embodiment 3] In this embodiment, a case where a liquid crystal display device is manufactured by a manufacturing process different from that in Embodiment 1 will be described. FIG. 5 is used for the description.

First, the steps up to the step of FIG. However, in this embodiment, 1 is used as the protective film 108.
A 50 nm silicon oxide film 501a and a 1 μm thick polyimide film 501b are formed. Then, FIG.
As in (E), resists 110a to 110f are formed.
(FIG. 5 (A))

What is important here is that the protective film 108 has a laminated structure, and a layer above it can be selectively removed while leaving some layers. Therefore, if a silicon oxide film is used as the film indicated by 501a, a resin material other than the polyimide film can be used as the film indicated by 501b. Further, if a silicon nitride film is used as the film indicated by 501a, a silicon oxide film can be used as the film indicated by 501b. Of course, the structure of the present embodiment may be configured by using the same material and using the difference between the two etching rates.

Next, the polyimide film 501b is etched using the resists 110a to 110f as masks to form polyimide patterns 502a to 502f. At this time, the polyimide film 501b is etched by a dry etching method using oxygen gas, but the underlying silicon oxide film 501a remains without being etched.

Then, an n-type impurity element is added in this state. The addition conditions are the same as those in the step of FIG. 2A of the first embodiment to form n-type impurity regions (b) 112a to 112k. (FIG. 5 (B))

In the case of the present embodiment, the step of adding the n-type impurity element is performed while the protective film remains on the polysilicon film, so that the concentration of the impurity element can be easily controlled.

Thereafter, the polyimide patterns 502a to 502a-5
The active layer 114 to 118 is formed by patterning the polysilicon film by removing the 02f and the silicon oxide film 501a. (FIG. 5 (C))

The subsequent steps are the same as those shown in FIG.
The following steps may be followed. The configuration of this embodiment is the same as that of the first embodiment.
It is needless to say that a part of the process is improved in the method described above, and may be carried out when manufacturing the liquid crystal display device of Example 2.

[Embodiment 4] In this embodiment, a case where a liquid crystal display device is manufactured by a manufacturing process different from that in Embodiment 1 will be described. FIG. 6 is used for the description.

The present embodiment is characterized in that a step shown in FIG. 6 is added after the step shown in FIG. That is, after the step shown in FIG.
a, 126b are removed, and resists 601a, 601b are newly formed.
To form

Then, in this state, FIG.
An n-type impurity element adding step is performed under the same conditions as the step shown in FIG. At this time, the n-type impurity element is
Using n as a mask, n-type impurity regions (a) 602 and 603 are formed in a self-aligned manner. At the same time, n-type impurity regions (b) 604 and 605 are defined.

At this time, n-type impurity region (b) 604,
Reference numeral 605 denotes an LDD region completely overlapping the gate wiring 121. That is, in the active matrix substrate shown in FIG.
The n-type impurity regions (b) 604 and 605 of this embodiment are formed.

The LDD region completely overlapped with the gate wiring is suitable for a TFT which requires a high-speed operation because carriers move faster due to a small resistance component. Therefore, it is suitable for a TFT forming a circuit such as a shift register which needs to operate at several MHz to several tens of MHz.

The steps after FIG. 6 are performed in the same manner as in FIG.
(E) The subsequent steps may be followed. The configuration of the present embodiment is obtained by improving some of the steps in the first embodiment, and it goes without saying that it may be implemented when the liquid crystal display device of the second embodiment is manufactured. Also, the combination with the third embodiment is easy.

[Embodiment 5] In this embodiment, a case where a liquid crystal display device is manufactured by a manufacturing process different from that of Embodiment 1 will be described. FIG. 7 is used for the description. The reference numerals used in the first embodiment will be referred to as needed.

First, the process up to the step of FIG. Note that a gate wiring provided in the pixel portion (hereinafter, referred to as a first gate wiring) has a width of 7 in FIG.
As shown by 01 and 702, the feature is that it is formed as an independent pattern for each pixel. That is, the first gate wiring is formed in each pixel, but is electrically isolated between the pixels.

After the step shown in FIG. 2D, the resists 126a and 126b are removed next, and 450-550 in that state.
The activation step is performed at a temperature of ° C. In the case of the first embodiment, since a silicon film is used as the material of the first gate wiring, an oxide or a nitride is formed on the surface.

Next, the oxide or nitride is removed with a hydrofluoric acid-based etching solution. Note that in this case, the gate insulating film is also etched, but this is not a problem as the oxide or nitride is thinner.

After the oxides or nitrides formed on the surfaces of the first gate wirings 701 and 702 are removed, an alloy film containing aluminum or copper as a main component or a laminated film of these and other metal films is formed. I do. Any material may be used as long as it is a conductive film, but a conductive film having as low a resistivity as possible is preferable.

Then, the conductive film is patterned to form a second gate wiring 703. This second gate wiring 7
03 is used as a bus line for connecting in series a first gate wiring which is provided electrically isolated for each pixel.

FIG. 7B shows this state. FIG. 7 (B)
FIG. 7A is a cross-sectional view of the top view of FIG. As described above, the first gate lines 701 and 702
The first gate lines are electrically connected to each other by a second gate line 703 provided in contact with the first gate line.

It is also possible to use a known transparent conductive film typified by an ITO film as the first gate wiring.
In this case, if only an ohmic contact with the second gate wiring can be ensured, the surface treatment of the first gate wiring can be omitted.

After the second gate wiring 703 is formed, a first interlayer insulating film 129 is formed, and a hydrogenation process is performed according to the first embodiment. Of course, hydrogenation may be performed before forming the first interlayer insulating film 129. Subsequent steps may be in accordance with the first embodiment. Further, the configuration of the present embodiment is obtained by improving some of the steps in the first embodiment, and may be implemented in manufacturing the liquid crystal display device of the second embodiment.

This embodiment is characterized in that a conductive film, such as a silicon film or an ITO film, having a higher resistivity than other metal films is used for the TFT.
And a relatively low resistivity metal film such as an alloy film containing aluminum as a main component is used as a bus line for electrically connecting the gate wiring.

In the present invention, it is necessary to use a material capable of transmitting light of about 350 to 450 nm as an electrode (or wiring) functioning as a gate of a TFT, and thus it is difficult to use a metal material having a low resistivity. . In that case, T
Only the gate portion of the FT is made of such a material,
The gates may be connected later with a low-resistance material.

The structure of the present embodiment is obtained by improving some of the steps in the first embodiment, and it goes without saying that the structure of the present embodiment may be applied to manufacture the liquid crystal display device of the second embodiment. Further, the combination with the third embodiment or the fourth embodiment is easy.

[Embodiment 6] In this embodiment, a case where a liquid crystal display device is manufactured by a manufacturing process different from that in Embodiment 1 will be described. FIG. 8 is used for the description. The reference numerals used in the first embodiment will be referred to as needed.

First, according to the steps of the first embodiment, FIG.
The process up to the step (E) is completed. At this time, the protective film 10
Resists 801a to 801f are formed on the upper surface 8 by backside exposure. (FIG. 8A)

Next, the protective film 108 is etched using the resists 801a to 801f as a mask to form patterned protective films 802a to 802f. (FIG. 8 (B))

Next, using the resists 801a to 801f as a mask, the patterned protective films 802a to 802f are isotropically etched. In this step, the protective film 802a
To 802f are etched from the lateral direction, and the resist 80
Patterned protective films 803a to 803f having a reduced width are formed inside 1a to 801f. (FIG. 8
(C))

Subsequent steps may be performed in accordance with the steps of FIG. 2A of the first embodiment, and finally, an active matrix substrate as shown in FIG. 3 and a liquid crystal display as shown in FIG. The device is completed.

In the first embodiment, the width (length) of the n-type impurity regions (b) 112a to 112k is determined by the amount of wraparound light for backside exposure, whereas in the present embodiment, the protective film 802a is formed.
It is characterized in that the width (length) of the n-type impurity regions (b) 112a to 112k is determined by the etching amount from the lateral direction to 802f.

The structure of the present embodiment is obtained by improving some of the steps in the first embodiment, and it goes without saying that the structure of the present embodiment may be applied to manufacture the liquid crystal display device of the second embodiment. Further, the combination with any of the configurations of the third to fifth embodiments is easy.

[Embodiment 7] This embodiment is different from the embodiment 1 shown in FIG.
This is an embodiment in which the structure of the pixel portion is improved in the active matrix substrate shown in FIG. Since the pixel structure is almost the same as that of the first embodiment, only the changed points will be described with reference numerals.

In this embodiment, as shown in FIG. 9, after forming a source wiring 901 and a drain wiring 902, a pixel electrode 903 made of a transparent conductive film is formed.

The structure of the present embodiment is obtained by improving some of the steps in the first embodiment, and it goes without saying that the present embodiment may be implemented in manufacturing the liquid crystal display device of the second embodiment. Further, the combination with any of the configurations of the third to sixth embodiments is easy.

[Embodiment 8] This embodiment is different from the embodiment 1 shown in FIG.
This is an embodiment in which the structure of the pixel portion is improved in the active matrix substrate shown in FIG. Since the pixel structure is almost the same as that of the first embodiment, only the changed points will be described with reference numerals.

In this embodiment, as shown in FIG.
In forming the source wiring 135 in the step (E), the drain wiring 138 is not formed and the contact hole is left open. After that, a pixel electrode 1001 made of a transparent conductive film is formed so as to be connected to the drain region 217.

The structure of the present embodiment is obtained by improving some of the steps in Embodiment 1, and it goes without saying that the present embodiment may be carried out when manufacturing the liquid crystal display device of Embodiment 2. Further, the combination with any of the configurations of the third to sixth embodiments is easy.

[Embodiment 9] In this embodiment, a case where a reflection type liquid crystal display device is manufactured by implementing the present invention will be described. In the case of this embodiment, the drain wiring denoted by reference numeral 138 in FIG. 2E may be formed widely in the pixel and used as a reflective electrode (functioning as a pixel electrode). However, since the pixel electrode is formed in the same layer as the source wiring,
Short circuit (short circuit) between source line and pixel electrode
Need attention.

More specifically, as shown in FIG.
The source wiring 1101 and the drain wiring 1102 are formed in the same layer, so that the drain wiring 1102 also functions as a pixel electrode. FIG. 11 shows an example in which the configuration of the fifth embodiment is combined with that of the fifth embodiment. Reference numeral 1103 denotes a second gate wiring formed of a low-resistance material used as a bus line of the first gate wiring. (Corresponding to two gate wirings 703).

FIG. 11B is a sectional view taken along the line AA ′ of FIG. As shown in FIG. 11B, a drain wiring (pixel electrode) 1102 is a source wiring 1101
And a pixel surrounded by a gate wiring (corresponding to the second gate wiring 1103 in this case), and formed so as to occupy most of the area occupied by the pixel. It is necessary to design with a margin so as not to contact the source wiring 1101, but 70 to 95% of the area occupied by the pixel
The drain wiring 1102 occupies (typically 80 to 90%). Therefore, the area in which an image can be displayed is greatly increased as compared with the transmissive liquid crystal display device.

Further, according to the present embodiment, since the film forming step and the patterning step of the pixel electrode 131 in the first embodiment can be omitted, the number of steps is greatly simplified, and
The number of masks required for patterning is reduced to five.

The appearance of the liquid crystal module as a reflection type liquid crystal display device is not different from the structure shown in FIG. Further, the present embodiment may be implemented by combining the configurations of Embodiments 3 to 8.

Example 10 In the manufacturing process of Example 1,
As an example of a method for forming a semiconductor film including a crystal structure, a catalyst element that promotes crystallization is used.
A case where a semiconductor film having a crystal structure is formed by thermal crystallization or laser crystallization without using such a catalyst element will be described.

In the case of thermal crystallization, after a semiconductor film having an amorphous structure is formed, a temperature of 600 to 650 ° C.
A heat treatment step of 24 hours may be performed. That is, by performing heat treatment at a temperature exceeding 600 ° C., a natural nucleus is generated,
Crystallization proceeds.

In the case of laser crystallization, after forming a semiconductor film having an amorphous structure, a laser annealing step may be performed under the first annealing conditions shown in the first embodiment.
Thus, a semiconductor film including a crystal structure can be formed in a short time. Of course, lamp annealing may be performed instead of laser annealing.

The technique described in Example 1 of the specification of Japanese Patent Application No. 11-79667 may be used. According to the manufacturing process of Example 1 of the specification of the application, a polysilicon film having a unique crystal structure can be obtained. The details of this polysilicon film are described in Japanese Patent Application No.
No. 044659, Japanese Patent Application No. 10-152316, Japanese Patent Application No. 10-152308 or Japanese Patent Application No. 10-15230.
Reference may be made to the application No. 5.

As described above, a semiconductor film including a crystal structure used for a TFT can be formed by any known means. Note that this embodiment can be freely combined with any of the configurations of Embodiments 1 to 9.

[Embodiment 11] The configurations shown in Embodiments 1 to 10 can be applied to the case of manufacturing an active matrix type EL (electroluminescence) display device.

In a normal EL display device, two TFTs, a switching TFT and a current control TFT, are formed in a pixel. The n-channel TFT 304 shown in FIG. 3 is suitable for the switching TFT. n-channel type TFT
Reference numeral 302 is suitable for a current controlling TFT.

Therefore, an active matrix substrate for an EL display device was manufactured with reference to the structures of the first to tenth embodiments.
An active matrix EL display device may be completed using a known EL forming technique.

[Embodiment 12] An inexpensive electro-optical device obtained by implementing the present invention can be incorporated as a component into all electronic devices (electronic products) such as personal computers and the like, which incorporate a display.

Such electronic devices include a video camera, digital still camera, projector (rear or front type), goggle type display (head mounted display), car navigation, personal computer, and portable information terminal (mobile computer, portable An image reproducing apparatus provided with a recording medium (specifically, a compact disk (CD),
A device that reproduces a recording medium such as a laser disk (LD) or a digital video disk (DVD) and displays an image of the recording medium). FIG. 8 shows examples of these semiconductor devices.

FIG. 8A shows a personal computer, which includes a main body 2001, an image receiving section 2002, and a display device 200.
3, and a keyboard 2004 and the like. The present invention can be used for the display device 2004.

FIG. 8B shows a video camera,
101, display device 2102, audio input unit 2103, operation switch 2104, battery 2105, image receiving unit 210
6 and so on. The invention of the present application can be used for the display device 2102.

FIG. 8C shows a goggle type display, which comprises a main body 2201, a display device 2202, and an arm 220.
3 and so on. The present invention can be used for the display device 2202. However, actually, the display device 2202 is incorporated in an optical system so as not to block the field of view.

FIG. 8D shows an image reproducing apparatus (specifically, a DVD reproducing apparatus) provided with a recording medium.
1, a recording medium (CD, LD, DVD, etc.) 2302,
It comprises an operation switch 2303, a display device (a) 2304, a display device (b) 2305, and the like. The display device (a) mainly displays image information, and the display device (b) mainly displays character information. The present invention can be used for these display devices (a) and (b). Note that the present invention can be applied to a CD playback device, a game machine, and the like as an image playback device provided with a recording medium.

FIG. 8E shows a front type projector, which is composed of a main body 2401, an optical engine 2402 including a light source, an optical lens and a display device, and can display an image on a screen 2403. The present invention can be used for a display device (not shown) incorporated in the optical engine 2402. Note that the display device may be a system using three devices or a system using one device, and may be a transmissive display device or a reflective display device.

FIG. 8F shows a rear type projector, which comprises a main body 2501, an optical engine 2402 including a light source, an optical lens and a display device, a light source 2502, reflectors 2503 and 2504, a screen 2505, and the like. The present invention can be used for a display device (not shown) incorporated in the optical engine 2502. Note that the display device may be a system using three devices or a system using one device, and may be a transmissive display device or a reflective display device.

The electro-optical device according to this embodiment may be manufactured using any combination of the first to twelfth embodiments.

[0132]

According to the present invention, the manufacturing process of an electro-optical device such as a liquid crystal display device or an EL display device has a high yield, and the manufacturing cost can be reduced. Further, a highly reliable electro-optical device can be manufactured at such a low manufacturing cost.

Further, by mounting the inexpensive electro-optical device obtained by implementing the present invention, the manufacturing cost of the electronic device can be reduced. As described above, the present invention is an industrially very useful technique.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a manufacturing process of a pixel portion and a driver circuit.

FIG. 2 illustrates a manufacturing process of a pixel portion and a driver circuit.

FIG. 3 is a diagram illustrating a manufacturing process of an active matrix substrate.

FIG. 4 is a perspective view of an active matrix liquid crystal display device.

FIG. 5 illustrates a manufacturing process of a pixel portion and a driver circuit.

FIG. 6 illustrates a manufacturing process of a pixel portion and a driver circuit.

FIG. 7 is a diagram illustrating a top structure of a pixel portion.

FIG. 8 illustrates a manufacturing process of a pixel portion and a driver circuit.

FIG. 9 illustrates a cross-sectional structure of a pixel portion.

FIG. 10 illustrates a cross-sectional structure of a pixel portion.

FIG. 11 illustrates a cross-sectional structure and a top structure of a pixel portion.

FIG. 12 illustrates an example of an electronic device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Substrate 102a-102f Light-shielding film 103 Base film 104 Polysilicon film 105 Polysilicon film 106a-106e Resist 107a-107f N-type impurity region (a) 108 Protective film 109a-109f P-type impurity region (b) 110a-110f Resist 111a To 111f patterned protective film 112a to 112k n-type impurity region (b) 115 to 118 active layer 119 gate insulating film 120 conductive film pattern 121 to 124, 127 gate wiring 125 capacity wiring 126a, 126b resist 128a, 128b p-type Impurity region (a) 129 First interlayer insulating film 130 Second interlayer insulating film 131 Pixel electrode 132-135 Source wiring 136-138 Drain wiring 139, 145 Alignment film 140 Substrate 141 Opposing light shielding film 142 Color filter 14 Planarizing film (overcoating agent) 144 counter electrode 146 liquid crystal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 31/02 H01L 31/02 A F term (Reference) 2H092 GA29 HA28 JA24 JA31 JA32 JA46 JB51 JB58 KA04 KA05 KA10 MA04 MA05 MA07 MA09 MA15 MA17 MA27 MA29 MA30 NA27 NA29 PA01 PA06 PA08 5C094 AA25 AA42 AA43 AA44 AA53 BA03 BA29 BA43 CA19 DA09 DA13 DB01 DB04 EA04 EA05 EA10 EB02 ED15 FA01 FA02 FB01 FB02 FB15 A03 A05 A05 AB5A15 AB5A10 A5A AA04 NN47 NN72 PP01 PP02 PP03 PP10 PP34 QQ09 QQ12 QQ19 QQ24 QQ25 QQ28

Claims (6)

[Claims] 1. A method of manufacturing an electro-optical device including at least a pixel portion formed of an n-channel TFT or a p-channel TFT on a same substrate and a driving circuit, wherein a first step of forming a light-shielding film on the substrate A second step of forming an insulating film containing silicon on the light-shielding film, a third step of forming a semiconductor film on the insulating film containing silicon, and back-side exposure using the light-shielding film as a mask Forming a resist on the semiconductor film, using the resist as a mask,
Later, n is added to the semiconductor region included in the n-channel TFT.
A fourth step of adding a type impurity element; a fifth step of forming a protective film on the semiconductor film which has been completed up to the fourth step; and forming a resist by back surface exposure using the light shielding film as a mask. A step of removing the protective film by using as a mask a step of adding an n-type impurity element to a semiconductor region included in the n-channel TFT later using the resist or the protective film formed in the sixth step as a mask A seventh step, an eighth step of removing the protective film remaining in the sixth step, a ninth step of patterning the semiconductor film completed up to the eighth step to form a plurality of active layers, A tenth step of forming a gate insulating film in contact therewith; an eleventh step of forming a conductive film that transmits light of a predetermined wavelength on the gate insulating film; and A twelfth step of forming a resist on the conductive film and etching the conductive film using the resist as a mask to form a gate wiring of the n-channel TFT; Cover and etch the conductive film to form the p-channel type TF.
A thirteenth step of forming a gate wiring of T, and p using the resist formed in the thirteenth step as a mask.
A p-type impurity region by adding a p-type impurity element
A method for manufacturing an electro-optical device, comprising: 2. A method for manufacturing an electro-optical device including at least a pixel portion formed of an n-channel TFT or a p-channel TFT on a same substrate and a driving circuit, wherein a first step of forming a light-shielding film on the substrate A second step of forming an insulating film containing silicon on the light-shielding film, a third step of forming a semiconductor film on the insulating film containing silicon, and back-side exposure using the light-shielding film as a mask Forming a resist on the semiconductor film, using the resist as a mask,
Later, n is added to the semiconductor region included in the n-channel TFT.
A fourth step of adding a type impurity element; a fifth step of forming a protective film on the semiconductor film which has been completed up to the fourth step; and forming a resist by back surface exposure using the light shielding film as a mask. A step of removing the protective film by using as a mask a step of adding an n-type impurity element to a semiconductor region included in the n-channel TFT later using the resist or the protective film formed in the sixth step as a mask A seventh step, an eighth step of removing the protective film remaining in the sixth step, a ninth step of patterning the semiconductor film completed up to the eighth step to form a plurality of active layers, A tenth step of forming a gate insulating film in contact therewith; an eleventh step of forming a conductive film that transmits light of a predetermined wavelength on the gate insulating film; and A twelfth step of forming a resist on the conductive film and etching the conductive film using the resist as a mask to form a gate wiring of the n-channel TFT; Cover and etch the conductive film to form the p-channel type TF.
A thirteenth step of forming a gate wiring of T, and p using the resist formed in the thirteenth step as a mask.
A p-type impurity region by adding a p-type impurity element
A fourth step, a fifteenth step of forming an insulating film made of a resin material above the gate wiring formed in the twelfth and thirteenth steps, and a transparent conductive film on the insulating film made of the resin material A sixteenth step of forming a pixel electrode; and a seventeenth step of forming a contact hole in an insulating film made of the resin material and forming a source wiring and a drain wiring. The method of manufacturing an electro-optical device according to claim 1, wherein the drain wiring formed in the step (c) is formed so as to partially overlap the pixel electrode. 3. A method of manufacturing an electro-optical device including at least a pixel portion formed of an n-channel TFT or a p-channel TFT on a same substrate and a driving circuit, wherein a first step of forming a light-shielding film on the substrate is performed. A second step of forming an insulating film containing silicon on the light-shielding film, a third step of forming a semiconductor film on the insulating film containing silicon, and back-side exposure using the light-shielding film as a mask Forming a resist on the semiconductor film, using the resist as a mask,
Later, n is added to the semiconductor region included in the n-channel TFT.
A fourth step of adding a type impurity element; a fifth step of forming a protective film on the semiconductor film which has been completed up to the fourth step; and forming a resist by back surface exposure using the light shielding film as a mask. A step of removing the protective film by using as a mask a step of adding an n-type impurity element to a semiconductor region included in the n-channel TFT later using the resist or the protective film formed in the sixth step as a mask A seventh step, an eighth step of removing the protective film remaining in the sixth step, a ninth step of patterning the semiconductor film completed up to the eighth step to form a plurality of active layers, A tenth step of forming a gate insulating film in contact therewith; an eleventh step of forming a conductive film that transmits light of a predetermined wavelength on the gate insulating film; and A twelfth step of forming a resist on the conductive film and etching the conductive film using the resist as a mask to form a gate wiring of the n-channel TFT; Cover and etch the conductive film to form the p-channel type TF.
A thirteenth step of forming a gate wiring of T, and p using the resist formed in the thirteenth step as a mask.
A p-type impurity region by adding a p-type impurity element
A fourth step, a fifteenth step of forming an insulating film made of a resin material above the gate wiring formed in the twelfth and thirteenth steps, and forming a contact hole in the insulating film made of the resin material; 16. A manufacturing method of an electro-optical device, comprising: a sixteenth step of forming a wiring and a drain wiring; and a seventeenth step of forming a pixel electrode made of a transparent conductive film so as to partially overlap the drain wiring. Method. 4. A method for manufacturing an electro-optical device including at least a pixel portion formed of an n-channel TFT or a p-channel TFT on a same substrate and a driving circuit, wherein a first step of forming a light-shielding film on the substrate A second step of forming an insulating film containing silicon on the light-shielding film, a third step of forming a semiconductor film on the insulating film containing silicon, and back-side exposure using the light-shielding film as a mask Forming a resist on the semiconductor film, using the resist as a mask,
Later, n is added to the semiconductor region included in the n-channel TFT.
A fourth step of adding a type impurity element; a fifth step of forming a protective film on the semiconductor film which has been completed up to the fourth step; and forming a resist by back surface exposure using the light shielding film as a mask. A step of removing the protective film by using as a mask a step of adding an n-type impurity element to a semiconductor region included in the n-channel TFT later using the resist or the protective film formed in the sixth step as a mask A seventh step, an eighth step of removing the protective film remaining in the sixth step, a ninth step of patterning the semiconductor film completed up to the eighth step to form a plurality of active layers, A tenth step of forming a gate insulating film in contact therewith; an eleventh step of forming a conductive film that transmits light of a predetermined wavelength on the gate insulating film; and A twelfth step of forming a resist on the conductive film and etching the conductive film using the resist as a mask to form a gate wiring of the n-channel TFT; Cover and etch the conductive film to form the p-channel type TF.
A thirteenth step of forming a gate wiring of T, and p using the resist formed in the thirteenth step as a mask.
A p-type impurity region by adding a p-type impurity element
A fourth step, a fifteenth step of forming an insulating film made of a resin material above the gate wiring formed in the twelfth and thirteenth steps, and forming a contact hole in the insulating film made of the resin material; And a seventeenth step of forming a wiring and a drain wiring. The drain wiring provided in the pixel portion is formed in a pixel surrounded by the source wiring and the gate wiring, and is exclusively used by the pixel. A method for manufacturing an electro-optical device, which is formed so as to occupy 70 to 95% of the area. 5. The method according to claim 1, wherein
The method for manufacturing an electro-optical device, wherein the protective film formed in the step is a stacked film including an insulating film containing silicon and an insulating film made of a resin material. 6. The method for manufacturing an electro-optical device according to claim 1, wherein the predetermined wavelength in the eleventh step is a wavelength of light used for backside exposure in the twelfth step. .