JP2001028533A - Power supply boosting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To boost to an operating limit by realizing low voltage of a low- voltage power supply, without using a level shifter while the potential of a high-voltage power supply is lower than the potential of the low voltage power supply nor depending on the driving limit of the level shifter, in the case of boosting the high voltage power supply by using a power supply boosting circuit of high power. SOLUTION: When a comparator 7 detects that the potential of a high voltage power supply (VLCD) 11 has reached the potential of a low-voltage power supply (VDD) 10, a switching device 8 supplies a clock signal 5 for boosting to a level shifter 3, and in the shifter 3, a clock signal 6 for boosting undergoing level shifting to a high voltage potential is made to be inputted to a charge pump 4. Therefore, it is possible to realize the low voltage of the VDD 10, without depending on the driving limit of the shifter 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply boosting circuit, and more particularly to a power supply boosting circuit for boosting a high voltage power supply using a low voltage power supply by a level shifter.

[0002]

2. Description of the Related Art A power supply boosting circuit is mainly composed of an LCD C / D.
(Liquid crystal control driver) and used for internal supply of high voltage power. The high-voltage power supply referred to here is a high-voltage power supply (VLCD) used for liquid crystal display. While a low-voltage power supply (VDD), which is externally supplied, is generally used at about 3 to 5 V, The power supply supplies a potential of about 8 to 15V. LCD ・
C / D is generally used for mobile devices such as mobile phones and PHSs. In recent years, in addition to higher functions and higher quality of display, power consumption has been reduced more than before. .

Accordingly, the external power supply VDD has been reduced in voltage, and the voltage difference from the display power supply voltage VLCD has been increasing. For this reason, a high-power-supply voltage boosting circuit is required, and a shift ratio of the level shifter between VDD and VLCD is required to be high, and an extreme difference is provided in the drive balance of the transistors of the level shifter.

[0004]

The above-mentioned conventional power supply boosting circuit has the following problems. FIG.
A configuration example of the level shifter is shown by a circuit diagram. The signal input to the charge pump is always the level shifter 10
3 is the only output 106. The level shifter 103 needs to set the high-speed clock (boost clock signal) 105 to a low power supply potential and shift the level to the number of VDD.

[0005] In the circuit shown in FIG.
For the gm of −tr112, the input stage Nch−t
The gm of r113 is necessarily required to be large. Therefore, when the potential of VDD is reduced, the operation limit of the level shifter is worse than other circuits, and the boosting operation cannot be performed due to the limitation by the operation limit of the level shifter 103. As a result,
The charge pump does not operate, and no boosting is performed. As described above, when the power supply voltage on the low voltage side is reduced, there is a problem that the boosting becomes impossible due to the operation limit of the level shifter 103.

Further, a conventional configuration will be described in detail with reference to FIG. When VDD110 rises, VDD1
The voltage lower than VDD 110 by Vf is set to V by the diode 101 connected in the forward direction from VLCD 111 to VLCD 111.
It is applied to the LCD 111 as an initial voltage. Then, the boosting clock signal 105 generated by the low voltage circuit 102 is
The level is shifted through the level shifter 103 and input to the charge pump 104 to perform the boosting operation.

The operation of FIG. 5 will be described in detail with reference to FIGS. 6 and 7. When the VDD 110 rises, a voltage lower than the VDD 110 by Vf is applied to the VLCD 111 as an initial voltage by the diode 101 connected in a forward direction from the VDD 110 to the VLCD 111 (period t0 to t1). Then, the level shifter 103
Starts operation at the moment (t1) when the voltage exceeds the operation limit voltage (v1), shifts the level of the boosting clock signal 105 generated by the low voltage circuit 102 to the charge pump 104, and the VLCD 111 starts boosting. (After t1).

Here, when the voltage of the VDD 110 is reduced, v
2, the VLCD 111 has a diode 10
Since a voltage lower by vf is applied via the VLC 1, the VLCD 111 is lower than the operation limit voltage v 1 of the level shifter 103. In other words, the operation limit of the level shifter 103 operated by the VLCD 111 has a problem that the operation limit voltage becomes higher than that of the other circuits by vf of the diode 101 until the VLCD 111 is boosted.

The present invention has been made in view of the above problems, and uses a level shifter while boosting a high-voltage power supply using a high-power power supply boosting circuit while the potential of the high-voltage power supply is lower than the potential of the low-voltage power supply. It is an object of the present invention to provide a power supply boosting circuit capable of boosting a voltage to an operation limit by realizing a low-voltage power supply without depending on a driving limit of a level shifter.

[0010]

In order to achieve the above object, the invention according to claim 1 is interposed between a low-voltage power supply and a high-voltage power supply, and the high-voltage power supply can be boosted by using the low-voltage power supply. The configuration includes a level shifter and a boosting control circuit that boosts the high-voltage power supply using the level shifter when the potential of the high-voltage power supply reaches the potential of the low-voltage power supply when boosting the high-voltage power supply.

That is, when boosting the high-voltage power supply, the boost control circuit switches the low-voltage power supply by a level shifter interposed between the low-voltage power supply and the high-voltage power supply after the potential of the high-voltage power supply reaches the potential of the low-voltage power supply. To boost the high voltage power supply.

Here, the time after the potential of the high-voltage power supply has reached the potential of the low-voltage power supply may be strictly when the potential of the high-voltage power supply has reached the potential of the low-voltage power supply. It may be from the time when the potential reaches a value approximately equal to the potential of the low-voltage power supply. The level shifter is interposed between the low-voltage power supply and the high-voltage power supply, and the configuration can be changed as appropriate without any limitation from the viewpoint that it is sufficient that the low-voltage power supply can be used to boost the high-voltage power supply. It is. The boosting control circuit may be any circuit that boosts the high-voltage power supply using a level shifter after the potential of the high-voltage power supply reaches the potential of the low-voltage power supply when boosting the high-voltage power supply.

As a configuration example when the potential of the high-voltage power supply is lower than the potential of the low-voltage power supply, the invention according to claim 2 is the power supply booster circuit according to claim 1,
When the potential of the high-voltage power supply is lower than the potential of the low-voltage power supply, the first boosting clock signal generated in the low-voltage circuit interposed between these low-voltage power supplies and the high-voltage power supply The high voltage power supply is stepped up by input to a charge pump interposed therebetween.

That is, when the potential of the high-voltage power supply is lower than the potential of the low-voltage power supply, the low-voltage circuit interposed between the low-voltage power supply and the high-voltage power supply generates a first boosting clock signal, The high-voltage power supply is boosted by input to a charge pump interposed between the circuit and the high-voltage power supply.

Further, as a configuration example when the potential of the high-voltage power supply reaches the potential of the low-voltage power supply,
3. The power supply boosting circuit according to claim 2, wherein the boosting control circuit causes the first boosting clock signal to be supplied to the level shifter when the potential of the high-voltage power supply reaches the potential of the low-voltage power supply. A switch is provided to input the level-shifted second boosting clock signal to the charge pump to boost the high-voltage power supply.

That is, when the potential of the high-voltage power supply reaches the potential of the low-voltage power supply, the switch supplies the first boosting clock signal to the level shifter. Then, the second boosting clock signal that has been level-shifted to the high potential by the level shifter is input to the charge pump, and the high-voltage power supply boosts the voltage.

As a configuration example for detecting that the potential of the high-voltage power supply has reached the potential of the low-voltage power supply, the invention according to claim 4 is the power supply boosting circuit according to claim 3, wherein the boosting control circuit comprises: And a timer that causes the switch to supply the first boosting clock signal to the level shifter when the set time has elapsed. Is provided.

That is, when the timer sets the time from when the high-voltage power supply is boosted to become the potential of the low-voltage power supply or more,
When the set time has elapsed, the switch is supplied with the first boosting clock signal to the level shifter.

As another configuration example for detecting that the potential of the high-voltage power supply has reached the potential of the low-voltage power supply, the invention according to claim 5 is the power supply booster circuit according to any one of claims 1 to 4. , The step-up control circuit includes a comparator for comparing the potential of the high-voltage power supply with the potential of the low-voltage power supply.

That is, the comparator compares the potential of the high-voltage power supply with the potential of the low-voltage power supply and, when detecting that the potential of the high-voltage power supply has reached the potential of the low-voltage power supply, causes the high-voltage power supply to be boosted using a level shifter. .

The invention according to claim 6 is an example of a configuration in which the comparator detects that the potential of the high-voltage power supply has reached the potential of the low-voltage power supply and executes boosting of the high-voltage power supply using a level shifter. Wherein the comparator outputs a low-level signal to the switch when the potential of the high-voltage power supply is lower than the potential of the low-voltage power supply;
When the potential of the high-voltage power supply reaches the potential of the low-voltage power supply, a high-level signal is output to the switch.

That is, the comparator outputs a low-level signal to the switch when the potential of the high-voltage power supply is lower than the potential of the low-voltage power supply, and outputs the high-level signal when the potential of the high-voltage power supply reaches the potential of the low-voltage power supply. Output to the switch. Therefore, when a low level signal is input, the switch boosts the high voltage power supply without using a level shifter, and when a high level signal is input, boosts the high voltage power supply using the level shifter.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a main configuration of a power supply booster circuit according to an embodiment of the present invention.

The power supply boosting circuit includes a diode 1, a low voltage circuit 2, a level shifter 3, a charge pump 4, a comparator 7, and a switch 8. Diode 1 has VD
An initial voltage is supplied from D10 to VLCD 11, and after boosting, VLCD
Backflow from the LCD 11 to the VDD 10 is prevented. The low voltage circuit 2 generates a boost clock signal 5 that operates at the VDD 10 and operates the charge pump 4.

The level shifter 3 operates on the VLCD 11 to shift the level of the clock generated by the low voltage circuit 2 and outputs the clock to the switch 8 operated by the high voltage power supply. Charge pump 4
Operates at VDD10 to generate VLCD11. The comparator 7 operates on the VLCD 11 and compares the potential of the VDD 10 with the potential of the VLCD 11.

The switch 8 is connected to the VLC immediately after the low-voltage power is turned on.
When D11 is lower than VDD10, the boosting clock signal 5 is selected, and after a predetermined time elapses, VLCD11 switches to VDD1.
When it becomes higher than 0, the boosted clock signal 6 whose level has been shifted is selected and output to the charge pump 4.

Therefore, the potential of VDD 10 and VLCD 11
And the comparator 7 that compares the potential of the VLCD 11 and the boosting clock signal 5 when the VLCD 11 is lower than the VDD 10. When the VLCD 11 becomes higher than the VDD 10, the boosting clock signal 6 whose level is shifted is selected. The switch 8 that outputs to the pump 4 means, in this sense,
This constitutes a boost control circuit according to the present invention.

The boosting clock signal 5 generated by the low voltage circuit 2 and the boosting clock signal 6 shifted in level by the level shifter 3 are, in this sense, the first boosting clock according to the present invention. The signal and the second boosting clock signal are respectively configured.

FIG. 2 shows V when the power supply boosting circuit is operated.
The change of DD10 and VLCD11 is shown by the graph. First, when VDD10 rises, VDD10
A voltage lower than VDD10 by Vf is applied to the VLCD 11 by the diode 1 connected to the VLCD 11 in the forward direction (period t0 to t1). At this time, the comparator 7 operates during the period when the VLCD 11 is lower than the VDD 10.
0 ”(LOW) is output, and the switch 8 controls the low-voltage circuit 2 to directly input the boosting clock signal 5 to the charge pump 4, thereby performing the boosting operation.

It should be noted that the potential of VDD10 is
Is low, the output of the comparator 7 is "0" (L
OW) means that the charge pump 4
In order to select the boosting clock signal 5 to be input to the. When the boosting clock signal 5 is input to the charge pump 4 and the VLCD 11 starts boosting and rises to the same potential as the VDD 10, the level shifter 3 can normally shift the level of the boosting clock signal.
The potential of 11 will soon become higher than the potential of VDD10 (period from t1 to t2).

The comparator 7 is connected to the VLCD 11
That the potential of VDD has become greater than the potential of VDD10, and outputs "1" (HIGH).
Operates such that the boosting clock signal 6 obtained by shifting the level of the boosting clock signal 5 is input from the low-voltage circuit 2 to the charge pump 4 via the level shifter 3 (after t2).

Therefore, when the VLCD 11 is smaller than the VDD 10, the boosting clock signal 5 is directly input to the charge pump 4 without passing through the level shifter 3. For this reason, the boost operation is performed up to the operation limit of the circuit on the low voltage side,
Even if VDD10 becomes low, the boosting operation can be performed.

In this embodiment, in order to operate the charge pump 4 up to the operation limit of the low voltage circuit 2, the VLCD 11 is compared with the VDD 10 by the comparator 7, and the VLCD 1
When the potential of 1 is lower than the potential of VDD 10, the boosting clock signal of the charge pump 4 is realized by directly inputting it without passing through the level shifter 3. However, it can be realized by switching the switch 8 by a timer. it can. FIG. 3 shows the configuration in this case.

A timer 16 is used in place of the comparator 7 shown in FIG. 1, and the time from when the power is turned on until the VLCD 11 is boosted and becomes equal to the VDD 10 (t0 to t0 shown in FIG. 2).
(period of t2), and the output of the timer 16 is changed from “0” to “1”. The switch 8 outputs the boosting clock signal 5 to the charge pump 4 while the output from the timer 16 is “0”, and outputs the boosting clock signal 5 after the output from the timer 16 changes to “1”. The boosting clock signal 6 whose level has been shifted via the level shifter 3 is output to the charge pump 4.

Therefore, it is possible to obtain an operation of switching the boosting clock signal input to the charge pump 4 by the timer 16. Note that the configuration of the timer 16 may be any configuration that generates the time until the VLCD 11 becomes the same as the VDD 10.

As described above, the comparator 7 controls the VLCD
When the switch 8 detects that the potential of 11 has reached the potential of VDD 10, the switch 8 supplies the boosting clock signal 5 to the level shifter 3, and outputs the boosting clock signal 6 whose level has been shifted to the high potential by the level shifter 3. Since the voltage is input to the charge pump 4, the voltage of the VDD 10 can be reduced without depending on the driving limit of the level shifter 3, thereby providing a power supply boosting circuit capable of boosting the voltage to the operation limit.

[0037]

As described above, according to the present invention, when boosting a high-voltage power supply using a high-magnification power supply boosting circuit, the level shifter is not used while the potential of the high-voltage power supply is lower than the potential of the low-voltage power supply. By realizing low voltage of the low voltage power supply without depending on the drive limit of the level shifter, a power supply boosting circuit capable of boosting the voltage to the operation limit can be provided. According to the invention of claim 2, when the potential of the high-voltage power supply is lower than the potential of the low-voltage power supply, the high-voltage power supply can be boosted with a simple configuration without using a level shifter.

Further, according to the invention of claim 3,
When the potential of the high-voltage power supply reaches the potential of the low-voltage power supply, the high-voltage power supply can be boosted by the level shifter using the boosting clock signal. Furthermore, according to the invention of claim 4, it is possible to detect that the potential of the high-voltage power supply has reached the potential of the low-voltage power supply based on the elapsed time.

Further, according to the invention of claim 5,
The comparator can detect that the potential of the high-voltage power supply has reached the potential of the low-voltage power supply. Further, claim 6
According to the invention, the switching operation in the switch can be controlled in accordance with the level of the signal output from the comparator.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a power booster circuit according to an embodiment.

FIG. 2 is a graph for explaining the operation of the power supply boosting circuit according to the embodiment.

FIG. 3 is a block diagram showing a configuration of a power supply boosting circuit according to a modification.

FIG. 4 is a circuit diagram showing a configuration example of a level shifter in a conventional example.

FIG. 5 is a block diagram showing a configuration of a power supply boosting circuit in a conventional example.

FIG. 6 is a graph for explaining the operation of a power supply boosting circuit in a conventional example.

FIG. 7 is a graph for explaining an operation of a power supply boosting circuit in a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Diode 2 Low voltage circuit 3 Level shifter 4 Charge pump 5, 6 Boost clock signal 7 Comparator 8 Switching device 10 Low voltage power supply (VDD) 11 High voltage power supply (VLCD) 16 Timer

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yasuhiro Yokozawa 1-403, Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa 53 F-term in NEC Icy Microcomputer System Co., Ltd. (reference) 5H730 AA04 BB02 BB57 FD01 FD11 5J039 CC15 CC18 KK20 KK34 MM16

Claims (6)

[Claims] 1. A high voltage power supply interposed between a low voltage power supply and a high voltage power supply,
A level shifter capable of boosting the high-voltage power supply using the low-voltage power supply; and, when boosting the high-voltage power supply, using the level shifter after the potential of the high-voltage power supply reaches the potential of the low-voltage power supply. And a boosting control circuit for boosting the voltage. 2. The power supply boosting circuit according to claim 1, wherein the boosting control circuit is configured to switch between the low-voltage power supply and the high-voltage power supply when a potential of the high-voltage power supply is lower than a potential of the low-voltage power supply. Boosting the high-voltage power supply by inputting a first boosting clock signal generated by an intervening low-voltage circuit to a charge pump interposed between the low-voltage circuit and the high-voltage power supply. Power booster circuit. 3. The power supply boosting circuit according to claim 2, wherein said boosting control circuit sends said first boosting clock signal to said level shifter when a potential of said high-voltage power supply reaches a potential of said low-voltage power supply. A booster circuit for supplying a second boosting clock signal, which has been level-shifted to a high potential by the level shifter, to the charge pump to boost the high-voltage power supply. 4. The power supply boosting circuit according to claim 3, wherein the boosting control circuit can set a time until the high-voltage power supply is boosted and becomes equal to or higher than the potential of the low-voltage power supply. And a timer for causing the switch to supply the first boosting clock signal to the level shifter when the set time has elapsed. 5. The power supply boosting circuit according to claim 1, wherein the boosting control circuit includes a comparator that compares a potential of the high-voltage power supply with a potential of the low-voltage power supply. Power booster circuit. 6. The power supply boosting circuit according to claim 5, wherein the comparator outputs a low-level signal to the switch when a potential of the high-voltage power supply is lower than a potential of the low-voltage power supply. When the potential of the power supply reaches the potential of the low-voltage power supply, a high-level signal is output to the switch.