JP2001024159A - Semiconductor integrated circuit device and layout method for semiconductor integrated circuit device - Google Patents

Abstract

(57) Abstract: In a semiconductor integrated circuit device, a large number of capacity cells can be inserted, and a timing violation can be automatically repaired without changing the size of a standard cell. In a semiconductor integrated circuit device, a capacity cell that can be changed to a repair cell by changing a contact 101 or the like is arranged in an empty area. Similarly, when a repair cell is required, the capacity cell is changed to a repair cell. use. In addition, a capacitor cell that can be changed to a repeater cell by changing the contact is placed in an empty area adjacent to the long-distance wiring, and if a timing violation occurs in the long-distance wiring, the capacitance cell is changed to a repeater cell. use.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device and a layout method for the semiconductor integrated circuit device.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit device, a capacitance cell using a gate capacitance of a transistor is inserted as a bypass capacitor in a region where a functional circuit block is not arranged in order to suppress a voltage fluctuation of a power supply line. FIG.
Is a plan view of a conventional semiconductor integrated circuit device, FIG.
1 is a plan view of a capacitor cell in a conventional semiconductor integrated circuit device, FIG. 1B is a cross-sectional view taken along line XY of FIG. 1A, FIG. 1 is a layout diagram of the capacitor cell, and 1 is a p-type semiconductor. Substrate, 2 is polysilicon, 3 is aluminum wiring, 100 is contact, 36 is p + diffusion region, 6 is power supply wiring, 7 is ground wiring, 8 is functional circuit block,
9 is a pad block and 10 is a space area where no functional circuit block is arranged. In FIG. 9, the signal wiring and the power supply wiring in the block are omitted. In a conventional semiconductor integrated circuit device, as shown in FIG. 11, capacitance cells are arranged in a space area 10 where no functional circuit block is arranged on both sides of a power supply line 6 and a ground line 7. The structure of the capacitance cell is shown in FIGS. 10A and 10B, and a capacitor is formed between the polysilicon 2 and the p-type semiconductor substrate 1.

A repair cell is inserted into a functional circuit block to correct the function after diffusion. FIG. 12 is a plan view of a semiconductor integrated circuit designed by using a conventional standard cell. Reference numeral 8 denotes a functional circuit block whose layout is designed by the standard cell method, reference numeral 21 denotes a standard cell, reference numeral 22 denotes a pad, and reference numeral 23 denotes a repair cell. It is. Since the repair cell 23 is a standard cell used when the function needs to be changed after the diffusion, it is not used as a repair cell when the function does not need to be changed.

In order to correct the timing violation after the layout is completed in the functional circuit block 8, the fan-out of the standard cell driving the signal wiring in which the timing violation has occurred is changed. Changing the fan-out changes the size of the standard cell, and thus requires re-layout.

[0005]

When the area where the functional circuit block into which the capacity cell can be inserted is reduced due to the progress of miniaturization of the process, it becomes difficult to insert a bypass capacitor having a sufficient capacity, and the voltage of the power supply wiring is reduced. Fluctuations cannot be sufficiently suppressed, and there is a problem in that if a noise is generated in the outside world or a sufficient capacity cell is arranged, the semiconductor substrate becomes large and the cost increases.

Further, the repair cell is not used at all when the function does not need to be changed, and occupies a useless space.

Further, by changing the fan-out of the standard cell driving the signal wiring in which the timing violation has occurred, the size of the standard cell changes, and the layout is re-laid out. there were.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and occupies a semiconductor integrated circuit device in which a bypass capacitor which does not require a dedicated area for placement is inserted, and an unused and wasteful space. It is an object of the present invention to provide a semiconductor integrated circuit device using a repair cell as a capacity cell, and a layout method of a semiconductor integrated circuit device capable of correcting a timing violation without changing the size of a standard cell during a relayout.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a first transistor, and a second transistor. Wiring provided for the third transistor and the fourth transistor;
A first transistor, a second transistor, a third transistor, and a contact for connecting the fourth transistor and a wiring; and a first transistor, a second transistor, a third transistor, and a fourth transistor. A first mode in which the capacitance is connected to a power supply; and a second mode in which the capacity of the first transistor and the fourth transistor is connected to the power supply.
A second mode in which the first and third transistors are used for logic and a third mode in which the first transistor, the second transistor, the third transistor, and the fourth transistor are used for logic are contacted. Are selected by changing the position of the item.

According to the semiconductor integrated circuit device of the first aspect, by selecting an aspect, a repair cell that has not been used conventionally can be used as a capacity cell, and a large amount of bypass capacitors can be inserted into the power supply.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit device including a plurality of transistors, a wiring provided for the plurality of transistors, and a contact connecting the plurality of transistors to the wiring, and The whole capacity of the transistor is connected to a power supply.

According to the semiconductor integrated circuit device of the second aspect, the same effect as that of the first aspect is obtained.

According to a third aspect of the present invention, in the semiconductor integrated circuit device according to the first aspect, the first transistor, the second transistor, the third transistor, and the fourth transistor of the semiconductor integrated circuit device are MOSFETs. .

According to the semiconductor integrated circuit device of the third aspect, in addition to the same effects as those of the first aspect, when a MOSFET is used as a transistor, an n-channel or a p-channel can be used for a gate capacitance. Capacitance fluctuations due to process fluctuations can be reduced as compared to the case where only channels are used.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit device according to the first aspect, the logic of the semiconductor integrated circuit device is a combinational logic.

According to the semiconductor integrated circuit device of the fourth aspect, the same effect as that of the first aspect is obtained.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit device according to the first aspect, the logic of the semiconductor integrated circuit device is an inverter logic or a NAND logic.

According to the semiconductor integrated circuit device of the fifth aspect, the same effect as that of the first aspect is obtained.

The layout method of a semiconductor integrated circuit device according to claim 6, wherein the capacitive cell inserted over replacing the input layout data to the detected capacitance cell region without cells
And extent, and the long-distance wires detection step of detecting a long-distance wiring from the layout data, and the capacitor cell detection step of detecting a capacitive cell under the long-distance wires, the capacitance cell for connecting the long-distance wiring and capacitance cell line , A timing analysis process for analyzing the timing of layout information, a timing violation detection process for detecting a long-distance wiring having a timing violation of the layout information, and a capacitance cell under the long-distance wiring having a timing violation. It includes a process of detecting a capacity cell to be detected and a process of inserting a repeater cell for changing a capacity cell to a repeater cell.

According to the layout method of the semiconductor integrated circuit device according to the present invention, when correcting a timing violation, it can be performed without changing the size of the standard cell. Since the repeater cell can be inserted without any change, the man-hour at the time of re-layout can be reduced. After the diffusion, when a timing violation occurs and the repeater cell is inserted, the change from the capacity cell to the repeater cell can be performed only by changing the contact, so that only one mask is required to be changed, and the cost can be reduced. .

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1A is a schematic diagram of a layout of an inverter of a semiconductor integrated circuit device according to the first embodiment, where 31 is a first transistor, 32 is a second transistor, and 33 is a third transistor. Transistor, 34 a fourth transistor, 35 an n-diffusion region, 60 an input signal wiring, 6
1 is an output signal wiring, 100, 101, 110 and 111 are contacts, and 120 and 121 are single-layer aluminum wirings on the transistor. The contact 110 makes contact between the output signal wiring 61 and the single-layer aluminum wiring 120. The contact 111 makes contact between the input signal wiring 60 and the single-layer aluminum wiring 121. FIG.
2 is an electric circuit diagram of FIG. First transistor 31, second transistor 32, third transistor 3
The third and fourth transistors 34 are connected to the input signal wiring 60 and the output signal wiring 61 as logic.

FIG. 2A is a schematic diagram of a layout of inverters and capacitors of the semiconductor integrated circuit device according to the first embodiment, and 102 and 103 are contacts. FIG.
FIG. 2B is an electric circuit diagram of FIG. The gate capacitances of the first transistor 31 and the fourth transistor 34 are connected to a power supply, and the second transistor 32 and the third transistor 33 are connected to the input signal wiring 60 and the output signal wiring 61 as logic.

FIG. 3A is a schematic diagram of the layout of the capacitance of the semiconductor integrated circuit device according to the first embodiment.
Reference numerals 104, 112, and 113 indicate contacts, and reference numeral 130 indicates polysilicon. Contact 112 is in contact with input signal wiring 60 and polysilicon 130. The contact 113 is in contact with the output signal wiring 61 and the polysilicon 130. FIG. 3B is an electric circuit diagram of FIG. First transistor 31, second transistor 32, third transistor 33, fourth transistor 3
4 is connected to the power supply. The circuit change from FIG. 1A to FIG. 2A is performed by attaching a contact 102 except for the contact 101. The change of the circuit from FIG. 2A to FIG. 3A is performed by attaching a contact 104 except for the contact 103.

FIG. 4A is a schematic diagram of a NAND layout of the semiconductor integrated circuit device according to the first embodiment, and 140 is a contact. FIG. 3B is an electric circuit diagram of FIG. A first transistor 31,
The second transistor 32, the third transistor 33, and the fourth transistor 34 are used as logic for the input signal wiring 60,
It is connected to the output signal wiring 61.

FIG. 5A is a schematic diagram of a layout of NANDs and capacitors of the semiconductor integrated circuit device according to the first embodiment, and 141 and 142 are contacts. FIG.
FIG. 2B is an electric circuit diagram of FIG. The gate capacitances of the first transistor 31 and the fourth transistor 34 are connected to a power supply, and the second transistor 32 and the third transistor 33 are connected to the input signal wiring 60 and the output signal wiring 61 as logic.

FIG. 6A is a schematic diagram of a layout of the capacitance of the semiconductor integrated circuit device according to the first embodiment.
143 is a contact. FIG. 6B is an electric circuit diagram of FIG. Gate capacitances of the first transistor 31, the second transistor 32, the third transistor 33, and the fourth transistor 34 are connected to a power supply.

The circuit change from FIG. 4A to FIG. 5A is performed by attaching a contact 141 except for the contact 140. The change of the circuit from FIG. 5A to FIG. 6A is performed by attaching the contact 143 except for the contact 142. The structure shown in FIGS. 3A and 6A is arranged in a semiconductor integrated circuit as a capacitance cell. When used as a repair cell, the contact of the capacity cell is changed as shown in FIGS. 1A, 2A, 4A, and 5A to be used as a functional cell.

In this embodiment, the case where the transistor is a MOSFET has been described. However, the present invention is not limited to the MOSFET, and the same effect can be obtained when a transistor such as a bipolar transistor is used. In this embodiment, the case where the logic is the inverter and the NAND has been described. However, the present invention is not limited to the inverter and the NAND, and the same effect can be obtained for other logics. In the present embodiment,
Although the case where the wiring is made of polysilicon and single-layer aluminum wiring has been described, the present invention is not limited to the case of using polysilicon and single-layer aluminum wiring, and similar effects can be obtained when wiring of another layer or another material is used. Can be

FIG. 7 is a flow chart of a layout method of a semiconductor integrated circuit device according to a second embodiment of the present invention, wherein reference numeral 80 denotes a layout data input step, and reference numeral 81 denotes an area without cells based on the layout data. Is replaced with a capacity cell by a capacity cell insertion means.
Is a long-distance wiring detection step of detecting long-distance wiring based on layout data by long-distance wiring detection means, 83 is a capacitance cell detection step of detecting a capacitance cell under the long-distance wiring by capacitance cell detection means, 84 is 85. Connection process between the capacitance cell and the wiring for connecting the capacitance cell and the long-distance wiring by the connection means,
Is a timing analysis step in which timing analysis is performed by the timing analysis means based on the layout data, and 86 is a timing violation in which a long-distance wiring having a timing violation is detected by the long-distance wiring detection means based on the result of the timing analysis step 85. A long-distance wiring detection step 87 is a capacitance cell detection step in which a capacitance cell below a wiring having a timing violation is detected by a capacitance cell detection means, and a capacitance cell detected in the capacitance cell detection step 87 is repeated to a repeater cell. This is a repeater cell insertion process changed by the cell insertion means. In the capacity cell insertion step 81, a changeable capacity cell is inserted into a repeater cell having buffer logic by changing a contact. In the long distance wiring detection step 82, a long distance wiring is detected by comparing a wiring length with a parameter given in advance. The capacitance cell detection step 83 is performed by comparing the coordinates of the wiring and the coordinates of the capacitance cell.

FIG. 8 is a configuration diagram showing a capacitance cell and a signal wiring in the layout method of the semiconductor integrated circuit device according to the second embodiment. FIG. 8A shows a state before the capacitance cell 90 and the signal wiring 91 are connected. FIG. 2B is a layout diagram after the capacitance cell 90 and the signal wiring 91 are connected, where 90 is a capacitance cell, and 91 is a signal wiring. In the connection step 84 between the capacitance cell 90 and the wiring 91, the capacitance cell 90 and the wiring 91 are connected as shown in the figure. Reference numeral 30 denotes a contact. In the capacity cell detection step 83, 1
When there are a plurality of wirings on one capacitance cell, first, the names of the signal wirings on the capacitance cell are stored. Then, after connecting the signal cell and the signal wiring in the case where there is one signal wiring on the capacitance cell, the length of the signal wiring on the capacitance cell having a plurality of wirings is compared, and the signal wiring is connected to the longest wiring.

In this embodiment, the case where the layer through which the power supply wiring runs is a layer below the layer through which the signal wiring 91 runs is described. However, the present invention is not limited to this case, and the present invention is not limited to this case. The same effect can be obtained in the case of. The timing analysis step 85 can be performed using a timing analysis tool used by the ASIC vendor. In the long-distance wiring detection step 86 having a timing violation, the timing-violation wiring obtained by the timing analysis step 85 is compared with the long-distance wiring obtained in the long-distance wiring detection step 82, and a matching long-distance wiring is detected. The repeater cell inserting means 88 replaces the capacity cell obtained in the capacity cell detection step 87 with a repeater cell. This replacement can be performed by changing the contact 30. When there are a plurality of capacitance cells on the same wiring in the repeater cell insertion step 88, the capacitance cell closest to the center of the wiring is replaced with the repeater cell.

[0033]

According to the semiconductor integrated circuit device of the first aspect, by selecting the mode, a repair cell that has not been used conventionally can be used as a capacity cell, and a large amount of bypass capacitors can be inserted into the power supply.

According to the semiconductor integrated circuit device of the second aspect, the same effect as that of the first aspect is obtained.

According to the semiconductor integrated circuit device of the third aspect, in addition to the same effects as those of the first aspect, when a MOSFET is used as a transistor, an n-channel or a p-channel can be used for a gate capacitance. Capacitance fluctuations due to process fluctuations can be reduced as compared to the case where only channels are used.

According to the semiconductor integrated circuit device of the fourth aspect, the same effect as that of the first aspect is obtained.

According to the semiconductor integrated circuit device of the fifth aspect, the same effect as that of the first aspect is obtained.

According to the layout method of a semiconductor integrated circuit device according to the present invention, when correcting a timing violation, it can be performed without changing the size of the standard cell. Since the repeater cell can be inserted without any change, the man-hour at the time of re-layout can be reduced. After the diffusion, when a timing violation occurs and the repeater cell is inserted, the change from the capacity cell to the repeater cell can be performed only by changing the contact, so that only one mask is required to be changed, and the cost can be reduced. .

[Brief description of the drawings]

FIGS. 1A and 1B are a schematic diagram (a) and an electric circuit diagram (b) of a layout of an inverter of a semiconductor integrated circuit device according to a first embodiment.

FIGS. 2A and 2B are a schematic diagram (a) and an electric circuit diagram (b) of a layout of inverters and capacitors of the semiconductor integrated circuit device according to the first embodiment.

FIGS. 3A and 3B are a schematic diagram (a) and an electric circuit diagram (b) of a layout of a capacitance of the semiconductor integrated circuit device according to the first embodiment. FIGS.

FIGS. 4A and 4B are a schematic diagram (a) and an electric circuit diagram (b) of a NAND layout of the semiconductor integrated circuit device according to the first embodiment.

FIGS. 5A and 5B are a schematic diagram of a layout of NAND and capacitors of the semiconductor integrated circuit device according to the first embodiment, and FIG.

FIGS. 6A and 6B are a schematic diagram of a capacitance layout of the semiconductor integrated circuit device according to the first embodiment and an electric circuit diagram of FIG.

FIG. 7 is a flowchart illustrating a layout method of a semiconductor integrated circuit device according to a second embodiment.

FIG. 8 is a configuration diagram showing a capacitance cell and a signal wiring in a layout method of a semiconductor integrated circuit device according to a second embodiment.

FIG. 9 is a plan view of a conventional semiconductor integrated circuit device.

FIG. 10A is a plan view of a capacitor cell in a conventional semiconductor integrated circuit device, and FIG.

FIG. 11 is a layout diagram of a capacitance cell in a conventional semiconductor integrated circuit device.

FIG. 12 is a plan view of a semiconductor integrated circuit designed using a conventional standard cell.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 p-type semiconductor substrate 2, 130 polysilicon 3, 120, 121 1 layer aluminum wiring 6 power supply wiring 7 ground wiring 8 functional circuit block 9 pad block 10 area where no functional block is arranged 21 standard cell 22 pad 23 repair cell 31 1 transistor 32 second transistor 33 third transistor 34 fourth transistor 35 n diffusion region 36 p diffusion region 60 input signal wiring 61 output signal wiring 80 layout data input process 81 capacitance cell insertion process 82 long distance wiring detection Process 83 Capacitance cell detection process 84 Capacitance cell and wiring connection process 85 Timing analysis process 86 Long distance wiring detection process with timing violation 88 Repeater cell insertion process 90 Capacitance cell 91 Signal wiring 100 to 104, 110, 111 , 140-143 contacts

Claims (6)

[Claims] A first transistor, a second transistor, a third transistor, and a fourth transistor; and the first transistor, the second transistor, the third transistor, and the fourth transistor. A wiring provided for the first transistor, the second transistor, the third transistor, and the fourth transistor; and a contact connecting the wiring to the wiring. A first aspect in which the capacitances of the second transistor, the third transistor, and the fourth transistor are connected to a power supply; and a second aspect in which the capacitances of the first transistor and the fourth transistor are connected to a power supply. A transistor and the third
A second mode in which the first transistor, the second transistor, the third transistor, and the fourth transistor are used for logic; A semiconductor integrated circuit device selected by changing the position of the semiconductor integrated circuit. 2. A semiconductor device comprising: a plurality of transistors; a wiring provided for the plurality of transistors; and a contact for connecting the plurality of transistors to the wiring. A connected semiconductor integrated circuit device. 3. The first transistor, the second transistor, the third transistor, and the fourth transistor of the semiconductor integrated circuit device.
2. The semiconductor integrated circuit device according to claim 1, wherein said transistor is a MOSFET. 4. The semiconductor integrated circuit device according to claim 1, wherein the logic of the semiconductor integrated circuit device is combinational logic. 5. The semiconductor integrated circuit device according to claim 1, wherein the logic of the semiconductor integrated circuit device is inverter logic or NAND logic. 6. A capacitor cell inserting step of detecting a cell-free area from input layout data and replacing it with a capacitor cell, a long-distance wiring detecting step of detecting a long-distance wiring from the layout data, and a step of detecting the long-distance wiring. A capacitance cell detection step of detecting the underlying capacitance cell; a connection step of a capacitance cell and a wiring connecting the long-distance wiring and the capacitance cell; a timing analysis step of performing timing analysis of the layout information; A timing violation detecting step of detecting a long distance wiring having a timing violation of information; a capacitance cell detecting step of detecting a capacitance cell below the long distance wiring having the timing violation; and changing the capacitance cell to a repeater cell. A layout method for a semiconductor integrated circuit device including a step of inserting a repeater cell.