JP2001015619A - Manufacture of nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable to thin an insulation film (a film thickness converted to an oxide film) between a floating gate and a control gate with charge holding characteristics and dielectric strength maintained, and to prevent reduction in capacitance due to a bird's beak entering the floating gate and the control gate in a required oxidation process after the control gate is processed. SOLUTION: A tunnel oxide film 13 is formed on a semiconductor substrate of an element region defined by an element separation region, and a floating gate 14 is formed on the tunnel oxide film. A silicon oxide film 15A is formed on the floating gate 14 by a CVD method, and a nitride film 15B is formed by introducing nitrogen in the vicinity of an interface between the floating gate 14 and the silicon oxide film 15A. Moreover, a silicon nitride film 15C is formed on the silicon oxide 15A by a low pressure CVD method, and a control gate is formed on the silicon nitride film 15C.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device, and more particularly to a method of manufacturing an insulating film between a floating gate and a control gate of a memory cell having a stacked gate structure.

[0002]

2. Description of the Related Art At present, in a nonvolatile semiconductor memory device having a floating gate and a control gate, an insulating film (ONO film) composed of three layers of an oxide film / nitride film / oxide film is used as an insulating film between the floating gate and the control gate. ) Is used.

FIG. 11 is a sectional view of a memory cell in the semiconductor memory device.

An element isolation region 102 is formed in a p-type silicon substrate 101, and a tunnel oxide film 103 is formed in an element region partitioned by the element isolation region 102. The floating gate 10 is formed on the tunnel oxide film 103.
4, an insulating film (ONO film) 105 composed of the three layers and a control gate 106 are formed. The insulating film (ONO)
The cross-sectional structure of the film 105 is shown in FIG. An oxide film 105A is formed in a lower layer, a nitride film 105B is formed in an intermediate layer, and an oxide film 105C is formed in an upper layer.

Generally, in a nonvolatile semiconductor memory device, it is necessary to inject electrons into the floating gate 104 and hold it for a practically sufficient time. In the state of holding electrons,
Relatively weak electric field (self electric field) generated by the electrons
Is applied to the insulating film (ONO film) 105 between the floating gate 104 and the control gate 106. If the oxide film 105A under the ONO film 105 is 6 nm or more, Fo
Since a wler-Nordheim type tunneling current conduction mechanism is shown and the current flowing in a low electric field is extremely small, electrons can be trapped in the floating gate 104 for a practically sufficient time. When the upper oxide film 105C has a thickness of 3 nm or more, hole injection can be prevented, and the three-layer film can have high insulating properties even in a high electric field.

As described above, in the conventional ONO film, in order to prevent a direct tunnel phenomenon, the underlying oxide film 10 is formed.
5A needs to have a thickness of 6 nm or more, and the upper oxide film 105C also needs to have a thickness of 3 nm or more to prevent injection of holes. In addition, in order to form a film having a regular nitride film function without defects such as pinholes, the nitride film 105B generally needs to have a thickness of at least about 5 nm. Then, in the conventional oxide film / nitride film / oxide film structure, when this ONO film is converted into a film thickness of the oxide film by a dielectric constant, the converted film thickness is 12n.
m. This is because the nitride film has a dielectric constant approximately twice as large as that of the oxide film, and its thickness is reduced to half when converted to an oxide film. Here, the function of the nitride film is that if there is no hole injection, there is little leakage current when a high electric field is applied, and the trapping of electrons reduces the electric field at the electric field concentration part (edge of floating gate, etc.) It is.

[0007]

In recent years, the demand for lowering the withstand voltage of peripheral transistors and the operating voltage of memory cells has led to the demand for the insulating film 105 (ONO film).
It is necessary to reduce the equivalent oxide film thickness of the thin film.

However, the upper and lower oxide films 105C and 105C
When A is thinner than 3 nm and 6 nm, respectively, it becomes difficult to hold the charge, and the insulating property and the reliability decrease. For example, if the thickness of the lower oxide film 105A is less than 6 nm, the leak current due to the direct tunnel becomes a nonnegligible value, and it becomes difficult to hold the charge. Also, the upper oxide film 10
When 5C becomes thinner than 3 nm, a large amount of holes are formed in the nitride film 1.
The film that is injected into the substrate 05B and contributes to the withstand voltage is only the lower oxide film 105A.

Further, when the thickness of the nitride film 105B is also thinner than about 5 nm, the reduction of leakage current and the relaxation of electric field concentration become insufficient, and the reliability is reduced. Therefore, the insulating film 10
No. 5 cannot be thinner than about 12 nm in oxide film equivalent film thickness.

In the case of the ONO film 105, after the control gate is processed, usually, in a necessary oxidation step, as shown in FIG. 13, oxidation between the oxide film 105A and the floating gate 104 and between the oxide film 105C and the control gate 106 are performed. The bird's beak 107 penetrates into the gate, thereby lowering the capacitance between the floating gate and the control gate. FIG. 13 is a cross-sectional view of a memory cell having a floating gate, an insulating film, and a control gate when a bird's beak has occurred. The effect of the bird's beak on the capacitance is particularly large when the gate length is short.

The present invention has been made in view of the above-mentioned problems, and it is possible to reduce the thickness of an insulating film (equivalent oxide film thickness) between a floating gate and a control gate while maintaining charge retention characteristics and dielectric strength. It is an object of the present invention to provide a method for manufacturing a nonvolatile semiconductor memory device that can prevent a bird's beak from entering a floating gate and a control gate to reduce a capacity in an oxidation step necessary after processing a control gate.

That is, in other words, an object of the present invention is to increase the capacitive coupling ratio between the floating gate and the control gate so that the memory cell can be driven at a low voltage. In addition to reducing the equivalent oxide film thickness of the insulating film formed on the substrate, a decrease in capacitive coupling due to penetration of a gate bird's beak is prevented.

[0013]

In order to achieve the above object, a method of manufacturing a nonvolatile semiconductor memory device according to the present invention comprises the steps of: forming a gate insulating film on a semiconductor substrate; Forming a floating gate, forming a silicon oxide film on the floating gate by a CVD method, and forming a nitride layer by introducing nitrogen near an interface between the floating gate and the silicon oxide film. Process and
A step of forming a silicon nitride film on the silicon oxide film; and a step of forming a control gate on the silicon nitride film.

Further, in the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a step of forming a gate insulating film on a semiconductor substrate; a step of forming a floating gate on the gate insulating film; Forming a silicon oxide film by a CVD method; introducing nitrogen near the interface between the floating gate and the silicon oxide film to form a first nitride layer; A step of introducing nitrogen to form a second nitrided layer; and a step of forming a control gate on the second nitrided layer.

In a method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a step of forming an element isolation region on a semiconductor substrate and a step of forming a tunnel oxide on the semiconductor substrate in an element region partitioned by the element isolation region Forming a film, forming a floating gate on the tunnel oxide film, forming a silicon oxide film on the floating gate by CVD, and providing an interface between the floating gate and the silicon oxide film. Forming a nitride layer by introducing nitrogen in the vicinity, forming a silicon nitride film on the silicon oxide film by low-pressure CVD, and forming a control gate on the silicon nitride film. It is characterized by having.

As an oxide film forming method, there are an oxide film formed by thermal oxidation and a CVD method. In the present invention, a CVD oxide film is used. This is because when polycrystalline silicon doped with a large amount of n-type impurities is thermally oxidized to prevent depletion of the floating gate, the film quality of the oxide film is not good. This is because, at a high temperature, there is a problem that it is difficult to form a thin film aimed at by the present application and that a lower tunnel oxide film is deteriorated.

That is, in the present invention, a CVD oxide film is used as a film for preventing a leak current. If the ONO film is not used as the insulating film between the floating gate and the control gate, electron leakage due to electric field concentration at the edge of the floating gate becomes a problem.
The interface with the oxide film is strongly nitrided. In addition, the edge of the floating gate is rounded as necessary. As a result, the leakage current when a high electric field is applied is reduced, and the electric field in the electric field concentration portion is reduced. Further, the nitride layer formed at the interface between the floating gate and the CVD oxide film also prevents bird's beak from entering in a post-oxidation step after the gate processing.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

First, the structure of a nonvolatile semiconductor memory device manufactured by the manufacturing method according to the embodiment of the present invention will be briefly described.

FIG. 1 is a sectional view showing the structure of the nonvolatile semiconductor memory device.

The p-type silicon substrate 11 has an element isolation region 1
2 is formed, and a tunnel oxide film 13 is formed in an element region surrounded by the element isolation region 12. On the tunnel oxide film 13, the floating gate 14, the insulating film 1
5, the control gate 16 is formed in order.

[First Embodiment] Next, a method of manufacturing the nonvolatile semiconductor memory device of the first embodiment will be described.

FIGS. 2 to 5 are sectional views showing steps of a method for manufacturing the nonvolatile semiconductor memory device.

First, as shown in FIG. 2, an element isolation region 12 is formed on a p-type silicon substrate 11 by trench isolation or the like, and an element region partitioned by the element isolation region 12 is formed. A tunnel oxide film 13 is formed on the silicon substrate 11 in this element region. afterwards,
As shown in FIG. 3, a CV
The polycrystalline silicon film is formed to a thickness of 100 to 200 nm by the D method.
Degree formed. Then, the floating gate 14 is formed by patterning the polycrystalline silicon film by the RIE method. After depositing a tunnel oxide film and a part of the polycrystalline silicon film serving as a floating gate, a trench for element isolation is dug.
There is also a method of forming in the order of embedding with an insulating film.

Next, a method of forming the insulating film 15 will be described with reference to an enlarged view of a portion indicated by 4 in FIG. FIG.
FIG. 3C is an enlarged cross-sectional view illustrating a method of forming the insulating film 15 formed on the floating gate 14. FIG. 4D is an enlarged cross-sectional view showing the structure of another example of the insulating film described later.

As shown in FIG. 4A, the floating gate 14
A silicon oxide film 15A is formed to a thickness of 7n by CVD.
m. As a method for forming the silicon oxide film 15A, there are a thermal oxidation method and a CVD method. In the case of the thermal oxidation method,
A thermal oxide film of a polycrystalline silicon film (floating gate material) doped with impurities generally has poor film quality and a large leak current. In order to reduce the leakage current, it is necessary to oxidize at a high temperature. However, the high-temperature oxidation step deteriorates the quality of the tunnel oxide film under the floating gate, and is not preferable for a stack gate type flash memory.

In the case of the CVD method, it is desirable to deposit an HTO (High Temperature Oxide) oxide film by decomposition of trichlorsilane. This is because the HTO oxide film has high insulation properties and exhibits a leak characteristic close to that of a thermal oxide film.

In addition, an HTO oxide film using dichlorosilane as a source gas, and a CV by decomposition of a TEOS-based gas.
There is a D oxide film. Particularly, the former has good film quality and is often used. However, since the leakage current is large as compared with the HTO oxide film due to the decomposition of trichlorsilane, a CVD oxide film having a good thin film quality is formed as described above. In this case, an HTO oxide film formed by decomposition of trichlorsilane is more preferable.

The HTO oxide film resulting from the decomposition of trichlorsilane is SiCl4 + 2N2O → SiO2 + 2Cl2 +
It is formed at a temperature of, for example, 850 ° C. to 900 ° C. by a reaction of 2N2. Generally, compared to the HTO oxide film of dichlorsilane, the content of H2 is slightly lower and the content of Cl is higher.

Next, as shown in FIG. 4B, near the interface between the floating gate 14 and the silicon oxide film 15A, nitrogen is introduced to form a nitride layer 15B. N2O, NO,
By performing a heat treatment (nitriding process) in a gas such as ammonia, a nitride layer 15B can be formed near the interface between the floating gate 14 and the silicon oxide film 15A.

At this time, hydrogen may enter the underlying tunnel oxide film 13 and cause deterioration of the film quality. Therefore, in the nitriding treatment used here, N 2 O, N 2 containing no hydrogen is used.
Nitriding with O is more desirable. For example, heat treatment is performed at a temperature of 950 ° C. in N 2 O or NO gas. Although the amount of nitrogen that can be introduced varies depending on the process conditions, it is possible to introduce about several to 20% of nitrogen as atomic% near the interface. The reaction temperature may be further increased if necessary.

Since the nitride layer 15B on the floating gate 14 generally contains an electron trap unless a process for reducing the trap is particularly added, the electric field concentration at the edge of the floating gate 14 is reduced, and the leakage current during the high electric field operation is reduced. Has the function of suppressing. The nitride layer 15B is formed between the floating gate and the C layer.
Bird's beak can be sufficiently prevented from entering the interface of the VD oxide film.

Here, it is not possible to use a method in which a nitride film is formed on a floating gate by a low pressure CVD method and a CVD oxide film is formed thereon. This is because the interface between the CVD nitride film and the CVD oxide film and the CVD nitride film itself contain a large amount of traps, and the threshold voltage of the memory cell fluctuates as electrons enter and exit the traps.
This is, for example, by S. Mori et al., IEEE Trans. On Elect.
ron Devices vol.39 pp.283 (1992).

Next, as shown in FIG. 4C, a silicon nitride film 15C is formed to a thickness of 6 nm on the silicon oxide film 15A by a low pressure CVD method. When the silicon nitride film 15C applies a negative potential to the floating gate 14 to the control gate 16 to extract electrons from the floating gate 14 to the silicon substrate 11, electrons are injected from the control gate 16 to the floating gate 14. It has the function of effectively preventing it from being done. This is because when the silicon nitride film 15C has a film thickness enough to prevent holes from being injected to the anode side, the leak current under a high electric field can be suppressed to be lower than that of an oxide film.

For example, in recent NOR-type flash memories and NAND-type flash memories, an operation of extracting electrons from a floating gate to a silicon substrate over the entire channel is performed. At this time, if the amount of electrons injected from the control gate to the floating gate is large, the erasing time may be long, or conversely, writing may occur. In particular, in the case of NOR type flash memory, channel injection of electrons from the drain side is often used when injecting electrons, and a high electric field is applied between the floating gate and the control gate during operation when electrons are extracted from the floating gate. It is very important to reduce the leakage current at that time.

Thus, as shown in FIG. 5, the silicon oxide film 15A (including the nitride layer 15B) having a thickness of 7 nm is formed.
Then, an insulating film 15 made of a silicon nitride film 15C having a thickness of 6 nm is formed on the floating gate 14. In this case, when the insulating film 15 is converted into a thickness of an oxide film by a dielectric constant, the converted thickness is 10 nm. This is because the nitride film has a dielectric constant approximately twice as large as that of the oxide film, and its thickness is reduced to half when converted to an oxide film. 7 nm thick
If the silicon oxide film 15A exists, no leak current flows due to direct tunneling, and therefore, there is no problem in charge retention characteristics. More strictly, CVD
Since the oxide film is subjected to the nitriding treatment, the dielectric constant is increased. Therefore, there is also an advantage that the equivalent film thickness becomes smaller than 7 nm after the nitriding treatment even for a 7 nm film.

Next, as shown in FIG. 1, a polycrystalline silicon film having a thickness of about 200 to 400 nm is formed on the silicon nitride film 15C, that is, on the insulating film 15 by the CVD method. Subsequently, the control gate 16 and the floating gate 14 are formed by patterning the two-layered polycrystalline silicon film by the RIE method. After that, the nonvolatile semiconductor memory device is manufactured by a generally used manufacturing method.

With such a manufacturing process, the floating gate 1
4 and the effective oxide film thickness of the insulating film 15 between the control gate 16
A thin film can be formed while maintaining the charge retention characteristics and the withstand voltage. In particular, even when the thickness of the insulating film 15 is reduced, no problem occurs when electrons are emitted from the floating gate 14 to the silicon substrate 11.

In an ordinary nonvolatile semiconductor memory device, after an insulating film is formed on the floating gate, the insulating film, the floating gate material, and the tunnel oxide film in the transistor portion are removed. Thereafter, a step of performing oxidation to form a gate oxide film of the peripheral transistor is used. The insulating film is O
In the case of the NO film, since the silicon nitride film is present in the intermediate layer and its surface is hardly oxidized under the conditions when the gate oxide film of the peripheral transistor is formed, the peripheral circuit region can be oxidized using the ONO film as a mask material. . This first
Also in the structure of the insulating film 15 according to the embodiment, since the silicon nitride film 15C exists in the uppermost layer, the insulating film 15 on the floating gate 14 in the memory cell portion is not affected, and the gate oxide film of the peripheral transistor is not affected. Can be formed.

If the thickness of the uppermost silicon nitride film 15C is too large, the influence of the charges trapped in the silicon nitride film 15C on the threshold voltage of the memory cell cannot be ignored. Therefore, it is desirable that the thickness of the silicon nitride film 15C be 6 nm or less.

The main purpose of the silicon nitride film 15C is as follows.
The purpose is to prevent intrusion of the gate bird's beak and to function as a blocking film of an oxidizing agent in the oxidation step of the peripheral circuit portion. For this reason, the silicon nitride film 15C is formed, for example, by the JVD method (JetVap method) with few traps.
or Deposition method). This method is used, for example, in Applied Surfaces science 117
/ 118 (1997) pp 256-267. The concentration of hydrogen contained in the silicon nitride film 15C is set to 1 × 10 ¹⁹ cm.
^By controlling to ^-3 or less, the same low trap density can be obtained even when the film is formed by another film forming method, and the instability of the threshold voltage Vth due to the entrance and exit of charges into and from the trap can be reduced.

Further, in the device manufacturing process, the peripheral gate oxidation process is performed first, so that the surface of the insulating film between the floating gate and the control gate is not exposed, and when the device is not exposed to the oxidation process, It suffices if gate bird's beak can be suppressed. For this reason, as shown in FIG. 4D, there may be a case where a certain amount of the nitride layer 15D needs to be present on the surface of the silicon oxide film 15A without the silicon nitride film 15C. When strong nitriding is performed to introduce a large amount of nitrogen into the surface of the oxide film 15A in addition to the interface between the floating gate 14 and the CVD oxide film 15A, the uppermost silicon nitride film 15C may be omitted.

In the semiconductor memory device of this embodiment, an electron trap is generated by nitriding the vicinity of the interface between the polycrystalline silicon film of the floating gate 14 and the silicon oxide film (CVD oxide film) 15A formed by CVD. , And exerts an electric field relaxation effect. However, a large amount of electron traps cannot be formed like the interface between the oxide film and the nitride film in the ONO film. Therefore, when a problem such as electric field concentration occurs at the edge portion of the floating gate 14, the edge 14A of the floating gate 14 is formed before the CVD oxide film 15A is formed on the floating gate 14, as shown in FIG. It is advisable to add a rounding step.

The electric field concentration at the edge of the floating gate 14 is
Assuming that the equivalent oxide thickness of the insulating film 15 between the floating gate 14 and the control gate 16 is Tox, it can be calculated by the formula (Tox / In (1 + Tox / R)) × 1 / R. From this equation, when Tox = 12 nm, if the electric field concentration (how many times the electric field is applied to the plane portion at the edge) is to be suppressed within twice, the radius of curvature of the edge must be at least 5 nm or more. is there. Curvature 10
If it is set to nm, the electric field concentration can be suppressed to 1.5 times, and the curvature at 50 nm can be suppressed to 1.2 times or less. Actually, the reduction of the leak current by performing the normal nitriding treatment is in a range where the amount of current can be suppressed to, for example, 、. Therefore, it is desired to suppress the electric field concentration to about 1.2 times. If the curvature can be set to 50 nm or more, high insulation properties can be obtained.

The step of rounding the edge 14A includes a CD
After oxidizing the polycrystalline silicon film by E (Chemical Dry Etching) or high-temperature dilution oxidation, a method of removing and rounding the generated oxide film may be used. In addition, there are various methods such as rounding by processing in a hydrogen atmosphere at 950 ° C. to 1000 ° C. or using an appropriate wet processing. FIG. 6 is a sectional view of the nonvolatile semiconductor memory device at this time.

As described above, according to the first embodiment, a method of manufacturing a nonvolatile semiconductor memory device capable of reducing the thickness of an insulating film between a floating gate and a control gate while maintaining charge retention characteristics and dielectric strength. Can be provided.
Even if the insulating film is thinned, no problem occurs when electrons are emitted from the floating gate to the silicon substrate.Also, in the step of forming a gate oxide film of a peripheral transistor after the formation of the insulating film, a conventional method is used. As in the case of the ONO film described above, only the peripheral portion is oxidized using the insulating film as a mask to form a gate oxide film having a desired thickness.

[Second Embodiment] The nonvolatile semiconductor memory device according to the first embodiment has the above-mentioned effects and can be used sufficiently.
The natural oxide film present at the interface between 5A and the floating gate 14 (polycrystalline silicon film) has poor film quality, and the presence of the film may deteriorate the controllability of the final nitride layer 15B in thickness. . In some cases, this natural oxide film grows before the deposition step starts in a device for depositing a CVD oxide film. In such a case, it is effective that the surface of the floating gate 14 is nitrided after the formation of the floating gate (polycrystalline silicon film) 14 and before the deposition of the silicon oxide film 15A.

Hereinafter, a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment will be described.

FIGS. 2, 3, and 7A to 7D are cross-sectional views showing steps of a method for manufacturing the nonvolatile semiconductor memory device.

First, similarly to the first embodiment, as shown in FIG. 2, an element isolation region 12 is formed on a p-type silicon substrate 11 by trench isolation or the like. A partitioned element region is formed. A tunnel oxide film 13 is formed on the silicon substrate 11 in this element region. Then, as shown in FIG.
A polycrystalline silicon film having a thickness of about 100 to 200 nm is formed on the tunnel oxide film 13 by a CVD method. Then, the floating gate 14 is formed by patterning the polycrystalline silicon film by the RIE method.

Next, a method of forming the insulating film 21 between the floating gate and the control gate will be described with reference to an enlarged view of a portion indicated by 4 in FIG. 7A to 7D are enlarged cross-sectional views illustrating a method of forming the insulating film 21 formed on the floating gate 14.

As shown in FIG. 7A, the floating gate 14
A silicon nitride film 14B is formed thereon by nitriding. The silicon nitride film 14B is formed by performing a heat treatment (nitriding process) in a gas such as N2O, NO, or ammonia. At this time, the underlying tunnel oxide film 13
From the standpoint of suppressing the adverse effect on nitrogen, nitridation with N 2 O and NO, rather than ammonia, is more desirable. As a result, the natural oxide film existing on the polycrystalline silicon film (floating gate 14) is eliminated.

Further, as shown in FIG. 7B, on the silicon nitride film 14B formed on the surface of the floating gate 14,
A silicon oxide film 15A is formed to a thickness of 7 nm by the CVD method. In the formation of the silicon oxide film 15A, the first
Similarly to the embodiment, an HTO (High Temperature Oxide) oxide film is formed by decomposition of trichlorsilane. This film has a high insulating property and exhibits a leak characteristic close to that of a thermal oxide film, and thus is desirable as a film used for the silicon oxide film 15A. Other than these, there are an HTO oxide film made of dichlorosilane and a TEOS-based CVD oxide film, which generally have a larger leak current than an HTO oxide film made of trichlorosilane.
O-oxide films are most preferred.

Next, as shown in FIG. 7C, nitrogen is introduced near the interface between the silicon nitride film 14B and the silicon oxide film 15A to form a nitride layer 15B. Regarding the manufacturing conditions and the like at this time, the first type shown in FIG.
The description is omitted because it is the same as that of the embodiment.

Next, as shown in FIG. 7D, a 6-nm-thick silicon nitride film 15C is formed on the silicon oxide film 15A by low-pressure CVD. The manufacturing conditions and the like at this time are the same as those in the first embodiment shown in FIG.

As described above, as shown in FIG. 8, the insulating film 21 composed of the silicon oxide film 15A (including the nitride layer 15B) having a thickness of 7 nm, the silicon nitride film 15C having a thickness of 6 nm, and the silicon nitride film 14B. Is formed on the floating gate 14. In this case, when the insulating film 21 is converted into a thickness of an oxide film by a dielectric constant, the converted thickness is 10 nm.
This is because the nitride film has a dielectric constant approximately twice as large as that of the oxide film, and its thickness is reduced to half when converted to an oxide film. Further, the silicon nitride film 14B is
It is not considered because it is sufficiently thin compared to other films.
If the silicon oxide film 15A having a thickness of 7 nm exists, no leak current flows due to direct tunneling, and therefore, there is no problem in charge retention characteristics.

Next, as shown in FIG. 9, a polycrystalline silicon film having a thickness of about 200 to 400 nm is formed on the silicon nitride film 15C, that is, on the insulating film 21 by the CVD method. Subsequently, the control gate 16 and the floating gate 14 are formed by patterning the two-layered polycrystalline silicon film by the RIE method. After that, the nonvolatile semiconductor memory device is manufactured by a generally used manufacturing method.

By such a manufacturing process, the floating gate 1
4 and the effective oxide film thickness of the insulating film 21 between the control gate 16
A thin film can be formed while maintaining the charge retention characteristics and the withstand voltage. In particular, even when the thickness of the insulating film 21 is reduced, no problem occurs when electrons are emitted from the floating gate 14 to the silicon substrate 11.

In an ordinary nonvolatile semiconductor memory device, after an insulating film is formed on the floating gate, the insulating film, the floating gate material, and the tunnel oxide film in the transistor portion are removed. Thereafter, a step of performing oxidation to form a gate oxide film of the peripheral transistor is used. The insulating film is O
In the case of the NO film, since the silicon nitride film is present in the intermediate layer and its surface is hardly oxidized under the conditions when the gate oxide film of the peripheral transistor is formed, the peripheral circuit region can be oxidized using the ONO film as a mask material. . This second
Also in the structure of the insulating film 21 according to the embodiment, since the silicon nitride film 15C exists in the uppermost layer, the gate oxide film of the peripheral transistor is formed without affecting the insulating film of the floating gate in the memory cell portion. be able to.

In the semiconductor memory device of this embodiment, an electron trap is generated by nitriding the vicinity of the interface between the polycrystalline silicon film of the floating gate 14 and the silicon oxide film (CVD oxide film) 15A formed by CVD. , And exerts an electric field relaxation effect. However, a large amount of electron traps cannot be formed like the interface between the oxide film and the nitride film in the ONO film. Therefore, when a problem such as electric field concentration occurs at the edge portion of the floating gate 14, the edge 14A of the floating gate 14 is formed before the CVD oxide film 15A is formed on the floating gate 14 as shown in FIG. It is advisable to add a rounding step.

The electric field concentration at the edge of the floating gate 14 is
Assuming that the equivalent oxide film thickness of the insulating film 21 between the floating gate 14 and the control gate 16 is Tox, it can be calculated by the formula (Tox / In (1 + Tox / R)) × 1 / R. From this equation, when Tox = 12 nm, if the electric field concentration (how many times the electric field is applied to the plane portion at the edge) is to be suppressed within twice, the radius of curvature of the edge must be at least 5 nm or more. is there. Curvature 10
If it is set to nm, the electric field concentration can be suppressed to 1.5 times, and the curvature at 50 nm can be suppressed to 1.2 times or less. Actually, the reduction of the leak current by performing the normal nitriding treatment is in a range where the amount of current can be suppressed to, for example, 、. Therefore, it is desired to suppress the electric field concentration to about 1.2 times. If the curvature can be set to 50 nm or more, high insulation properties can be obtained.

In the step of rounding the edge, CDE (Ch
After the polycrystalline silicon film is oxidized by emical dry etching or high-temperature dilution oxidation, a method of removing and rounding the generated oxide film may be used. In addition, there are various methods such as rounding by processing in a hydrogen atmosphere at 950 ° C. to 1000 ° C. or using an appropriate wet processing. FIG. 10 is a sectional view of the nonvolatile semiconductor memory device at this time. The description of the other effects and functions that are the same as those of the first embodiment will be omitted.

As described above, according to the second embodiment, as compared with the first embodiment, the charge holding characteristic and the withstand voltage between the floating gate and the control gate are maintained more stably. A method for manufacturing a nonvolatile semiconductor memory device in which an insulating film can be thinned can be provided. Even when the thickness of the insulating film is reduced, no problem occurs when electrons are emitted from the floating gate to the silicon substrate. Also, in the step of forming the gate oxide film of the peripheral transistor after the formation of the insulating film, similarly to the conventional ONO film, only the peripheral portion is oxidized using the insulating film as a mask to form a gate oxide film of a desired thickness. Can be formed.

In the embodiment of the present invention, a CVD oxide film is used as a film for preventing a leak current. If the ONO film is not used as the insulating film between the floating gate and the control gate, electron leakage due to electric field concentration at the edge of the floating gate becomes a problem.
The interface with the oxide film is strongly nitrided. In addition, the edge of the floating gate is rounded as necessary. As a result, the leakage current when a high electric field is applied is reduced, and the electric field in the electric field concentration portion is reduced. Further, the nitride layer formed at the interface between the floating gate and the CVD oxide film also prevents bird's beak from entering in a post-oxidation step after the gate processing.

Further, in a general flash memory manufacturing process, a gate oxide film of a peripheral circuit may be formed using an insulating film between the floating gate and the control gate as an oxidation resistant mask. Further, when performing Fowler-Nordheim tunnel erasure (emission of electrons from the floating gate to the substrate) from the entire surface of the channel, the insulating film desirably suppresses current flowing from the control gate to the floating gate. Further, in order to prevent bird's beak from entering in a post-oxidation step after gate processing, a CVD
A silicon nitride film is formed by a method. As described above, as the insulating film between the floating gate and the control gate, a CVD oxide film whose interface with the floating gate is nitrided, and a silicon nitride film deposited by the CVD method on the CVD oxide film are formed.

[0066]

As described above, according to the present invention, the insulating film (equivalent oxide film thickness) between the floating gate and the control gate can be reduced while maintaining the charge retention characteristics and the withstand voltage. It is possible to provide a method for manufacturing a nonvolatile semiconductor memory device that can prevent a bird's beak from entering a floating gate and a control gate in a later necessary oxidation step to reduce the capacitance.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a nonvolatile semiconductor memory device manufactured by a manufacturing method according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of a first step showing a method for manufacturing a nonvolatile semiconductor memory device according to first and second embodiments of the present invention.

FIG. 3 is a sectional view of a second step in the method for manufacturing the nonvolatile semiconductor memory device according to the first and second embodiments.

FIGS. 4A to 4C are cross-sectional views illustrating a third step of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment. (D) is a sectional view showing the structure of another example of the insulating film.

FIG. 5 is a sectional view of a fourth step in the method for manufacturing the nonvolatile semiconductor memory device of the first embodiment.

FIG. 6 is a cross-sectional view showing a structure of a nonvolatile semiconductor memory device manufactured by a manufacturing method according to a modification of the first embodiment.

FIG. 7 is a sectional view of a third step in the method for manufacturing the nonvolatile semiconductor memory device of the second embodiment.

FIG. 8 is a sectional view of a fourth step in the method for manufacturing the nonvolatile semiconductor memory device of the second embodiment.

FIG. 9 is a sectional view showing a structure of a nonvolatile semiconductor memory device manufactured by a manufacturing method according to a second embodiment of the present invention;

FIG. 10 is a cross-sectional view illustrating a structure of a nonvolatile semiconductor memory device manufactured by a manufacturing method according to a modification of the second embodiment.

FIG. 11 is a sectional view showing the structure of a conventional nonvolatile semiconductor memory device.

FIG. 12 is a cross-sectional view showing a structure of an insulating film between a floating gate and a control gate in the nonvolatile semiconductor memory device.

FIG. 13 is a cross-sectional view showing a structure when a bird's beak occurs in the nonvolatile semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... p-type silicon substrate 12 ... element isolation region 13 ... tunnel oxide film 14 ... floating gate 15 ... insulating film 16 ... control gate 15A ... silicon oxide film 15B ... nitride layer 15C ... silicon nitride film 14A ... edge of floating gate 14B ... Silicon nitride film 21 insulating film 101 p-type silicon substrate 102 element isolation region 103 tunnel oxide film 104 floating gate 105 insulating film (ONO film) 105A oxide film 105B nitride film 105C oxide film 106 control Gate

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F001 AA25 AA43 AA63 AB08 AB09 AC02 AC06 AD12 AD53 AD60 AE08 AG21 AG23 AG30 5F083 EP02 EP23 EP55 EP76 EP77 ER02 ER05 ER09 ER14 ER19 GA22 GA30 JA04 NA01 PR15 PR21 PR33

Claims (10)

[Claims] A step of forming a gate insulating film on a semiconductor substrate; a step of forming a floating gate on the gate insulating film; and a step of forming a silicon oxide film on the floating gate by a CVD method. Near the interface between the floating gate and the silicon oxide film,
A step of introducing nitrogen to form a nitride layer; a step of forming a silicon nitride film on the silicon oxide film; and a step of forming a control gate on the silicon nitride film. A method for manufacturing a nonvolatile semiconductor memory device. A step of forming a gate insulating film on the semiconductor substrate; a step of forming a floating gate on the gate insulating film; and a step of forming a silicon oxide film on the floating gate by a CVD method. Near the interface between the floating gate and the silicon oxide film,
A step of introducing nitrogen to form a first nitride layer; a step of introducing nitrogen to form a second nitride layer on the surface of the silicon oxide film; and a control gate on the second nitride layer. Forming a non-volatile semiconductor memory device. A step of forming an element isolation region on the semiconductor substrate; a step of forming a tunnel oxide film on the semiconductor substrate in an element region defined by the element isolation region; and floating on the tunnel oxide film. A step of forming a gate; a step of forming a silicon oxide film on the floating gate by a CVD method; a step of forming a silicon oxide film near an interface between the floating gate and the silicon oxide film;
Forming a nitride layer by introducing nitrogen; forming a silicon nitride film on the silicon oxide film by a low-pressure CVD method; and forming a control gate on the silicon nitride film. A method for manufacturing a nonvolatile semiconductor memory device. 4. The method according to claim 1, further comprising, before the step of forming a silicon oxide film on the floating gate, a step of introducing nitrogen to the surface of the floating gate to form a nitride layer. 4. The method for manufacturing a nonvolatile semiconductor memory device according to any one of items 3 to 3. 5. The method according to claim 1, further comprising, before the step of forming a silicon oxide film on the floating gate, a step of rounding an edge present at a portion where the floating gate is separated with a curvature of 5 nm or more. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1. 6. The step of forming the silicon oxide film is performed by a reaction using trichlorosilane.
4. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the method is a step of forming a film (ture oxide) film. 7. The step of forming the silicon nitride film includes reducing the hydrogen content in the formed silicon nitride film to 1 × 10
^{4. The} method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the method is performed so as to be suppressed to ¹⁹ cm ^-3 or less. 8. The method according to claim 1, wherein the silicon nitride film has a thickness of 6 nm or less. 9. After forming the silicon oxide film, the nitride layer, and the silicon nitride film on the floating gate, the silicon oxide film, the nitride layer, the silicon nitride film, and the floating gate in a peripheral circuit region are formed. And removing the gate insulating film and oxidizing the gate of the peripheral circuit region using the silicon nitride film on the floating gate as an oxidation-resistant mask. 3. The method for manufacturing a nonvolatile semiconductor memory device according to 1. 10. The nonvolatile semiconductor memory device according to claim 1, wherein the step of forming the nitride layer is a step of performing a heat treatment in a gas of N 2 O or NO. Manufacturing method.