JP2001015603A - Adjusting the circuit operating speed - Google Patents

Abstract

(57) [Problem] To solve a timing violation of a circuit while suppressing an increase in power consumption. SOLUTION: After a placement and routing process of an integrated circuit, a cell library including cells having the same logic, different threshold voltages and different output transistor sizes is used, and two consecutive violating timings in the integrated circuit are violated. Attention is paid only to the cells, and the timing violation is eliminated by changing the threshold voltage and the output transistor size of these cells. By performing the above processing after the placement and routing processing, it is possible to use cells having a low threshold voltage only in a portion having a timing problem, thereby suppressing an increase in leakage current during standby. Also, by simultaneously changing the output transistor size of the cell, it is possible to easily select a combination with lower power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit in which a plurality of cells having different threshold values are integrated, and more particularly to a method for adjusting a circuit operation speed for adjusting the speed of an integrated circuit.

[0002]

2. Description of the Related Art Conventionally, a circuit is formed on an integrated circuit using a plurality of cells. For example, when a logic circuit is formed by a plurality of these cells, each cell distinguishes a high-level or low-level input voltage by a threshold and sets its output to a high or low level. In such an integrated circuit, when a block violating the timing is found, the threshold value of the cells constituting the block is reduced uniformly to increase the operation speed of the block.

Here, when the threshold voltage of a cell is lowered, when the input voltage slightly rises from a low level, it can be recognized as a high-level input signal, and its output can be made high. Thus, the operating speed of the cell can be increased.

When a block violating the timing violation described above is found, the operation speed of the block is increased by increasing the output transistor size of the cells constituting the block and increasing the driving force of the cells. Has also been done.

[0005]

However, when the threshold voltage of the cell is lowered, if the voltage slightly increases with respect to the low-level input voltage, the cell approaches the threshold value, and the cell is likely to be half-open. In addition, there has been a problem that the leakage current of the cell at the time of standby increases and power consumption increases.

In the above method of increasing the size of the output transistor, the leakage current of the cell during standby is small, but the power consumption of the cell during operation increases.
There is a problem that power consumption during operation increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a method of adjusting a circuit operating speed capable of eliminating a timing violation of a circuit while suppressing an increase in power consumption. It is to provide.

[0008]

In order to achieve the above object, a feature of the present invention is to provide a method of adjusting a circuit operating speed of a circuit formed by connecting a plurality of cells, the method comprising the steps of: Attention is paid to the first and second cells connected as described above, and the output transistor size of the first cell is changed, and the threshold value of the second cell driven by the first cell is changed. It is in.

A second aspect of the present invention is a method for adjusting a circuit operating speed of a circuit formed by connecting a plurality of cells, wherein a step of performing a wiring arrangement process of the circuit to calculate a wiring load capacitance; Attention is focused on the process of performing a timing analysis of the operation speed of the circuit based on the calculated wiring load capacitance, and the two consecutively connected first and second cells whose operation speed is a problem in the timing analysis. And the first
Change the output transistor size of the cell
A step of obtaining a combination of first and second cells obtained by changing a threshold value of the second cell driven by the first cell; and an optimum output transistor size among the obtained combinations. Selecting the first and second cells having a threshold value.

According to a third aspect of the present invention, there is provided a method for adjusting a circuit operating speed of a circuit formed by connecting a plurality of cells, wherein the step of arranging and wiring the circuit and the step of simulating each cell by simulation of the circuit. Analyzing the operation establishment P of the circuit, performing the timing analysis of the operation speed of the circuit, and performing the timing analysis on the two consecutively connected first and second cells whose operation speed is a problem. Focusing on changing the output transistor size of the first cell and the second cell driven by the first cell.
Of the first and second cell combinations obtained by changing the threshold value of the cell, and the power consumption W = (P × power consumption during cell operation) + 消費(1−P) × selecting the first and second cells having the optimum output transistor size and the optimum threshold value in consideration of the power consumption の due to the leakage current at the time of standby of the cell.

A feature of the invention according to claim 4 is that the combination of the first and second cells obtained by changing the size of the output transistor and the threshold value is a cell having the same logic, different threshold voltage and different output transistor size. To select from a cell library consisting of:

The circuit formed by connecting the plurality of cells according to the invention of claim 5 is an integrated circuit.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of an integrated circuit to which the circuit operation speed adjusting method of the present invention is applied. The integrated circuit 1 integrates a circuit configured by connecting a plurality of cells C.

FIG. 2 is a circuit diagram showing, in the circuit shown in FIG. 1, cells Cd and Cr of interest in order to increase the operation speed in the net N violating the timing.

Next, a method for increasing the speed of the integrated circuit according to the present embodiment will be described.

(1) A library including cells having the same logic and different threshold voltages and cells having different output transistor sizes is prepared.

(2) A process of arranging and wiring the integrated circuit is performed to calculate a wiring load capacitance.

(3) A timing analysis is performed based on the result of (2).

(4) Based on the result of (3), a wiring that violates the timing is extracted.

(5) The following processing is performed on the net N extracted in (4).

(5.1) The delay value Ta and the power consumption P when the output transistor size of the cell Cd driving the net N and the threshold value of the cell Cr driven by the net N are changed
Is created as shown in FIG. here,
The delay values for eliminating the timing violation are Tr and Ta (here, the delay time realized by the combination of the output transistor size of Cd and the threshold voltage of Cr is Ta).

(5.2) From the library obtained in (5.1), a library with the smallest power consumption P is selected from combinations of thresholds and output transistor sizes satisfying Ta ≦ Tr.

(5.3) The cell is changed according to the combination selected in (5.2).

Here, a method of increasing the speed of the net N will be described in more detail with reference to FIG.

FIG. 3 shows three types of threshold voltages (L-Vth).
<(M−Vth) <(H−Vth) and three types of output transistor sizes (S−Tr) <(M−Tr) <(LT)
This is an example when a cell library having r) is used.

The combination in the horizontal direction of this library is the case where the threshold value is changed with the output transistor size being the same, and the combination in the vertical direction is the case where the output transistor size is changed with the threshold value kept constant. Are changed at the same time.

As the size of the output transistor increases, the rise of the voltage with respect to time becomes steeper. If the threshold value is constant, the speed of the cell increases as the size of the output transistor increases. Also, the lower the threshold, the slower the cell speed.

The output transistor size of the cell Cd driving the net N shown in FIG.
The delay time Ta based on the combination of the threshold voltages r is as shown in FIG.

For example, when a timing violation is committed in the initial state designed by the combination of (M-Vth, M-Tr), in the example of FIG.
th, S-Tr), (L-Vth, M-Tr), (L-
Vth, L-Tr), (M-Vth, L-Tr), (H
-Vth, L-Tr). A low power consumption circuit can be realized by selecting a combination that consumes the least power from these combinations.

In the example shown in FIG. 4, the combination of the threshold value and the output transistor size is changed to the combination of (L-Vth, L-Tr). This is the result of the selection with priority given to speed. In this case, the setting of the net N is changed as shown in FIG. 4, the output transistor size of the cell Cd is large, and the threshold value of the cell Cr is low. However, if the speed does not need to be so high, (M-Vth, L-
Tr) or (H-Vth, L-Tr) can be selected, and a change to suppress power consumption is also possible.

Generally, when the threshold voltage is changed, no change in the cell size occurs. However, when the output transistor size is changed, the physical size of the cell itself also changes. If the cell size changes, it is not always possible to place the cell after the change at the same coordinates.
It is necessary to search for possible coordinates and recalculate the wiring load capacitance.

According to this embodiment, a cell library composed of cells having the same logic, different threshold voltages and different output transistor sizes is used, and only a pair of cells Cd and Cr constituting a net violating the timing are used. On the other hand, by eliminating the timing violation by changing the threshold voltage of the cell and the size of the output transistor, the combination in the diagonal direction in FIG. 3 becomes possible, and the number of combinations can be increased. Therefore, a combination that consumes less power can be selected, and the speed of the integrated circuit can be increased without increasing power consumption.

Further, by performing the above-described processing for changing the threshold value and the output transistor size after the placement and routing processing, cells having a low threshold voltage can be used only in a portion having a timing problem, and the integrated circuit can be used. As a whole, it is possible to suppress an increase in leakage current during standby.

FIG. 5 is a flowchart showing a second embodiment of the circuit operation speed adjusting method according to the present invention.

The circuit speed adjusting method of the present embodiment includes an integrated circuit arrangement / wiring process 501, a circuit simulation 502, a timing analysis 503, and a cell setting process 504. Using a cell library consisting of cells with the same logic, different threshold voltages and different output transistor sizes,
For a portion where a timing violation is committed, a cell using a transistor having a threshold voltage lower than the standard value and a cell using an output transistor having a size larger than the standard value are used.

At this time, since the low threshold voltage cell has a higher leakage current during standby than the standard threshold voltage cell, using the low threshold voltage cell for the portion where the operation of the cell is low is not advantageous in terms of power consumption. From disadvantages. Therefore, a cell using an output transistor larger than the standard size is used for a circuit module with a low probability of operation, and a cell using a transistor with a threshold voltage lower than the standard value is used for a circuit module with a high probability of operation. .

The operation of each circuit module can be established by performing a circuit simulation in step 502.

Next, the processing procedure of the method of adjusting the operating speed of the integrated circuit will be described.

First, in step 501 shown in FIG.
An arrangement and wiring process of the integrated circuit is performed, and in step 502, the operation establishment is analyzed by circuit simulation. Further, in step 503, a timing violation is extracted by timing analysis of the integrated circuit, and in step 504, a cell replacement process is performed.

Here, during the cell replacement process, the power consumption during operation and the power consumption during standby of both the low threshold voltage cell and the cell having a large output transistor size are compared, and a replacement candidate with lower power consumption is selected. .

For this purpose, a cell library in which both the power consumption during operation and the power consumption during standby are registered is prepared, and the power consumption is obtained by the following formula. Assuming that the operation probability (switching probability) of the cell is P, the power consumption W
Is expressed as follows.

Power consumption W = P * Power consumption during operation + (1−P) * Power consumption due to leakage current during standby ... (1) Pay attention to power consumption W from equation (1) so as to decrease. Change the threshold value of the cell or the size of the output transistor. That is, if the same operation speed is to be realized, the replacement that increases the output transistor size is advantageous in terms of power consumption where the operation probability is low, and the replacement that lowers the cell threshold is where the operation probability is high. This is advantageous in power consumption.

Since the change in the threshold voltage of the cell does not affect the size of the cell, a high-speed operation product and a high-speed operation can be achieved by replacing each cell with the same logic cell having a different threshold voltage for an already designed integrated circuit. A low-speed operation / low power consumption product can be easily manufactured by the procedure shown in FIG.

After the placement and routing process in step 601, each cell is manufactured with standard threshold cells to produce a general product.

After the placement and routing processing in step 601, the circuit simulation in step 602 and the timing analysis of the circuit in step 603 are performed. In step 604, a cell replacement processing for lowering the cell threshold and increasing the circuit speed is performed. Operational products can be manufactured.

On the other hand, after performing the circuit timing analysis in step 603, in step 604, a cell replacement process for increasing the cell threshold and reducing the circuit power consumption is performed.
A low-speed operation and low power consumption product can be manufactured.

According to the present embodiment, when adjusting the speed of the circuit constituting the integrated circuit, the desired speed can be achieved by changing the threshold voltage of the cell based on the equation (1). By arbitrarily changing the circuit speed and power consumption, products having various characteristics can be manufactured easily and inexpensively from the same wafer.

[0048]

As described above in detail, according to the first aspect of the present invention, the combination of the cell speed and the power consumption is achieved by simultaneously changing the threshold value and the output transistor size of two consecutive cells. Therefore, it is possible to easily obtain a combination capable of suppressing a timing violation of a circuit while suppressing an increase in power consumption.

According to the second aspect of the present invention, since the combination of the cell speed and the power consumption is increased by simultaneously changing the threshold value and the output transistor size of two consecutive cells, the target speed is cleared. In addition, a combination with low power consumption can be easily selected, and increase in power consumption can be suppressed and a timing violation of a circuit can be eliminated. In addition, since the above-mentioned change processing is performed after the circuit arrangement and wiring processing, it is possible to eliminate the timing violation only in the part where the timing is problematic,
An increase in power consumption of the entire circuit can be suppressed.

According to the third aspect of the present invention, it is possible to quantitatively and strictly manage the increase in power consumption when changing the cell threshold value and the output transistor size.

According to the fourth aspect of the present invention, by selecting a combination having an appropriate cell threshold value and an output transistor size from the cell library, it is possible to easily and quickly adjust the speed of the circuit without increasing power consumption. Can be done on time.

According to the fifth aspect of the present invention, since the applied circuit is an integrated circuit, the usefulness of the effect that the speed can be adjusted without increasing the power consumption can be greatly enhanced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an integrated circuit to which a circuit operation speed adjusting method of the present invention is applied.

FIG. 2 is a circuit diagram showing cells of interest Cd and Cr for adjusting an operation speed in the circuit shown in FIG. 1;

FIG. 3 is a diagram illustrating a characteristic example of a cell library having three types of threshold voltages and three types of output transistor sizes.

FIG. 4 is a circuit diagram showing an example of a cell in which the speed is adjusted by changing a threshold voltage and an output transistor size.

FIG. 5 is a flowchart showing a second embodiment of the circuit operation speed adjusting method according to the present invention.

FIG. 6 is a flowchart showing a procedure for manufacturing products having different performances by changing the speed and power consumption of an integrated circuit on a common wafer.

[Explanation of symbols]

 1 Integrated circuit C, Cd, Cr cell

Claims (5)

[Claims] 1. A method for adjusting a circuit operating speed of a circuit formed by connecting a plurality of cells, wherein attention is paid to two consecutively connected first and second cells.
A method of adjusting a circuit operation speed, comprising changing an output transistor size of the first cell and changing a threshold value of the second cell driven by the first cell. 2. A method for adjusting a circuit operation speed of a circuit formed by connecting a plurality of cells, wherein: a step of performing wiring processing of the circuit to calculate a wiring load capacitance; Performing a timing analysis of the operation speed of the circuit based on the following; focusing on two consecutively connected first and second cells having an operation speed problem in the timing analysis; Changing the output transistor size of the first cell and changing the threshold value of the second cell driven by the first cell to obtain a combination of the first and second cells. Selecting the first and second cells having the optimum output transistor size and threshold value from the combinations described above. 3. A method for adjusting a circuit operation speed of a circuit formed by connecting a plurality of cells, wherein a step of arranging and wiring the circuit and a step of establishing an operation of each cell by simulating the circuit.
Analyzing the operation speed of the circuit; performing a timing analysis of the operation speed of the circuit; and focusing on two consecutively connected first and second cells whose operation speed is a problem in the timing analysis. Obtaining a combination of first and second cells obtained by changing the output transistor size of the first cell and changing the threshold value of the second cell driven by the first cell. From the obtained combinations, the power consumption W = (P
× power consumption during cell operation) + {(1−P) × power consumption due to leakage current during standby of cell}
Selecting a first cell and a second cell having an optimum output transistor size and an optimum threshold value. 4. A combination of the first and second cells obtained by changing the output transistor size and the threshold value is selected from a cell library including cells having the same logic, different threshold voltages, and different output transistor sizes. The method for adjusting a circuit operation speed according to any one of claims 1 to 3, wherein the method is selected. 5. The circuit operating speed adjusting method according to claim 1, wherein the circuit formed by connecting the plurality of cells is an integrated circuit.