JP2001015599A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JP2001015599A JP2001015599A JP11186340A JP18634099A JP2001015599A JP 2001015599 A JP2001015599 A JP 2001015599A JP 11186340 A JP11186340 A JP 11186340A JP 18634099 A JP18634099 A JP 18634099A JP 2001015599 A JP2001015599 A JP 2001015599A
- Authority
- JP
- Japan
- Prior art keywords
- film
- width
- tin
- barrier layer
- alcu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 230000004888 barrier function Effects 0.000 claims description 31
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 229910016570 AlCu Inorganic materials 0.000 abstract description 30
- 238000001020 plasma etching Methods 0.000 abstract description 7
- 238000001312 dry etching Methods 0.000 abstract description 2
- 239000005368 silicate glass Substances 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 48
- 239000010410 layer Substances 0.000 description 15
- 239000011229 interlayer Substances 0.000 description 11
- 229910052731 fluorine Inorganic materials 0.000 description 7
- 239000011737 fluorine Substances 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 6
- 239000000460 chlorine Substances 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 101150016011 RR11 gene Proteins 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 150000002221 fluorine Chemical class 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に係わり、特に、アルミニウム配線（以下、
Ａｌ配線と称す）の形状及びその形状を実現するための
半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an aluminum wiring (hereinafter, referred to as an aluminum wiring).
(Referred to as Al wiring) and a semiconductor device for realizing the shape and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】例えば半導体記憶装置等の半導体装置に
は、Ａｌ配線が使用されている。図８乃至図１２は、従
来のＡｌ配線の製造工程を示している。2. Description of the Related Art For example, Al wiring is used in semiconductor devices such as semiconductor memory devices. 8 to 12 show a manufacturing process of a conventional Al wiring.
【０００３】まず、図８に示すように、シリコン基板１
１上に層間絶縁膜１２が形成される。次に、例えばスパ
ッタリング法により、この層間絶縁膜１２上に第１のバ
リア膜として例えばＴｉ／ＴｉＮ膜（ＴｉとＴｉＮから
なる積層膜）１３が形成され、この第１のＴｉ／ＴｉＮ
膜１３上に金属膜として例えばＡｌＣｕ膜１４が形成さ
れる。このＡｌＣｕ膜１４上に第２のバリア膜として例
えばＴｉ／ＴｉＮ膜１５が形成される。ここで、Ｔｉ／
ＴｉＮ膜１３、１４及びＡｌＣｕ膜１５の形成はスパッ
タリング法に限定されず、例えばＣＶＤ（Chemical Vap
or Deposition）法でもよい。[0003] First, as shown in FIG.
An interlayer insulating film 12 is formed on 1. Next, for example, a Ti / TiN film (laminated film composed of Ti and TiN) 13 is formed as a first barrier film on the interlayer insulating film 12 by, for example, a sputtering method, and the first Ti / TiN film is formed.
For example, an AlCu film 14 is formed on the film 13 as a metal film. On this AlCu film 14, for example, a Ti / TiN film 15 is formed as a second barrier film. Where Ti /
The formation of the TiN films 13 and 14 and the AlCu film 15 is not limited to the sputtering method.
or Deposition) method.
【０００４】次に、図９に示すように、第２のＴｉ／Ｔ
ｉＮ膜１５上に選択的にレジスト膜１６が形成される。
このレジスト膜１６をマスクとして、ＲＩＥ（Reactive
IonEtching）により、第２のＴｉ／ＴｉＮ膜１５、Ａ
ｌＣｕ膜１４、第１のＴｉ／ＴｉＮ膜１３が除去され
る。Next, as shown in FIG. 9, a second Ti / T
A resist film 16 is selectively formed on the iN film 15.
Using this resist film 16 as a mask, RIE (Reactive
IonEtching), the second Ti / TiN film 15, A
The lCu film 14 and the first Ti / TiN film 13 are removed.
【０００５】図１０に、図９のＢ部の拡大図を示す。上
述したＲＩＥでは、ＡｌＣｕ膜１４と第１のＴｉ／Ｔｉ
Ｎ膜１３を、同一のエッチングガス（例えばＢｌＣ3と
Ｃｌ2の混合ガス）で一括してエッチングしている。し
かし、ＡｌＣｕ膜１４と第１のＴｉ／ＴｉＮ膜１３で
は、エッチングレートに若干の違いがある。このため、
図１０に示すように、結果的にＴｉ／ＴｉＮ膜１５の幅
がＡｌＣｕ膜１４の幅より広い形状となる。つまり、Ａ
ｌＣｕ膜１４の一方の側面は、Ｔｉ／ＴｉＮ膜１５の幅
よりも例えば２０乃至３０ｎｍ後退している。その後、
レジスト膜１６が除去され、Ａｌ配線が形成される。FIG. 10 is an enlarged view of a portion B in FIG. In the above-described RIE, the AlCu film 14 and the first Ti / Ti
The N film 13 is collectively etched with the same etching gas (for example, a mixed gas of BIC 3 and Cl 2 ). However, there is a slight difference in the etching rate between the AlCu film 14 and the first Ti / TiN film 13. For this reason,
As shown in FIG. 10, as a result, the width of the Ti / TiN film 15 becomes wider than the width of the AlCu film 14. That is, A
One side surface of the lCu film 14 is recessed, for example, by 20 to 30 nm from the width of the Ti / TiN film 15. afterwards,
The resist film 16 is removed, and an Al wiring is formed.
【０００６】次に、このようなＡｌ配線上に層間膜が形
成される。この層間膜として、例えばＦ（フッ素）を含
むＦＳＧ（F doped Silicate Glass）膜を用いた場合、
成膜ガス中のフッ素が第１のＴｉ／ＴｉＮ膜１３、Ａｌ
Ｃｕ膜１４、第２のＴｉ／ＴｉＮ膜１５をアタッキング
する。従って、このフッ素のアタッキングを防止するた
め、第１のＴｉ／ＴｉＮ膜１３、ＡｌＣｕ膜１４、第２
のＴｉ／ＴｉＮ膜１５上を例えばＵＳＧ（Undoped Sili
cate Glass）膜で保護する必要がある。Next, an interlayer film is formed on such an Al wiring. For example, when an FSG (F doped Silicate Glass) film containing F (fluorine) is used as the interlayer film,
Fluorine in the film forming gas contains the first Ti / TiN film 13, Al
The Cu film 14 and the second Ti / TiN film 15 are attacked. Therefore, in order to prevent this fluorine attack, the first Ti / TiN film 13, the AlCu film 14, the second
For example, USG (Undoped Silicon) is formed on the Ti / TiN film 15 of FIG.
cate Glass) must be protected with a membrane.
【０００７】つまり、図１０に示す工程後、図１１に示
すように、全面に膜厚が例えば１００ｎｍのＵＳＧ膜１
７が形成される。その後、図１２に示すように、ＵＳＧ
膜１７上に膜厚が例えば１５００ｎｍのＦＳＧ膜１８が
形成される。That is, after the step shown in FIG. 10, as shown in FIG. 11, the USG film 1 having a thickness of, for example, 100 nm is formed on the entire surface.
7 is formed. Thereafter, as shown in FIG.
An FSG film 18 having a thickness of, for example, 1500 nm is formed on the film 17.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、上記従
来の製造方法では、図１０に示すように、Ｔｉ／ＴｉＮ
膜１５がＡｌＣｕ膜１４の側面より横に突き出た形状に
なっている。このため、Ａｌ配線上にＵＳＧ膜１７とＦ
ＳＧ膜１８の積層からなる層間膜を形成する場合、以下
に示す問題が生じる。However, in the above-mentioned conventional manufacturing method, as shown in FIG.
The film 15 has a shape protruding laterally from the side surface of the AlCu film 14. For this reason, the USG film 17 and the F
When an interlayer film composed of a stack of the SG films 18 is formed, the following problems occur.
【０００９】つまり、図１１に示すように、Ａｌ配線上
にＵＳＧ膜１７を形成した場合、層間絶縁膜１２上、Ｔ
ｉ／ＴｉＮ膜１５上、及びＡｌＣｕ膜１４側面の下部に
ＵＳＧ膜１７は形成されるが、ＡｌＣｕ膜１４側面の上
部にはＵＳＧ膜１７が十分に形成されない。このため、
ＡｌＣｕ膜１４側面の上部にボイド（隙間）３０が生じ
る。従って、Ｔｉ／ＴｉＮ膜１５のＡｌＣｕ膜１４の側
面より突き出た下面３１は、ＵＳＧ膜１７で保護されず
露出された状態となる。That is, as shown in FIG. 11, when a USG film 17 is formed on an Al wiring,
The USG film 17 is formed on the i / TiN film 15 and below the side surface of the AlCu film 14, but the USG film 17 is not sufficiently formed above the side surface of the AlCu film 14. For this reason,
A void (gap) 30 is formed on the upper portion of the side surface of the AlCu film 14. Therefore, the lower surface 31 of the Ti / TiN film 15 protruding from the side surface of the AlCu film 14 is exposed without being protected by the USG film 17.
【００１０】その後、図１２に示すように、ＵＳＧ膜１
７上にＦＳＧ膜１８が形成された場合、このＦＳＧ膜１
８中のフッ素が、ボイド３０の部分からＴｉ／ＴｉＮ膜
１５の突き出た下面３１を極端にエッチングする。これ
によって、Ｔｉ／ＴｉＮ膜１５が細り、結果的に配線の
高抵抗化及び信頼性の低下を招くという問題が生じる。[0010] Thereafter, as shown in FIG.
7, an FSG film 18 is formed on the FSG film 1.
The fluorine in 8 extremely etches the lower surface 31 of the Ti / TiN film 15 projecting from the void 30 portion. As a result, there is a problem that the Ti / TiN film 15 becomes thin, resulting in an increase in the resistance of the wiring and a decrease in reliability.
【００１１】本発明は上記課題を解決するためになされ
たものであり、その目的とするところは、配線抵抗の上
昇及び信頼性の低下を抑制することが可能な半導体装置
及びその製造方法を提供することにある。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device capable of suppressing an increase in wiring resistance and a decrease in reliability, and a method of manufacturing the same. Is to do.
【００１２】[0012]
【課題を解決するための手段】本発明は、前記目的を達
成するために以下に示す手段を用いている。The present invention uses the following means to achieve the above object.
【００１３】本発明の半導体装置は、半導体基板上に形
成された絶縁膜と、前記絶縁膜上に形成された第１のバ
リア層と、前記第１のバリア層上に形成され、前記第１
のバリア層の幅より狭い金属膜と、前記金属膜上に形成
され、前記金属膜の幅より狭い第２のバリア層とを具備
する。A semiconductor device according to the present invention includes an insulating film formed on a semiconductor substrate, a first barrier layer formed on the insulating film, and a first barrier layer formed on the first barrier layer.
And a second barrier layer formed on the metal film and having a width smaller than the width of the metal film.
【００１４】前記第２のバリア層の一方の側面は、前記
金属膜の幅の５乃至２０％の幅だけ前記金属膜の側面よ
り内側に位置している。One side surface of the second barrier layer is located inside the side surface of the metal film by a width of 5 to 20% of the width of the metal film.
【００１５】本発明の半導体装置の製造方法は、半導体
基板上に絶縁膜を形成する工程と、前記絶縁膜上に第１
のバリア層を形成する工程と、前記第１のバリア層上に
金属膜を形成する工程と、前記金属膜上に第２のバリア
層を形成する工程と、前記第２のバリア層上に選択的に
レジスト膜を形成する工程と、前記レジスト膜をマスク
として、前記第２のバリア層を除去する第１の除去工程
と、前記第２のバリア層の両側面を、前記レジスト膜の
幅よりも狭く除去する第２の除去工程と、前記レジスト
膜をマスクとして、前記金属膜及び前記第１のバリア層
を除去する第３の除去工程とを含む。According to a method of manufacturing a semiconductor device of the present invention, a step of forming an insulating film on a semiconductor substrate and a step of forming a first
Forming a barrier layer, forming a metal film on the first barrier layer, forming a second barrier layer on the metal film, and selecting on the second barrier layer. Forming a resist film, a first removing step of removing the second barrier layer using the resist film as a mask, and removing both side surfaces of the second barrier layer from the width of the resist film. And a third removing step of removing the metal film and the first barrier layer by using the resist film as a mask.
【００１６】前記第２の除去工程において、前記第２の
バリア層の一方の側面は、前記第３の除去工程後の前記
金属膜の幅の５乃至２０％の幅だけ前記金属膜の側面よ
り内側に位置するように除去する。In the second removing step, one side surface of the second barrier layer is separated from the side surface of the metal film by a width of 5 to 20% of a width of the metal film after the third removing step. Remove so that it is located inside.
【００１７】前記第２の除去工程は、Ｃｌ2とＡｒとＣ
Ｆ4を含むガスを用いてＣＤＥにより行う。In the second removing step, Cl 2 , Ar and C are used.
This is performed by CDE using a gas containing F 4 .
【００１８】[0018]
【発明の実施の形態】本発明の実施の形態を以下に図面
を参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１９】まず、図１に示すように、シリコン基板１
１上に層間絶縁膜１２が形成される。次に、例えばスパ
ッタリング法により、この層間絶縁膜１２上に第１のバ
リア膜として例えばＴｉ／ＴｉＮ膜１３が形成され、こ
の第１のＴｉ／ＴｉＮ膜１３上に金属膜として例えばＡ
ｌＣｕ膜１４が形成される。このＡｌＣｕ膜１４上に第
２のバリア膜として例えばＴｉ／ＴｉＮ膜１５が形成さ
れる。ここで、Ｔｉ／ＴｉＮ膜１３、１４及びＡｌＣｕ
膜１５の形成はスパッタリング法に限定されず、例えば
ＣＶＤ法でもよい。First, as shown in FIG.
An interlayer insulating film 12 is formed on 1. Next, for example, a Ti / TiN film 13 is formed as a first barrier film on the interlayer insulating film 12 by, for example, a sputtering method, and a metal film such as A is formed on the first Ti / TiN film 13.
An lCu film 14 is formed. On this AlCu film 14, for example, a Ti / TiN film 15 is formed as a second barrier film. Here, the Ti / TiN films 13, 14 and AlCu
The formation of the film 15 is not limited to the sputtering method, and may be, for example, a CVD method.
【００２０】次に、図２に示すように、第２のＴｉ／Ｔ
ｉＮ膜１５上に選択的にレジスト膜１６が形成される。
このレジスト膜１６をマスクとして、ＲＩＥにより、第
２のＴｉ／ＴｉＮ膜１５が除去される。Next, as shown in FIG. 2, the second Ti / T
A resist film 16 is selectively formed on the iN film 15.
Using this resist film 16 as a mask, the second Ti / TiN film 15 is removed by RIE.
【００２１】次に、図２のＡ部に注目して説明する。図
３に示すように、Ｃｌ2（塩素）とＡｒ（アルゴン）と
ＣＦ4を含むガスを用いてＣＤＥ（Chemical Dry Etchin
g）が行われ、第２のＴｉ／ＴｉＮ膜１５の両側面が除
去される。ここで、レジスト膜１６の幅が例えば３２０
ｎｍの場合、第２のＴｉ／ＴｉＮ膜１５の一方の側面
は、例えば２０ｎｍ乃至５０ｎｍ後退されればよく、こ
の場合は例えば３５ｎｍ後退される。Next, a description will be given focusing on the portion A in FIG. As shown in FIG. 3, CDE (Chemical Dry Etching) is performed using a gas containing Cl 2 (chlorine), Ar (argon) and CF 4.
g) is performed, and both side surfaces of the second Ti / TiN film 15 are removed. Here, the width of the resist film 16 is, for example, 320
In the case of nm, one side surface of the second Ti / TiN film 15 may be recessed, for example, by 20 nm to 50 nm, and in this case, it is recessed, for example, by 35 nm.
【００２２】次に、図４に示すように、レジスト膜１６
をマスクとして、ＲＩＥによりＡｌＣｕ膜１４、第１の
Ｔｉ／ＴｉＮ膜１３が除去される。この結果、Ｔｉ／Ｔ
ｉＮ膜１３はほぼレジスト膜１６と同等の幅となり、Ａ
ｌＣｕ膜１４はＴｉ／ＴｉＮ膜１３より狭くなり、Ｔｉ
／ＴｉＮ膜１５の幅はＡｌＣｕ膜１４の幅より狭くな
る。尚、Ｔｉ／ＴｉＮ膜１５の一方の側面は、ＡｌＣｕ
膜１４の幅の例えば５％乃至２０％の幅だけＡｌＣｕ膜
１４の側面より内側に位置している。この後、レジスト
膜１６が除去され、Ａｌ配線が形成される。Next, as shown in FIG.
Using Al as a mask, the AlCu film 14 and the first Ti / TiN film 13 are removed by RIE. As a result, Ti / T
The iN film 13 has a width substantially equal to that of the resist film 16,
The lCu film 14 is narrower than the Ti / TiN film 13 and
The width of the / TiN film 15 is smaller than the width of the AlCu film 14. Note that one side surface of the Ti / TiN film 15 is made of AlCu.
It is located inside the side surface of the AlCu film 14 by, for example, 5% to 20% of the width of the film 14. Thereafter, the resist film 16 is removed, and an Al wiring is formed.
【００２３】次に、図５に示すように、全面に膜厚が例
えば１００ｎｍのＵＳＧ膜１７が形成され、連続して、
このＵＳＧ膜１７上に膜厚が例えば１５００ｎｍのＦＳ
Ｇ膜１８が形成される。ここで、ＵＳＧ膜１７はＦＳＧ
膜１８中のフッ素が、第１のＴｉ／ＴｉＮ膜１３、Ａｌ
Ｃｕ膜１４、第２のＴｉ／ＴｉＮ膜１５をエッチングす
ることを防止するための膜である。また、Ａｌ配線を形
成する膜の幅が上層程狭いため、Ａｌ配線の全面がＵＳ
Ｇ膜１７により覆われる。Next, as shown in FIG. 5, a USG film 17 having a thickness of, for example, 100 nm is formed on the entire surface.
An FS having a thickness of, for example, 1500 nm is formed on the USG film 17.
A G film 18 is formed. Here, the USG film 17 is FSG
Fluorine in the film 18 becomes the first Ti / TiN film 13
This is a film for preventing the Cu film 14 and the second Ti / TiN film 15 from being etched. Further, since the width of the film forming the Al wiring is narrower toward the upper layer, the entire surface of the Al wiring
It is covered with the G film 17.
【００２４】次に、図６に示すように、ＣＭＰ法によ
り、ＦＳＧ膜１８が平坦化され、このＦＳＧ膜１８上
に、フッ素をブロックするためにＴＥＯＳ膜１９が形成
される。その後、例えば４００℃乃至４５０℃の温度で
アニールが行われる。Next, as shown in FIG. 6, the FSG film 18 is flattened by the CMP method, and a TEOS film 19 is formed on the FSG film 18 to block fluorine. After that, annealing is performed at a temperature of, for example, 400 ° C. to 450 ° C.
【００２５】次に、ＴＥＯＳ膜１９上に選択的にレジス
ト膜（図示せず）が形成される。このレジスト膜をマス
クとして、ＴＥＯＳ膜１９、ＦＳＧ膜１８、ＵＳＧ膜１
７が除去され、ヴィア（Ｖｉａ）２１が形成される。Next, a resist film (not shown) is selectively formed on the TEOS film 19. Using this resist film as a mask, the TEOS film 19, the FSG film 18, the USG film 1
7 is removed, and a via 21 is formed.
【００２６】次に、全面にＷ（タングステン）２２が形
成され、Ｖｉａ２１が埋め込まれる。その後、ＣＭＰ法
によりタングステン２２が平坦化され、ＴＥＯＳ膜１９
の表面が露出される。Next, W (tungsten) 22 is formed on the entire surface, and Via 21 is embedded. Thereafter, the tungsten 22 is planarized by the CMP method, and the TEOS film 19 is formed.
Surface is exposed.
【００２７】次に、例えばスパッタリング法により、全
面にＴｉ／ＴｉＮ膜２３が形成され、このＴｉ／ＴｉＮ
膜２３上にＡｌＣｕ膜２４が形成される。このＡｌＣｕ
膜２４上にＴｉ／ＴｉＮ膜２５が形成される。Next, a Ti / TiN film 23 is formed on the entire surface by, for example, a sputtering method.
An AlCu film 24 is formed on the film 23. This AlCu
A Ti / TiN film 25 is formed on the film 24.
【００２８】この後は、上記工程と同様に行われ、例え
ば図６に示すような３層からなる多層配線構造の半導体
装置が形成される。Thereafter, the same processes as those described above are performed, and a semiconductor device having a multilayer wiring structure composed of three layers as shown in FIG. 6, for example, is formed.
【００２９】上記本発明の実施形態によれば、ＡｌＣｕ
膜１４の幅がＴｉ／ＴｉＮ膜１３の幅より狭く、Ｔｉ／
ＴｉＮ膜１５の幅がＡｌＣｕ膜１４の幅より狭い構造と
なっている。従って、Ｔｉ／ＴｉＮ膜１５上にＵＳＧ膜
１７を形成する際、ＡｌＣｕ膜１４上部の側面にボイド
が発生することを防止できる。このため、ＵＳＧ膜１７
上に形成する層間膜の材料にＦＳＧ膜１８を選んでもフ
ッ素のアタッキングによるＴｉ／ＴｉＮ膜１５のエッチ
ングを防止できる。従って、Ｔｉ／ＴｉＮ膜１５の細り
による配線抵抗の上昇及び信頼性の低下を抑制すること
ができる。According to the above embodiment of the present invention, AlCu
The width of the film 14 is smaller than the width of the Ti / TiN film 13 and
The structure is such that the width of the TiN film 15 is smaller than the width of the AlCu film 14. Therefore, when the USG film 17 is formed on the Ti / TiN film 15, it is possible to prevent the occurrence of voids on the side surface above the AlCu film 14. Therefore, the USG film 17
Even if the FSG film 18 is selected as the material of the interlayer film formed thereon, the etching of the Ti / TiN film 15 due to the attack of fluorine can be prevented. Therefore, an increase in wiring resistance and a decrease in reliability due to the thinning of the Ti / TiN film 15 can be suppressed.
【００３０】また、ＣＤＥによりＴｉ／ＴｉＮ膜１５の
両側面を除去する際に、Ｃｌ2（塩素）とＡｒ（アルゴ
ン）とＣＦ4を含むガスを用いた。このようなガスを用
いれば、Ｔｉ／ＴｉＮ膜１５のみが除去される。従っ
て、ＡｌＣｕ膜１４の上端部は除去されないため、Ａｌ
Ｃｕ膜１４の形状劣化や配線抵抗の増大を抑制すること
ができる。In removing both side surfaces of the Ti / TiN film 15 by CDE, a gas containing Cl 2 (chlorine), Ar (argon) and CF 4 was used. If such a gas is used, only the Ti / TiN film 15 is removed. Therefore, since the upper end of the AlCu film 14 is not removed,
Deterioration of the shape of the Cu film 14 and increase in wiring resistance can be suppressed.
【００３１】また、図７に示すように、ＦＳＧ膜の代わ
りにフッ素を含まない層間膜１８ａとして例えばＵＳＧ
膜やＴＥＯＳ膜を用いた場合も、本発明の実施形態によ
れば、Ｔｉ／ＴｉＮ膜１５ａ、１５ｂ、１５ｃの幅を減
少できる。つまり、Ｔｉ／ＴｉＮ膜１５ａと１５ｂの距
離が長くなるとともに、Ｔｉ／ＴｉＮ膜１５ａ、１５
ｂ、１５ｃの表面積が減少する。このため、上下方向、
及び横方向のＡｌ配線間のフリンジ容量を低減できる。
従って、信号の伝達速度の遅延を抑制でき半導体装置と
しての性能を向上できる。As shown in FIG. 7, instead of the FSG film, a fluorine-free interlayer film 18a such as USG is used.
According to the embodiment of the present invention, the width of the Ti / TiN films 15a, 15b, and 15c can be reduced even when a film or a TEOS film is used. That is, the distance between the Ti / TiN films 15a and 15b becomes longer, and the Ti / TiN films 15a and 15b become larger.
The surface area of b, 15c is reduced. Because of this,
In addition, the fringe capacitance between the Al wirings in the lateral direction can be reduced.
Therefore, the delay of the signal transmission speed can be suppressed, and the performance as a semiconductor device can be improved.
【００３２】尚、本発明の実施形態において、金属膜及
びバリア膜はＡｌＣｕ膜及びＴｉ／ＴｉＮ膜に限定され
るものではない。In the embodiment of the present invention, the metal film and the barrier film are not limited to the AlCu film and the Ti / TiN film.
【００３３】その他、本発明は、その要旨を逸脱しない
範囲で、種々変形して実施することが可能である。In addition, the present invention can be variously modified and implemented without departing from the gist thereof.
【００３４】[0034]
【発明の効果】以上説明したように本発明によれば、配
線抵抗の上昇及び信頼性の低下を抑制することが可能な
半導体装置及びその製造方法を提供できる。As described above, according to the present invention, it is possible to provide a semiconductor device capable of suppressing an increase in wiring resistance and a decrease in reliability, and a method of manufacturing the same.
【図１】本発明に係わる半導体装置の製造工程を示す断
面図。FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to the present invention.
【図２】図１に続く半導体装置の製造工程を示す断面
図。FIG. 2 is a sectional view showing a manufacturing step of the semiconductor device following FIG. 1;
【図３】図２に続く半導体装置の製造工程を示す断面
図。FIG. 3 is a sectional view showing a manufacturing step of the semiconductor device following FIG. 2;
【図４】図３に続く半導体装置の製造工程を示す断面
図。FIG. 4 is a sectional view showing a manufacturing step of the semiconductor device following FIG. 3;
【図５】図４に続く半導体装置の製造工程を示す断面
図。FIG. 5 is a sectional view showing a manufacturing step of the semiconductor device following FIG. 4;
【図６】図５に続く半導体装置の製造工程を示す断面
図。FIG. 6 is a sectional view showing a manufacturing step of the semiconductor device following FIG. 5;
【図７】Ａｌ配線相互間のフリンジ容量の低減を示す
図。FIG. 7 is a diagram showing a reduction in fringe capacitance between Al wirings.
【図８】従来技術による半導体装置の製造工程を示す断
面図。FIG. 8 is a sectional view showing a manufacturing process of a semiconductor device according to a conventional technique.
【図９】図８に続く半導体装置の製造工程を示す断面
図。FIG. 9 is a sectional view showing the manufacturing process of the semiconductor device, following FIG. 8;
【図１０】図９に続く半導体装置の製造工程を示す断面
図。FIG. 10 is a sectional view showing the manufacturing process of the semiconductor device, following FIG. 9;
【図１１】図１０に続く半導体装置の製造工程を示す断
面図。FIG. 11 is a sectional view showing the manufacturing process of the semiconductor device following FIG. 10;
【図１２】図１１に続く半導体装置の製造工程を示す断
面図。FIG. 12 is a sectional view showing a manufacturing step of the semiconductor device, following FIG. 11;
１１…シリコン基板、 １２…層間絶縁膜、 １３…第１のＴｉ／ＴｉＮ膜、 １４…ＡｌＣｕ膜、 １５、１５ａ、１５ｂ…第２のＴｉ／ＴｉＮ膜、 １６…レジスト膜、 １７…ＵＳＧ膜、 １８…ＦＳＧ膜、 １８ａ…層間膜、 １９…ＴＥＯＳ膜、 ２１…Ｖｉａ、 ２２…タングステン、 ２３…Ｔｉ／ＴｉＮ膜、 ２４…ＡｌＣｕ膜、 ２５…Ｔｉ／ＴｉＮ膜。 Reference Signs List 11: silicon substrate, 12: interlayer insulating film, 13: first Ti / TiN film, 14: AlCu film, 15, 15a, 15b: second Ti / TiN film, 16: resist film, 17: USG film, Reference numeral 18: FSG film, 18a: interlayer film, 19: TEOS film, 21: Via, 22: tungsten, 23: Ti / TiN film, 24: AlCu film, 25: Ti / TiN film.
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 4M104 BB14 DD06 DD37 DD43 DD65 DD67 EE08 EE12 FF16 GG16 HH13 5F004 AA05 BA04 DA01 DA04 DA23 DB00 DB08 DB12 EA09 EA23 EB01 EB02 EB03 5F033 HH09 HH18 HH33 JJ19 KK09 KK18 KK33 MM01 MM05 MM08 MM13 MM19 NN01 PP06 PP15 QQ08 QQ11 QQ13 QQ15 QQ23 QQ33 QQ37 QQ48 RR09 RR11 SS04 WW01 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 4M104 BB14 DD06 DD37 DD43 DD65 DD67 EE08 EE12 FF16 GG16 HH13 5F004 AA05 BA04 DA01 DA04 DA23 DB00 DB08 DB12 EA09 EA23 EB01 EB02 EB03 5F033 HH09 HH18 HH33 KK18 MM19 KK MM19 NN01 PP06 PP15 QQ08 QQ11 QQ13 QQ15 QQ23 QQ33 QQ37 QQ48 RR09 RR11 SS04 WW01
Claims (5)
の幅より狭い金属膜と、 前記金属膜上に形成され、前記金属膜の幅より狭い第２
のバリア層とを具備することを特徴とする半導体装置。An insulating film formed on a semiconductor substrate; a first barrier layer formed on the insulating film; and a width of the first barrier layer formed on the first barrier layer. A second metal film formed on the metal film, the second metal film being narrower than the width of the metal film;
And a barrier layer.
記金属膜の幅の５乃至２０％の幅だけ前記金属膜の側面
より内側に位置していることを特徴とする請求項１記載
の半導体装置。2. The method according to claim 1, wherein one side surface of the second barrier layer is located inside the side surface of the metal film by a width of 5 to 20% of the width of the metal film. 13. The semiconductor device according to claim 1.
と、 前記絶縁膜上に第１のバリア層を形成する工程と、 前記第１のバリア層上に金属膜を形成する工程と、 前記金属膜上に第２のバリア層を形成する工程と、 前記第２のバリア層上に選択的にレジスト膜を形成する
工程と、 前記レジスト膜をマスクとして、前記第２のバリア層を
除去する第１の除去工程と、 前記第２のバリア層の両側面を、前記レジスト膜の幅よ
りも狭く除去する第２の除去工程と、 前記レジスト膜をマスクとして、前記金属膜及び前記第
１のバリア層を除去する第３の除去工程とを含むことを
特徴とする半導体装置の製造方法。A step of forming an insulating film on the semiconductor substrate; a step of forming a first barrier layer on the insulating film; a step of forming a metal film on the first barrier layer; Forming a second barrier layer on the metal film; selectively forming a resist film on the second barrier layer; removing the second barrier layer using the resist film as a mask A first removing step, a second removing step of removing both side surfaces of the second barrier layer to be smaller than a width of the resist film, and using the resist film as a mask, the metal film and the first A third removing step of removing the barrier layer.
のバリア層の一方の側面は、前記第３の除去工程後の前
記金属膜の幅の５乃至２０％の幅だけ前記金属膜の側面
より内側に位置するように除去することを特徴とする請
求項３記載の半導体装置の製造方法。4. The method according to claim 1, wherein in the second removing step, the second
The one side surface of the barrier layer is removed so as to be located inside the side surface of the metal film by a width of 5 to 20% of the width of the metal film after the third removing step. Item 4. The method for manufacturing a semiconductor device according to Item 3.
ＣＦ4を含むガスを用いてＣＤＥにより行うことを特徴
とする請求項３記載の半導体装置の製造方法。5. The method according to claim 3, wherein the second removing step is performed by CDE using a gas containing Cl 2 , Ar, and CF 4 .
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|---|---|---|---|
| JP11186340A JP2001015599A (en) | 1999-06-30 | 1999-06-30 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11186340A JP2001015599A (en) | 1999-06-30 | 1999-06-30 | Semiconductor device and manufacture thereof |
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| Publication Number | Publication Date |
|---|---|
| JP2001015599A true JP2001015599A (en) | 2001-01-19 |
Family
ID=16186650
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|---|---|---|---|
| JP11186340A Pending JP2001015599A (en) | 1999-06-30 | 1999-06-30 | Semiconductor device and manufacture thereof |
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| Country | Link |
|---|---|
| JP (1) | JP2001015599A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7781772B2 (en) | 2002-09-20 | 2010-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
| JP2015088585A (en) * | 2013-10-30 | 2015-05-07 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| WO2018150781A1 (en) * | 2017-02-17 | 2018-08-23 | 株式会社村田製作所 | Thin film device and method for manufacturing thin film device |
-
1999
- 1999-06-30 JP JP11186340A patent/JP2001015599A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7781772B2 (en) | 2002-09-20 | 2010-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
| US7897973B2 (en) | 2002-09-20 | 2011-03-01 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
| US8450851B2 (en) | 2002-09-20 | 2013-05-28 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
| US8749061B2 (en) | 2002-09-20 | 2014-06-10 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
| US9082768B2 (en) | 2002-09-20 | 2015-07-14 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
| US9622345B2 (en) | 2002-09-20 | 2017-04-11 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
| US9847386B2 (en) | 2002-09-20 | 2017-12-19 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
| US10090373B2 (en) | 2002-09-20 | 2018-10-02 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
| JP2015088585A (en) * | 2013-10-30 | 2015-05-07 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| WO2018150781A1 (en) * | 2017-02-17 | 2018-08-23 | 株式会社村田製作所 | Thin film device and method for manufacturing thin film device |
| JPWO2018150781A1 (en) * | 2017-02-17 | 2019-02-21 | 株式会社村田製作所 | Thin film device and method for manufacturing thin film device |
| US10978249B2 (en) | 2017-02-17 | 2021-04-13 | Murata Manufacturing Co, Ltd. | Thin-film device and method of manufacturing thin-film device |
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