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JP2001007280A - Semiconductor device and mounting structure thereof - Google Patents

Semiconductor device and mounting structure thereof

Info

Publication number
JP2001007280A
JP2001007280A JP11178161A JP17816199A JP2001007280A JP 2001007280 A JP2001007280 A JP 2001007280A JP 11178161 A JP11178161 A JP 11178161A JP 17816199 A JP17816199 A JP 17816199A JP 2001007280 A JP2001007280 A JP 2001007280A
Authority
JP
Japan
Prior art keywords
package substrate
semiconductor device
semiconductor
substrate
side end
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP11178161A
Other languages
Japanese (ja)
Inventor
Yukinaga Imamura
幸永 今村
Keisuke Okada
圭介 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Engineering Co Ltd
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Engineering Co Ltd
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Engineering Co Ltd, Mitsubishi Electric Corp filed Critical Mitsubishi Electric Engineering Co Ltd
Priority to JP11178161A priority Critical patent/JP2001007280A/en
Priority to FR0007430A priority patent/FR2795556A1/en
Priority to TW089111833A priority patent/TW490836B/en
Priority to DE10030144A priority patent/DE10030144A1/en
Priority to KR1020000034038A priority patent/KR20010021009A/en
Priority to CN00118760A priority patent/CN1287382A/en
Publication of JP2001007280A publication Critical patent/JP2001007280A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0652—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3447—Lead-in-hole components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/366—Assembling printed circuits with other printed circuits substantially perpendicularly to each other

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Combinations Of Printed Boards (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To mount a package substrate which is vertical to a packaging substrate for mounting a semiconductor chip by equipping the package substrate with first and second main surfaces and a side end face that oppose each other with the semiconductor chip and a lead pin for electrical connection, extending in one direction and nearly in parallel with the main surface on the side end face. SOLUTION: Semiconductor chips 11 and 12 are arranged via a die pad 7 on the main surface at both the front and rear sides of a package substrate 13, where a lead pin 9 is arranged only on one side end face. The semiconductor chips 11 and 12 are connected to a package substrate pad provided on the package substrate 13 with wire 6. The package substrate pad is connected to an internal wiring 14, through the inside of the package substrate 13. Also the internal wiring 14 is connected to the lead pin 9 projecting from one side end face of the package substrate 13 to the outside. The semiconductor chips 11 and 12, the die pad 7, and the wire 6 are covered with mold 4 for covering the surface of the package substrate 13, thus packaging the semiconductor device two dimensionally for the packaging substrate with high density.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、複数の半導体チッ
プを実装するために用いる、パッケージ基板および実装
基板を備える半導体装置およびその実装構造に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with a package substrate and a mounting substrate for mounting a plurality of semiconductor chips, and a mounting structure thereof.

【０００２】[0002]

【従来の技術】従来から、半導体チップが設けられたパ
ッケージ基板を実装基板に設置して使用する半導体装置
が用いられている。従来の半導体装置は、図１４〜図１
７に示すＱＦＰ−ＬＳＩ（Quad Flat Package−Large
Scale Integration Circuit）１０１，１０２のよ
うに、１個の半導体チップ１０５が、タイパッド１０７
を介してパッケージ基板１０８の一方の主表面に設けら
れている。また、半導体チップ１０５内部の電極に接続
されたワイヤ１０６が、パッケージ基板１０８の側端面
に設けられたリードピン１０９に接続されている。ま
た、リードピン１０９および半導体チップ１０５はモー
ルド１０４により被覆され、パッケージ基板１０８に固
定されている。このＱＦＰ−ＬＳＩ１０１，１０２は、
図１７に示すように、実装基板１０３に半導体チップ１
０５が設けられていない面を向けて取付けられている。2. Description of the Related Art Conventionally, semiconductor devices have been used in which a package substrate provided with a semiconductor chip is mounted on a mounting substrate for use. FIGS. 14 to 1 show a conventional semiconductor device.
QFP-LSI (Quad Flat Package-Large)
Scale integration circuit) 101 and 102, one semiconductor chip 105 is
Is provided on one main surface of the package substrate 108 via the. A wire 106 connected to an electrode inside the semiconductor chip 105 is connected to a lead pin 109 provided on a side end surface of the package substrate 108. The lead pins 109 and the semiconductor chip 105 are covered with the mold 104 and fixed to the package substrate 108. These QFP-LSIs 101 and 102
As shown in FIG. 17, the semiconductor chip 1
05 is installed with its surface not provided.

【０００３】[0003]

【発明が解決しようとする課題】上記ＱＦＰ−ＬＳＩ１
０１，１０２は、図１７に示すように、実装基板１０３
面上において、１個当たりａ×ｂの占有面積を必要とす
る。それにより、ｎ個のＱＦＰ−ＬＳＩを実装基板１０
３上に設けるためには、ｎ×ａ×ｂの実装基板面積と、
電気信号をＱＦＰ−ＬＳＩに送るために、ＱＦＰ−ＬＳ
Ｉのリードピンに接続される配線を設けるための配線領
域面積とが必要となる。The above QFP-LSI1
01 and 102, as shown in FIG.
On the surface, an occupied area of a × b is required for each unit. As a result, n QFP-LSIs are mounted on the mounting board 10.
3, the mounting substrate area of n × a × b,
QFP-LS to send electric signals to QFP-LSI
A wiring area for providing a wiring connected to the I lead pin is required.

【０００４】このように、従来のＱＦＰ−ＬＳＩにおい
ては、半導体チップの個数に応じて実装基板を占有する
面積が増加する。また、設置されるＱＦＰ−ＬＳＩの増
加にともなってリードピンの数も増加し、実装基板上で
の配線の混雑という問題も生じている。さらに、半導体
素子の高速化とともに高集積化された半導体装置におい
ては、半導体チップから排出される熱を処理する必要が
あるが、上記のようなＱＦＰ−ＬＳＩの構造では、さら
なる放熱化のために、放熱フィンの追加やファンの追加
が必要となる。As described above, in the conventional QFP-LSI, the area occupying the mounting board increases according to the number of semiconductor chips. Further, as the number of QFP-LSIs installed increases, the number of lead pins also increases, which causes a problem of congestion of wiring on the mounting board. Further, in a semiconductor device that is highly integrated with an increase in the speed of a semiconductor element, it is necessary to treat heat discharged from a semiconductor chip. However, in the structure of the QFP-LSI described above, in order to further dissipate heat, Therefore, it is necessary to add a radiation fin or a fan.

【０００５】本発明は上記の課題を解決するためになさ
れたものであり、その目的は、パッケージ基板を実装基
板に対して垂直に取付けることにより、効率的に半導体
チップを実装し得る半導体装置およびその実装構造を提
供することである。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device capable of efficiently mounting a semiconductor chip by mounting a package substrate perpendicularly to a mounting substrate. It is to provide the mounting structure.

【０００６】[0006]

【課題を解決するための手段】請求項１に記載の本発明
における半導体装置は、互いに表裏をなして対向する第
１および第２の主表面ならびに側端面を有するパッケー
ジ基板と、第１および第２の主表面のそれぞれに設けら
れた半導体チップと、側端面に設けられ、第１および第
２の主表面と略平行な一方向に延びる電気的接続用のリ
ードピンとを備えている。According to a first aspect of the present invention, there is provided a semiconductor device according to the present invention, comprising: a package substrate having first and second main surfaces and side end surfaces which face each other; The semiconductor device includes a semiconductor chip provided on each of the two main surfaces and a lead pin for electrical connection provided on a side end surface and extending in one direction substantially parallel to the first and second main surfaces.

【０００７】このような構造にすることにより、パッケ
ージ基板のリードピンが設けられている面を実装基板に
向けて取付けることによって、実装基板に対してパッケ
ージ基板を垂直にして実装することができる。それによ
り、パッケージ基板の両面にそれぞれ半導体チップを取
りつけることによって、半導体装置を実装基板に対して
垂直な方向に数多く設けることができる。そのため、半
導体チップｎ個を実装する場合において、パッケージ基
板が実装基板上を占有する面積は、従来技術のように半
導体チップがパッケージ基板の一方の主表面にのみ設け
られ、実装基板に半導体チップが設けられていない面を
向けて取付けられる半導体装置の占有面積に比較して小
さくなる。その結果、同一実装基板面積で数多くの半導
体チップを設置することができるため、半導体装置を平
面的に高集積化して実装することが可能となる。With such a structure, the surface of the package substrate on which the lead pins are provided is mounted facing the mounting substrate, so that the package substrate can be mounted vertically with respect to the mounting substrate. Thus, by mounting semiconductor chips on both surfaces of the package substrate, a large number of semiconductor devices can be provided in a direction perpendicular to the mounting substrate. Therefore, when mounting n semiconductor chips, the area occupied by the package substrate on the mounting substrate is limited to that the semiconductor chip is provided only on one main surface of the package substrate as in the related art. The area occupied by the semiconductor device which is mounted with its non-provided surface facing is reduced. As a result, a large number of semiconductor chips can be installed in the same mounting substrate area, so that the semiconductor device can be mounted with high integration planarly.

【０００８】また、請求項２に記載のように、パッケー
ジ基板の第１および第２の主表面の少なくとも一方に複
数の半導体チップを設けることによって、実装基板に対
して垂直な方向に半導体チップの実装個数を増加させる
ことにより、同一実装基板面積で、さらに数多くの半導
体チップを設置することができる。その結果、半導体装
置を平面的にさらに高集積化して実装することが可能と
なる。According to a second aspect of the present invention, a plurality of semiconductor chips are provided on at least one of the first and second main surfaces of the package substrate, so that the semiconductor chips are mounted in a direction perpendicular to the mounting substrate. By increasing the number of mounted semiconductor devices, a larger number of semiconductor chips can be installed with the same mounting substrate area. As a result, the semiconductor device can be mounted with higher integration in a planar manner.

【０００９】また、共通する信号を送るパッケージ基板
に設けられる２以上の半導体チップのリードピンを１つ
にまとめることによって、全体のリードピンの数を削減
することができる。Further, by combining the lead pins of two or more semiconductor chips provided on a package substrate for transmitting a common signal into one, the total number of lead pins can be reduced.

【００１０】また、本発明の半導体装置においては、パ
ッケージ基板の主表面を構成する表面および裏面の両方
に半導体チップを直接設置することにより、主表面の一
方にのみ半導体チップが設けられたパッケージ基板をソ
ケット等に設けて実装基板に設置する従来用いられてい
た実装構造とする必要がなくなる。そのため、部品点数
の低減を図ることができるとともに、製造工程を簡略化
することができる。Further, in the semiconductor device of the present invention, the semiconductor chip is directly provided on both the front surface and the back surface constituting the main surface of the package substrate, so that the semiconductor chip is provided on only one of the main surfaces. It is not necessary to provide a mounting structure which has been used conventionally, in which is provided in a socket or the like and is mounted on a mounting substrate. Therefore, the number of parts can be reduced, and the manufacturing process can be simplified.

【００１１】請求項３に記載の本発明における半導体装
置は、請求項１または２に記載の半導体装置において、
側端面のうちの、リードピンが設けられた領域以外の所
定の領域から突き出すように、半導体チップの接地用平
板が設けられている。According to a third aspect of the present invention, there is provided a semiconductor device according to the first or second aspect,
A grounding flat plate of the semiconductor chip is provided so as to protrude from a predetermined region of the side end surface other than the region where the lead pins are provided.

【００１２】このような構造にすることにより、半導体
チップ内で発生した熱を、接地用平板を利用して放熱す
ることができる。また、接地用平板を大型化することに
より、接地面積が拡大するため、低インピーダンス化す
ることが可能になる。その結果、半導体装置の内部およ
び外部で発生するノイズの影響を低減することができ
る。With this structure, the heat generated in the semiconductor chip can be radiated by using the grounding flat plate. In addition, by increasing the size of the grounding plate, the grounding area is increased, so that the impedance can be reduced. As a result, the effects of noise generated inside and outside the semiconductor device can be reduced.

【００１３】請求項４に記載の本発明における半導体装
置は、請求項３に記載の半導体装置において、パッケー
ジ基板が実装基板に取付けられた状態のときに、接地用
平板が、その実装基板と対向する面と実装基板との間
に、他の半導体装置を挿入し得る隙間を残すような態様
で、パッケージ基板の側端面から突き出している。According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, when the package substrate is mounted on the mounting substrate, the grounding flat plate faces the mounting substrate. The semiconductor device protrudes from the side end surface of the package substrate in such a manner as to leave a gap into which another semiconductor device can be inserted between the mounting surface and the mounting substrate.

【００１４】このような構造にすることにより、上記隙
間に、従来から用いているような片面にのみ半導体チッ
プが設けられた他のパッケージ基板を、半導体基板が設
けられていない面を実装基板に接して設置することがで
きるため、同一実装基板面積でさらに数多くの半導体チ
ップを設置することができる。その結果、さらに半導体
装置を高集積化して実装することができる。With such a structure, another package substrate having a semiconductor chip provided only on one side, which has been conventionally used, can be used in the above-described gap, and a surface having no semiconductor substrate can be used as a mounting substrate. Since they can be placed in contact with each other, more semiconductor chips can be placed with the same mounting board area. As a result, the semiconductor device can be further integrated and mounted.

【００１５】請求項５に記載の本発明における半導体装
置は、請求項１または２に記載の半導体装置において、
側端面のうちの、リードピンが設けられた領域以外の領
域に半導体チップの接地用ピンが設けられている。A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to the first or second aspect,
The ground pins of the semiconductor chip are provided in a region of the side end surface other than the region where the lead pins are provided.

【００１６】このような構造にすることにより、請求項
６に記載のように、半導体装置が実装基板の主面に対し
て垂直に複数取付けられ、複数の半導体装置の接地用ピ
ン同士が接地用平板で電気的に接続された実装構造とす
ることができる。それによって、接地用平板を放熱基板
として用いるとともに、接地面積の拡大による低インピ
ーダンス化が可能となる点を利用して半導体装置の内部
および外部で発生するノイズの影響を低減することがで
きる。According to this structure, a plurality of semiconductor devices are vertically mounted on the main surface of the mounting board, and the ground pins of the plurality of semiconductor devices are connected to each other. A mounting structure electrically connected by a flat plate can be obtained. This makes it possible to reduce the influence of noise generated inside and outside the semiconductor device by using the fact that the grounding flat plate is used as a heat dissipation substrate and the impedance can be reduced by increasing the grounding area.

【００１７】[0017]

【発明の実施の形態】以下、本発明の実施の形態を図に
基づいて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

【００１８】（実施の形態１）まず、本発明の実施の形
態１における半導体装置を、図１〜図８を用いて説明す
る。本実施の形態の半導体装置においては、図１〜図３
に示すように、リードピン９が一方の側端面にのみ配置
されたパッケージ基板１３の表裏両側の主表面に、半導
体チップ１１，１２がタイパッド７を介して設置されて
いる。半導体チップ１１，１２はそれぞれ、ワイヤ６に
より、パッケージ基板１３上に設けられたパッケージ基
板パッド１５に接続されている。このパッケージ基板パ
ッド１５は、パッケージ基板１３内部を通る内部配線１
４に接続されている。First Embodiment First, a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. In the semiconductor device according to the present embodiment, FIGS.
As shown in FIG. 1, semiconductor chips 11 and 12 are provided via tie pads 7 on the main surfaces on both the front and back sides of a package substrate 13 in which lead pins 9 are arranged only on one side end surface. Each of the semiconductor chips 11 and 12 is connected to a package substrate pad 15 provided on the package substrate 13 by a wire 6. This package substrate pad 15 is used for the internal wiring 1 passing inside the package substrate 13.
4 is connected.

【００１９】また、内部配線１４は、パッケージ基板１
３の一方の側端面から外部に突き出したリードピン９に
接続されている。また、上記半導体チップ１１，１２、
タイパッド７、ワイヤ６は、パッケージ基板１３の表面
を覆うモールド４により被覆されている。The internal wiring 14 is formed on the package substrate 1.
3 is connected to a lead pin 9 protruding outside from one side end face. In addition, the semiconductor chips 11, 12,
The tie pad 7 and the wire 6 are covered with a mold 4 that covers the surface of the package substrate 13.

【００２０】さらに、図１〜図３に示すパッケージ基板
１３は、図４および図５に示すように、リードピン９を
有する側端面を向けて実装基板３の主面に対して垂直に
実装され、実装基板３上での平面的に見た占有面積はｃ
×ｄである。Further, as shown in FIGS. 4 and 5, the package substrate 13 shown in FIGS. 1 to 3 is mounted perpendicularly to the main surface of the mounting substrate 3 with the side end face having the lead pins 9 facing toward it. The area occupied on the mounting substrate 3 in a plan view is c
× d.

【００２１】また、図６〜図８には、パッケージ基板１
３の表裏両側の主表面それぞれに、３個ずつの半導体チ
ップ１６，１７，１８および半導体チップ１９，２０，
２１が設けられた態様を示している。本実施の形態で
は、パッケージ基板１３の主表面の表裏両側のぞれぞれ
に３個ずつ半導体チップを設けたが、パッケージ基板１
３表裏両側の主表面の少なくとも一方に複数個設けるよ
うな態様であってもよい。FIGS. 6 to 8 show the package substrate 1.
3, three semiconductor chips 16, 17, 18 and semiconductor chips 19, 20,
21 shows an aspect in which 21 is provided. In the present embodiment, three semiconductor chips are provided on each of the front and back sides of the main surface of the package substrate 13.
(3) A mode in which a plurality of the main surfaces are provided on at least one of the main surfaces on both sides.

【００２２】このような構造にすることにより、パッケ
ージ基板１３のリードピン９が設けられている面を実装
基板３に向けて取付けることによって、実装基板３に対
してパッケージ基板１３を垂直にして実装することがで
きる。それにより、パッケージ基板１３の主表面の表裏
両面にそれぞれ半導体チップ１１，１２を取付けること
によって、半導体装置を実装基板に対して垂直な方向に
数多く設けることができる。そのため、半導体チップｎ
個を実装する場合において、パッケージ基板１３が実装
基板上を占有する面積ｎ×ｃ×ｄは、従来技術で示した
一方の面にのみ半導体チップが設けられたパッケージ基
板の実装基板上での占有面積ｎ×ａ×ｂに比較して小さ
くなる。その結果、同一実装基板面積で数多くの半導体
チップ１１，１２を設置することができるため、半導体
装置を平面的に高密度化して実装することが可能とな
る。With such a structure, the surface on which the lead pins 9 of the package substrate 13 are provided is attached to the mounting substrate 3 so that the package substrate 13 is mounted perpendicular to the mounting substrate 3. be able to. Thus, by mounting the semiconductor chips 11 and 12 on the front and back surfaces of the main surface of the package substrate 13, a large number of semiconductor devices can be provided in a direction perpendicular to the mounting substrate. Therefore, the semiconductor chip n
In the case of mounting the semiconductor device, the area n × c × d occupied by the package substrate 13 on the mounting substrate is equal to the occupation on the mounting substrate of the package substrate in which the semiconductor chip is provided only on one surface shown in the related art. It is smaller than the area n × a × b. As a result, a large number of semiconductor chips 11 and 12 can be installed in the same mounting substrate area, so that the semiconductor device can be mounted with a high density in a plane.

【００２３】また、図６〜図８に示す半導体チップ１
６，１７，１８および半導体装置１９，２０，２１のよ
うにパッケージ基板１３の少なくとも一方の面に半導体
チップを複数個設ければ、さらに、同一平面積で数多く
の半導体チップ５を実装することができる。The semiconductor chip 1 shown in FIGS.
If a plurality of semiconductor chips are provided on at least one surface of the package substrate 13 as in the case of the semiconductor devices 6, 17, 18 and the semiconductor devices 19, 20, 21, more semiconductor chips 5 can be mounted in the same plane area. it can.

【００２４】また、共通する信号を送るパッケージ基板
１３に設けられる２つの半導体チップ１１，１２のリー
ドピンを１つにまとめることによって、全体のリードピ
ン９の数を削減することができる。Further, by combining the lead pins of the two semiconductor chips 11 and 12 provided on the package substrate 13 for transmitting a common signal into one, the total number of lead pins 9 can be reduced.

【００２５】また、本発明においては、半導体チップ１
１，１２をパッケージ基板１３の表面および裏面に直接
設置することにより、一方の面にのみ半導体チップが設
けられたパッケージ基板をソケット等に設けて実装基板
に設置する従来のような実装構造としなくてもすむた
め、部品点数の低減を図ることができるとともに、製造
工程を簡略化できる。In the present invention, the semiconductor chip 1
By directly mounting the package substrates 1 and 12 on the front and back surfaces of the package substrate 13, a package substrate having a semiconductor chip provided only on one surface is provided in a socket or the like, and a conventional mounting structure is not provided. Therefore, the number of parts can be reduced, and the manufacturing process can be simplified.

【００２６】（実施の形態２）次に、本発明の実施の形
態２における半導体装置を、図９〜図１２を用いて説明
する。本実施の形態の半導体装置は、図９〜図１２に示
すように、実施の形態１で説明した半導体装置におい
て、パッケージ基板１３の、リードピン９が取付けられ
る側端面以外の３つの側端面それぞれから突き出すよう
に、接地用平板２２がさらに設けられている。また、パ
ッケージ基板１３の左右の側端面から突き出す接地用平
板２２の下端と実装基板３との間には、所定の隙間ｅが
設けられている。このような隙間ｅを設けることによ
り、この部分に、一方の主表面にのみ半導体チップが設
置され、パッケージ基板の他方の主表面を実装基板に向
けて設置された上記従来技術で示したようなパッケージ
基板の端部を挿入することができる。Second Embodiment Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. As shown in FIGS. 9 to 12, the semiconductor device according to the present embodiment is different from the semiconductor device described in the first embodiment in that the package substrate 13 has three side end surfaces other than the side end surface to which the lead pins 9 are attached. A grounding flat plate 22 is further provided so as to protrude. A predetermined gap e is provided between the lower end of the grounding flat plate 22 protruding from the left and right side end surfaces of the package substrate 13 and the mounting substrate 3. By providing such a gap e, in this portion, the semiconductor chip is installed only on one main surface, and the other main surface of the package substrate is installed with the other main surface facing the mounting substrate, as shown in the above-described prior art. The end of the package substrate can be inserted.

【００２７】このような構造にすることにより、半導体
チップ１１，１２内で発生した熱を、接地用平板２２を
利用して放熱することができる。また、接地用平板２２
を外部まで引き出し、接地面積を拡大させることによっ
て低インピーダンス化が可能になる点を利用して、半導
体装置の内部および外部で発生するノイズの影響を低減
することができる。With such a structure, heat generated in the semiconductor chips 11 and 12 can be radiated by using the grounding flat plate 22. Also, the grounding plate 22
The effect of noise generated inside and outside the semiconductor device can be reduced by utilizing the fact that the impedance can be reduced by extending the ground area to the outside and increasing the ground area.

【００２８】また、上記従来技術で示したパッケージ基
板１０８のような、一方の主表面にのみ半導体チップ１
０５が設けられたパッケージ基板１０１，１０２を、他
方の主表面を実装基板３に接して、上記隙間ｅに端部を
挿入するようにしてさらに設置することができるため、
同一実装基板面積でさらに数多くの半導体チップを実装
することができる。その結果、平面的に見た半導体装置
の実装密度をさらに高めることができる。The semiconductor chip 1 is provided only on one main surface, such as the package substrate 108 shown in the prior art.
Since the package substrates 101 and 102 provided with 05 can be further installed such that the other main surface is in contact with the mounting substrate 3 and the end is inserted into the gap e.
More semiconductor chips can be mounted on the same mounting substrate area. As a result, the mounting density of the semiconductor device in a plan view can be further increased.

【００２９】（実施の形態３）次に、本発明の実施の形
態３における半導体装置を、図１３を用いて説明する。
本実施の形態の半導体装置は、図１３に示すように、実
施の形態１で示した半導体装置と略同様の構造である
が、パッケージ基板２４，２５が、実装基板３に取付け
られる側端面と反対側の側端面に接地用ピン２６をさら
に有する点において異なる。Third Embodiment Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG.
As shown in FIG. 13, the semiconductor device of the present embodiment has substantially the same structure as that of the semiconductor device shown in the first embodiment, except that the package substrates 24 and 25 have side end faces attached to the mounting substrate 3. The difference is that a grounding pin 26 is further provided on the opposite side end surface.

【００３０】このパッケージ基板２４，２５は、互いに
略平行に、実装基板３に対して略垂直に取付けられてい
る。また、一方のパッケージ基板２４の実装基板３に取
付けられる側と反対側の接地用ピン２６の全てが、他方
のパッケージ基板２５の実装基板３に取付けられる側端
面と反対側の側端面に設けられた接地用ピン２６の全て
と接地用平板２３で電気的に接続されている。The package substrates 24 and 25 are mounted substantially parallel to each other and substantially perpendicular to the mounting substrate 3. In addition, all of the ground pins 26 on one side of the package substrate 24 opposite to the side attached to the mounting substrate 3 are provided on the side end surface of the other package substrate 25 opposite to the side end surface attached to the mounting substrate 3. All of the grounding pins 26 are electrically connected to the grounding flat plate 23.

【００３１】このような構造にすることにより、上記の
接地用平板２３を放熱基板として用いるとともに、接地
面積の拡大による低インピーダンス化が可能になる機能
を利用して、半導体装置の内部および外部で発生するノ
イズの影響を低減することができる。With such a structure, the above-mentioned grounding flat plate 23 is used as a heat-radiating substrate, and the function of reducing the impedance by expanding the grounding area is used to enable the inside and outside of the semiconductor device to be used. The effect of the generated noise can be reduced.

【００３２】本実施の形態においては、リードピン９を
設けた側端面とは反対側のパッケージ基板２４，２５の
側端面に接地用ピン２６を設けて、鉛直に配した接地用
平板２３で接続したが、他の態様を採用することも可能
である。In the present embodiment, ground pins 26 are provided on the side end faces of the package substrates 24 and 25 opposite to the side end faces on which the lead pins 9 are provided, and are connected by the grounding flat plate 23 disposed vertically. However, other embodiments can be adopted.

【００３３】なお、今回開示された実施の形態はすべて
の点で例示であって制限的なものではないと考えられる
べきである。本発明の範囲は上記した説明ではなく特許
請求の範囲によって示され、特許請求の範囲と均等の意
味および範囲内でのすべての変更が含まれることが意図
される。It should be understood that the embodiments disclosed this time are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

【００３４】[0034]

【発明の効果】請求項１に記載の本発明における半導体
装置によれば、パッケージ基板の両面にそれぞれ半導体
チップを取付けることによって、半導体装置を実装基板
に対して垂直な方向に数多く設けることができるため、
半導体装置を平面的に高密度化して実装することが可能
となる。According to the semiconductor device of the present invention, a large number of semiconductor devices can be provided in the direction perpendicular to the mounting substrate by mounting the semiconductor chips on both surfaces of the package substrate. For,
The semiconductor device can be mounted with high density in a plane.

【００３５】また、共通する信号を送るパッケージ基板
に設けられる２以上の半導体チップのリードピンを１つ
にまとめることによって、全体のリードピンの数を削減
することができる。Further, by combining the lead pins of two or more semiconductor chips provided on a package substrate for transmitting a common signal into one, the total number of lead pins can be reduced.

【００３６】また、請求項１に記載の半導体装置におい
ては、パッケージ基板の主表面を構成する表面および裏
面の両方に半導体チップを設置することにより、従来の
実装構造と比較して、部品点数の低減を図ることができ
るとともに、製造工程を簡略化できる。In the semiconductor device according to the first aspect of the present invention, since the semiconductor chip is provided on both the front surface and the back surface constituting the main surface of the package substrate, the number of components is smaller than that of the conventional mounting structure. Reduction can be achieved, and the manufacturing process can be simplified.

【００３７】請求項２に記載の本発明の半導体装置によ
れば、パッケージ基板の少なくとも一方の主表面に複数
の半導体チップを設けることによって立体的に実装個数
を増加させることにより、半導体装置を平面的にさらに
高密度化して実装することが可能となる。According to the semiconductor device of the second aspect of the present invention, a plurality of semiconductor chips are provided on at least one main surface of the package substrate, so that the number of mounted semiconductor devices is three-dimensionally increased. It is possible to further increase the density of the mounting.

【００３８】請求項３に記載の本発明における半導体装
置によれば、半導体チップ内で発生した熱を、接地用平
板を利用して放熱することができるとともに、接地面積
の拡大による低インピーダンス化が可能になるため、半
導体装置の内部および外部で発生するノイズの影響を低
減することができる。According to the semiconductor device of the third aspect of the present invention, the heat generated in the semiconductor chip can be dissipated using the grounding flat plate, and the impedance can be reduced by increasing the grounding area. As a result, the influence of noise generated inside and outside the semiconductor device can be reduced.

【００３９】請求項４に記載の本発明における半導体装
置によれば、隙間に、従来から用いているような片面に
のみ半導体チップが設けられた他のパッケージ基板を、
半導体基板が設けられていない面を実装基板に接して設
置することができるため、さらに半導体装置を平面的に
高密度化して実装することができる。According to the semiconductor device of the present invention as set forth in claim 4, another package substrate having a semiconductor chip provided only on one side as conventionally used is provided in the gap.
Since the surface on which the semiconductor substrate is not provided can be placed in contact with the mounting substrate, the semiconductor device can be mounted with a higher density in a planar manner.

【００４０】請求項５に記載の本発明における半導体装
置によれば、請求項６に記載のように、半導体装置が実
装基板に対して垂直に複数取付けられ、複数の半導体装
置の接地用ピンそれぞれが接地用平板で接続された実装
構造とすることがでるため接地用平板を放熱基板として
用いるとともに、接地面積の拡大による低インピーダン
ス化が可能になる点を利用して半導体装置の内部および
外部で発生するノイズの影響を低減することができる。According to the fifth aspect of the present invention, as described in the sixth aspect, a plurality of semiconductor devices are vertically attached to the mounting substrate, and each of the plurality of ground pins of the plurality of semiconductor devices is provided. Can be used as a heat-dissipating board, and the inside and outside of the semiconductor device can be used by taking advantage of the fact that the impedance can be reduced by increasing the ground area. The effect of the generated noise can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 本発明の実施の形態１における半導体装置に
おいて、パッケージ基板の第１の主表面および第２の主
表面の両方に半導体チップが設けられた状態を示す断面
図である。FIG. 1 is a cross-sectional view showing a state in which semiconductor chips are provided on both a first main surface and a second main surface of a package substrate in a semiconductor device according to a first embodiment of the present invention.

【図２】 本発明の実施の形態１における半導体装置に
おいて、半導体チップが設けられた第１の主表面を示す
図である。FIG. 2 is a diagram illustrating a first main surface on which a semiconductor chip is provided in the semiconductor device according to the first embodiment of the present invention;

【図３】 本発明の実施の形態１における半導体装置に
おいて、半導体チップが設けられた第２の主表面を示す
図である。FIG. 3 is a diagram illustrating a second main surface on which a semiconductor chip is provided in the semiconductor device according to the first embodiment of the present invention;

【図４】 本発明の実施の形態１における半導体装置に
おいて、実装基板に対して垂直にパッケージ基板が取付
けられた状態を示す斜視図である。FIG. 4 is a perspective view showing a state in which the package substrate is mounted perpendicular to the mounting substrate in the semiconductor device according to the first embodiment of the present invention;

【図５】 本発明の実施の形態１における半導体装置に
おいて、パッケージ基板の第１の主表面および第２の主
表面の両方に半導体チップが設けられた状態で鉛直に立
てた状態を示す立面図である。FIG. 5 is an elevational view of the semiconductor device according to the first embodiment of the present invention, in which a semiconductor chip is provided on both the first main surface and the second main surface of the package substrate, and the semiconductor chip is vertically set; FIG.

【図６】 本発明の実施の形態１における半導体装置に
おいて、パッケージ基板の第１の主表面に複数の半導体
チップが設けられた状態を示す図である。FIG. 6 is a diagram illustrating a state in which a plurality of semiconductor chips are provided on a first main surface of a package substrate in the semiconductor device according to the first embodiment of the present invention;

【図７】 本発明の実施の形態１における半導体装置に
おいて、パッケージ基板の第１の主表面および第２の主
表面に複数の半導体チップが設けられた状態を示す立面
図である。FIG. 7 is an elevational view showing a state where a plurality of semiconductor chips are provided on a first main surface and a second main surface of a package substrate in the semiconductor device according to the first embodiment of the present invention;

【図８】 本発明の実施の形態１における半導体装置に
おいて、パッケージ基板の第２の主表面に複数の半導体
チップが設けられた状態を示す図である。FIG. 8 is a diagram illustrating a state in which a plurality of semiconductor chips are provided on a second main surface of a package substrate in the semiconductor device according to the first embodiment of the present invention;

【図９】 本発明の実施の形態２における半導体装置に
おいて、接地用平板がパッケージ基板の側端面に設けら
れた状態を示す断面図である。FIG. 9 is a cross-sectional view showing a state where a grounding flat plate is provided on a side end surface of a package substrate in the semiconductor device according to the second embodiment of the present invention;

【図１０】 本発明の実施の形態２における半導体装置
において、接地用平板がパッケージ基板の側端面に設け
られた状態の第１の主表面を示す図である。FIG. 10 is a diagram showing a first main surface of a semiconductor device according to a second embodiment of the present invention in a state where a grounding flat plate is provided on a side end surface of a package substrate.

【図１１】 本発明の実施の形態２における半導体装置
において、接地用平板がパッケージ基板の側端面に設け
られた状態で、パッケージ基板を鉛直に立てた状態を示
す立面図である。FIG. 11 is an elevational view showing a state in which the package substrate is set upright with a grounding flat plate provided on a side end surface of the package substrate in the semiconductor device according to the second embodiment of the present invention;

【図１２】 本発明の実施の形態２における半導体装置
において、接地用平板がパッケージ基板の側端面に設け
られた状態の第２の主表面を示す図である。FIG. 12 is a diagram showing a second main surface of the semiconductor device according to the second embodiment of the present invention in a state where a grounding flat plate is provided on a side end surface of a package substrate.

【図１３】 本発明の実施の形態３における半導体装置
において、実装基板に対して垂直に取付けられた２つの
パッケージ基板の接地用のピン同士を接地用平板で電気
的に接続した状態を示す図である。FIG. 13 is a diagram showing a state in which ground pins of two package substrates vertically mounted on a mounting substrate are electrically connected to each other by a ground plate in the semiconductor device according to the third embodiment of the present invention; It is.

【図１４】 従来の半導体装置において、パッケージ基
板の一方の主表面にのみ半導体チップが設けられた状態
の断面を示す図である。FIG. 14 is a diagram showing a cross section of a conventional semiconductor device in which a semiconductor chip is provided only on one main surface of a package substrate.

【図１５】 パッケージ基板の一方の主表面にのみ半導
体チップが設けられた従来の半導体装置において、半導
体チップが設けられた面を示す図である。FIG. 15 is a diagram showing a surface on which a semiconductor chip is provided in a conventional semiconductor device having a semiconductor chip provided only on one main surface of a package substrate.

【図１６】 パッケージ基板の一方の主表面にのみ半導
体チップが設けられた従来の半導体装置において、半導
体チップが設けられていない面を示す図である。FIG. 16 is a diagram illustrating a surface of a conventional semiconductor device in which a semiconductor chip is provided only on one main surface of a package substrate, where the semiconductor chip is not provided.

【図１７】 従来の半導体装置において、実装基板に対
して平行に複数の半導体チップが設けられた状態を示す
図である。FIG. 17 is a diagram showing a state in which a plurality of semiconductor chips are provided in parallel with a mounting substrate in a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

3 実装基板、4 モールド、5 半導体チップ、6
ワイヤ、７ タイパッド、８ パッケージ基板、９ リ
ードピン、１０ パッド、１１，１２ 半導体チップ、
1３ パッケージ基板、１４ 基板内配線、１５ パッ
ケージ基板パッド、１６，１７，１８，1９，2０，２１
半導体チップ、２２，２３ 接地用平板、２４，２５
半導体チップ、２６ 接地用ピン、ｃ 半導体装置
厚、ｄ 半導体装置幅 ｅ 隙間。3 mounting board, 4 mold, 5 semiconductor chip, 6
Wires, 7 tie pads, 8 package substrates, 9 lead pins, 10 pads, 11, 12 semiconductor chips,
13 package board, 14 wiring in board, 15 package board pad, 16, 17, 18, 19, 20, 21
Semiconductor chip, 22, 23 Grounding plate, 24, 25
Semiconductor chip, 26 grounding pin, c semiconductor device thickness, d semiconductor device width e gap.

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 互いに表裏をなして対向する第１および
第２の主表面ならびに側端面を有するパッケージ基板
と、 前記第１および第２の主表面のそれぞれに設けられた半
導体チップと、 前記側端面に設けられ、前記第１および第２の主表面と
略平行な一方向に延びる電気的接続用のリードピンとを
備えた、半導体装置。1. A package substrate having first and second main surfaces and side end surfaces facing each other with front and back sides; a semiconductor chip provided on each of the first and second main surfaces; And a lead pin for electrical connection provided on an end face and extending in one direction substantially parallel to the first and second main surfaces. 【請求項２】 前記半導体チップが前記第１および第２
の主表面の少なくとも一方に複数設けられた、請求項１
に記載の半導体装置。2. The semiconductor device according to claim 1, wherein said semiconductor chip includes said first and second semiconductor chips.
2. A plurality of the main surfaces are provided on at least one of the main surfaces.
3. The semiconductor device according to claim 1. 【請求項３】 前記側端面のうちの、前記リードピンが
設けられた領域以外の所定領域から突き出すように、前
記半導体チップの接地用平板が設けられた、請求項１ま
たは２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein a ground flat plate of the semiconductor chip is provided so as to protrude from a predetermined area of the side end face other than an area where the lead pin is provided. . 【請求項４】 前記パッケージ基板が実装基板に取付け
られた状態において、前記接地用平板が、その前記実装
基板と対向する面と前記実装基板との間に、他の半導体
装置を挿入し得る隙間を残す態様で、前記パッケージ基
板の前記側端面から突き出している、請求項３に記載の
半導体装置。4. A gap in which another ground device can be inserted between the surface of the flat plate for grounding and the mounting substrate when the package substrate is mounted on the mounting substrate. 4. The semiconductor device according to claim 3, wherein the semiconductor device protrudes from the side end surface of the package substrate in a mode in which the package substrate is left. 【請求項５】 前記側端面のうちの、前記リードピンが
設けられた領域以外の領域に前記半導体チップの接地用
ピンが設けられた、請求項１または２に記載の半導体装
置。5. The semiconductor device according to claim 1, wherein a ground pin of said semiconductor chip is provided in a region of said side end surface other than a region in which said lead pin is provided. 【請求項６】 請求項５に記載の半導体装置が実装基板
の主面に対して垂直に複数取付けられ、前記複数の半導
体装置の前記接地用ピン同士が接地用平板で電気的に接
続された、半導体装置の実装構造。6. The semiconductor device according to claim 5, wherein a plurality of the semiconductor devices are vertically attached to a main surface of the mounting substrate, and the ground pins of the plurality of semiconductor devices are electrically connected to each other by a ground plate. , Mounting structure of semiconductor device.
JP11178161A 1999-06-24 1999-06-24 Semiconductor device and mounting structure thereof Withdrawn JP2001007280A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP11178161A JP2001007280A (en) 1999-06-24 1999-06-24 Semiconductor device and mounting structure thereof
FR0007430A FR2795556A1 (en) 1999-06-24 2000-06-09 Semiconductor device and assembly structure, comprising chips mounted on both sides of casing substrate with laterally projecting pins for perpendicular mounting on printed circuit board
TW089111833A TW490836B (en) 1999-06-24 2000-06-16 Semiconductor device and mounting structure thereof
DE10030144A DE10030144A1 (en) 1999-06-24 2000-06-20 Semiconductor device and associated mounting structure
KR1020000034038A KR20010021009A (en) 1999-06-24 2000-06-21 Semiconductor device and mounting structure thereof
CN00118760A CN1287382A (en) 1999-06-24 2000-06-26 Semiconductor apparatus and its mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11178161A JP2001007280A (en) 1999-06-24 1999-06-24 Semiconductor device and mounting structure thereof

Publications (1)

Publication Number Publication Date
JP2001007280A true JP2001007280A (en) 2001-01-12

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Country Status (6)

Country Link
JP (1) JP2001007280A (en)
KR (1) KR20010021009A (en)
CN (1) CN1287382A (en)
DE (1) DE10030144A1 (en)
FR (1) FR2795556A1 (en)
TW (1) TW490836B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100461405C (en) * 2004-12-28 2009-02-11 日产自动车株式会社 Semiconductor device

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DE10255848B4 (en) * 2002-11-29 2008-04-30 Qimonda Ag Semiconductor device and method for its production and motherboard with this semiconductor device
US8053891B2 (en) * 2008-06-30 2011-11-08 Alpha And Omega Semiconductor Incorporated Standing chip scale package
CN102332410A (en) * 2011-09-29 2012-01-25 山东华芯半导体有限公司 Packaging method and structure of chip
CN103943581B (en) * 2013-01-23 2017-07-07 中兴通讯股份有限公司 Power device packaging structure and method for packing
CN108198799A (en) * 2017-12-21 2018-06-22 刘梦思 A kind of welding structure based on manufacture sensitive integrated circuits lead
CN110556303B (en) * 2019-09-06 2021-07-09 东和半导体设备(南通)有限公司 Semiconductor packaging mold and packaging process thereof

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JPH04312965A (en) * 1991-03-29 1992-11-04 Mitsubishi Electric Corp Memory ic
KR100192179B1 (en) * 1996-03-06 1999-06-15 김영환 Semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100461405C (en) * 2004-12-28 2009-02-11 日产自动车株式会社 Semiconductor device

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TW490836B (en) 2002-06-11
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KR20010021009A (en) 2001-03-15
FR2795556A1 (en) 2000-12-29

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