JP2001006529A - Cold cathode electron source - Google Patents
Cold cathode electron sourceInfo
- Publication number
- JP2001006529A JP2001006529A JP17304699A JP17304699A JP2001006529A JP 2001006529 A JP2001006529 A JP 2001006529A JP 17304699 A JP17304699 A JP 17304699A JP 17304699 A JP17304699 A JP 17304699A JP 2001006529 A JP2001006529 A JP 2001006529A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal film
- metal
- electron source
- cold cathode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002184 metal Substances 0.000 claims abstract description 91
- 229910052751 metal Inorganic materials 0.000 claims abstract description 91
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000013078 crystal Substances 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 10
- 229910019001 CoSi Inorganic materials 0.000 claims description 10
- 229910004261 CaF 2 Inorganic materials 0.000 claims description 8
- 239000000463 material Substances 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 239000000203 mixture Substances 0.000 abstract description 3
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical compound [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 abstract 3
- 229910001634 calcium fluoride Inorganic materials 0.000 abstract 3
- 239000011810 insulating material Substances 0.000 abstract 3
- 229910018999 CoSi2 Inorganic materials 0.000 abstract 2
- 239000006185 dispersion Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 100
- 239000010931 gold Substances 0.000 description 10
- 239000012212 insulator Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011162 core material Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Landscapes
- Cold Cathode And The Manufacture (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、冷陰極電子源に関
し、特に同平面型冷陰極電子源の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cold cathode electron source, and more particularly, to the structure of a planar cold cathode electron source.
【０００２】[0002]
【従来の技術】図４は従来の冷陰極電子源の典型的な構
造の概略を示す斜視図である。金属あるいは半導体から
なる基板４１上に絶縁体層４２を設け、更にその上部に
表面金属層４３が形成されている。2. Description of the Related Art FIG. 4 is a perspective view schematically showing a typical structure of a conventional cold cathode electron source. An insulator layer 42 is provided on a substrate 41 made of metal or semiconductor, and a surface metal layer 43 is further formed thereon.
【０００３】金属あるいは半導体基板４１と上部の金属
層４３との間に引き出しバイアス電源４９により電圧を
印加して金属層４３から電子を引き出す。このように、
金属基板−絶縁体−表面金属あるいは半導体基板−絶縁
体−表面金属の材料構成からなる電子源は平面状の電子
源を得ることができる点で有用である。A voltage is applied between a metal or semiconductor substrate 41 and an upper metal layer 43 by an extraction bias power supply 49 to extract electrons from the metal layer 43. in this way,
An electron source having a metal substrate-insulator-surface metal or semiconductor substrate-insulator-surface metal material composition is useful in that a planar electron source can be obtained.
【０００４】特開平６−１６２９１８号公報（以下、公
知例１とする）には、電子放出表面となる表面金属層を
単結晶Ａｕで形成して、Ａｕ膜中を通過する電子の散乱
を抑制し電子放出電流を増加させるとともに、表面の凹
凸による電子放出の不均一を防止する方法が開示されて
いる。Japanese Patent Application Laid-Open No. 6-162918 (hereinafter referred to as "known example 1") discloses that a surface metal layer serving as an electron emission surface is formed of single crystal Au to suppress scattering of electrons passing through an Au film. A method of increasing the electron emission current and preventing non-uniformity of electron emission due to surface irregularities is disclosed.
【０００５】また、特開平６−１７７０２０号公報（以
下、公知例２とする）には、ＭＩＭ構造の薄膜冷陰極の
絶縁薄膜に単結晶あるいは高配向アルミニウム酸化膜を
用いた構造が開示されている。Further, Japanese Patent Application Laid-Open No. 6-177020 (hereinafter referred to as "known example 2") discloses a structure using a single crystal or highly oriented aluminum oxide film as an insulating thin film of a thin-film cold cathode having an MIM structure. I have.
【０００６】[0006]
【発明が解決しようとする課題】公知例１では、電子放
出表面となる表面金属層に単結晶Ａｕを用いることで、
電子放出電流の増加あるいは電子放出の不均一の抑制と
いった効果を得ている。In the known example 1, a single crystal Au is used for a surface metal layer serving as an electron emission surface.
The effect of increasing the electron emission current or suppressing the non-uniformity of electron emission is obtained.
【０００７】しかし、この単結晶Ａｕは金錯体溶液中の
金錯体を分解処理する方法により形成されているため、
単結晶Ａｕを形成する際の核形成が基板表面材料に強く
依存し、絶縁体上に直接形成するのが困難であったり、
核となる材料を予め形成してからＡｕを成長させる工夫
が必要であったりする。However, since this single crystal Au is formed by a method of decomposing a gold complex in a gold complex solution,
Nucleation during the formation of single crystal Au strongly depends on the substrate surface material, and it is difficult to form directly on an insulator,
It may be necessary to devise a method of growing Au after forming a core material in advance.
【０００８】これは、電子源の形成工程を複雑にするば
かりでなく、電子の放出面形状等の構造の設計自由度を
制限するという問題がある。This not only complicates the process of forming the electron source, but also limits the degree of freedom in designing the structure such as the shape of the electron emission surface.
【０００９】次に、公知例２では、ＧａＡｓ（００１）
基板上にＡｌを室温〜４００℃の基板温度、１０-9Ｔｏ
ｒｒの真空雰囲気、０．０５ｎｍ／ｓの蒸着速度、の条
件下で２００ｎｍ付着して単結晶Ａｌ成長させ、更にこ
の単結晶Ａｌの表面に陽極酸化法によりあるいは１０-2
Ｔｏｒｒ程度の減圧酸素中で３００から６００℃の低温
で加熱して単結晶あるいは単結晶に近い高配向膜のＡｌ
2 Ｏ3 膜を形成した後、このＡｌ2 Ｏ3 膜の上に１０ｎ
ｍのＡｕ膜を上部電極（表面金属）として抵抗加熱蒸着
法で形成したＭＩＭ構造の薄膜冷陰極が開示されてい
る。Next, in the known example 2, GaAs (001)
Al is placed on the substrate at a substrate temperature of room temperature to 400 ° C., 10 -9 To
In a vacuum atmosphere of rr and a deposition rate of 0.05 nm / s, a 200 nm film is adhered and single crystal Al is grown, and the surface of the single crystal Al is further anodized or 10 −2.
A single crystal or a highly oriented Al film close to a single crystal is heated by heating at a low temperature of 300 to 600 ° C. in reduced pressure oxygen of about Torr.
After forming the 2 O 3 film, 10n on the the Al 2 O 3 film
A thin film cold cathode having an MIM structure in which an Au film of m is formed as an upper electrode (surface metal) by a resistance heating evaporation method is disclosed.
【００１０】この公知例２では、絶縁体に単結晶あるい
は高配向膜のＡｌ2 Ｏ3 膜を用いることでエネルギの揃
った単色の電子線が得られているが、電子放出表面とな
る表面金属層を単結晶化することが困難であり、電子放
出効率に限界がある。In this known example 2, a single-crystal electron beam having uniform energy is obtained by using a single crystal or a highly oriented Al 2 O 3 film as an insulator. It is difficult to single-crystallize the layer, and the electron emission efficiency is limited.
【００１１】本発明の目的は、金属基板−絶縁体−表面
金属あるいは半導体基板−絶縁体−表面金属の材料構成
からなる電子源において、表面金属及び絶縁体に互いに
格子整合した単結晶材料を用いることで、放出電子のエ
ネルギの制御、あるいはそのバラツキ幅を低減するとと
もに、放出効率の向上した冷陰極電子源を提供すること
にある。An object of the present invention is to provide an electron source having a metal substrate-insulator-surface metal or semiconductor substrate-insulator-surface metal material structure, using a single crystal material lattice-matched to the surface metal and the insulator. Accordingly, it is an object of the present invention to provide a cold cathode electron source having improved emission efficiency while controlling the energy of emitted electrons or reducing the variation width thereof.
【００１２】[0012]
【課題を解決するための手段】本発明の冷陰極電子源
は、金属又は半導体からなる基板の上に第１の絶縁膜と
第１の金属膜とが前記基板側からこの順序で積層されて
おり、前記第１の絶縁膜と前記第１の金属膜とはいずれ
も単結晶で且つ互いに格子整合しており、更に前記第１
の金属膜が真空中に電子を放出する表面電極を構成して
いる。このとき、基板と第１の絶縁膜とも格子整合して
いることがより望ましい。According to the cold cathode electron source of the present invention, a first insulating film and a first metal film are laminated on a substrate made of metal or semiconductor in this order from the substrate side. The first insulating film and the first metal film are both single crystal and lattice-matched to each other.
Metal film constitutes a surface electrode that emits electrons in a vacuum. At this time, it is more desirable that the substrate and the first insulating film are also lattice-matched.
【００１３】また、本発明の他の冷陰極電子源は、金属
又は半導体からなる基板の上に第２の絶縁膜，第２の金
属膜，第１の絶縁膜及び第１の金属膜が前記基板側から
この順序で積層されており、（ａ）前記第１の絶縁膜及
び前記第１の金属膜はいずれも単結晶で且つ互いに格子
整合しており、（ｂ）前記第１の金属膜が表面電極を構
成する表面金属膜であり、（ｃ）前記第２の絶縁膜及び
第２の金属膜は結晶である、というものである。In another cold cathode electron source according to the present invention, a second insulating film, a second metal film, a first insulating film and a first metal film are formed on a substrate made of metal or semiconductor. (A) the first insulating film and the first metal film are both single-crystal and lattice-matched to each other; (b) the first metal film Is a surface metal film constituting a surface electrode, and (c) the second insulating film and the second metal film are crystals.
【００１４】このとき、第２の金属膜に電圧を印加する
電極を更に付加することができる。At this time, an electrode for applying a voltage to the second metal film can be further added.
【００１５】また、第２の金属膜に量子井戸層が形成さ
れるのが好ましい。Preferably, a quantum well layer is formed in the second metal film.
【００１６】また、第１の金属膜にシート抵抗低減用の
低抵抗膜をこの第１の金属膜の電子放出面側あるいはそ
の裏面側に電気的に導通するように付加してもよい。Further, a low resistance film for reducing sheet resistance may be added to the first metal film so as to be electrically connected to the electron emission surface side or the back surface side of the first metal film.
【００１７】また、第１の金属膜の電子放出面側表面を
平坦にすることもできる。Further, the surface of the first metal film on the electron emission surface side can be made flat.
【００１８】更に、第１の金属膜及び第１の絶縁膜の代
表的な例としては、それぞれ単結晶ＣｏＳｉ2 ，単結晶
ＣａＦ2 を用いることができる。Further, as typical examples of the first metal film and the first insulating film, single crystal CoSi 2 and single crystal CaF 2 can be used, respectively.
【００１９】従って、本発明の冷陰極電子源は、表面電
極を構成する第１の金属膜を含めて格子整合した材料系
で電子源が構成されているので、電子放出効率を向上さ
せながら放出電子のエネルギのバラツキ幅を狭くするこ
とが可能になっている。Therefore, since the cold cathode electron source of the present invention is formed of a lattice-matched material system including the first metal film forming the surface electrode, the electron emission is performed while improving the electron emission efficiency. It is possible to reduce the variation width of the energy of electrons.
【００２０】また、第１の絶縁膜、第１の金属膜をエピ
タキシャル成長により成膜できるので、層構造を簡便に
作製でき、更に電子の放出面形状等の構造の設計自由度
が向上する。Further, since the first insulating film and the first metal film can be formed by epitaxial growth, the layer structure can be easily formed, and the degree of freedom in designing the structure such as the electron emission surface shape is improved.
【００２１】また、第２の金属膜を用いて電子源に量子
井戸層を導入することで、第２の金属膜に電極を導入
し、量子井戸層の電位を調整することが可能になること
から放出電子のエネルギの制御も可能となっている。In addition, by introducing a quantum well layer into an electron source using the second metal film, it is possible to introduce an electrode into the second metal film and adjust the potential of the quantum well layer. It is also possible to control the energy of emitted electrons.
【００２２】[0022]
【発明の実施の形態】次に、添付した図面を参照して、
本発明の実施形態を以下に詳述する。尚，図１から図３
において共通する要素はできるだけ同じ参照符号を用い
て説明を簡略化する。BRIEF DESCRIPTION OF THE DRAWINGS FIG.
Embodiments of the present invention will be described in detail below. 1 to 3
The description of the elements common to the above will be simplified using the same reference numerals as much as possible.
【００２３】まず、本発明の第１の実施形態の冷陰極電
子源を説明する。First, a cold cathode electron source according to a first embodiment of the present invention will be described.
【００２４】図１は、本発明の第１の実施形態の冷陰極
電子源の概略構造を示す斜視図である。FIG. 1 is a perspective view showing a schematic structure of a cold cathode electron source according to the first embodiment of the present invention.
【００２５】図１を参照すると、基板１としてシリコン
ウェハを用い、この基板１上に第１の絶縁膜２及び上部
電極となる第１の金属膜３としてそれぞれ２ｎｍから１
０ｎｍ程度の膜厚のＣａＦ2 層と１ｎｍから１０ｎｍ程
度の膜厚のＣｏＳｉ2 層をこの順序でエピタキシャル成
長により堆積する。このとき、第１の絶縁膜２であるＣ
ａＦ2 層は基板１であるシリコンウェハと、また第１の
金属膜３であるＣｏＳｉ2 層は第１の絶縁膜２であるＣ
ａＦ2 層とそれぞれ格子整合した結晶構造で堆積する。Referring to FIG. 1, a silicon wafer is used as a substrate 1, and a first insulating film 2 and a first metal film 3 serving as an upper electrode are formed on the substrate 1 by 2 nm to 1 nm, respectively.
A CaF 2 layer having a thickness of about 0 nm and a CoSi 2 layer having a thickness of about 1 nm to 10 nm are deposited by epitaxial growth in this order. At this time, the first insulating film 2 C
The aF 2 layer is a silicon wafer as the substrate 1, and the CoSi 2 layer as the first metal film 3 is a CSi as the first insulating film 2.
The aF 2 layer is deposited with a crystal structure that is lattice-matched with each other.
【００２６】次に、第１の金属膜３であるＣｏＳｉ2 層
の上部に、それぞれの膜厚が５〜３０ｎｍ及び１００〜
５００ｎｍ程度のＴｉ／Ｐｔを用いてシート抵抗低減用
の低抵抗膜５をリフトオフ法により形成する。ＴｉはＣ
ｏＳｉ2 との密着性を向上させるために設ける。Ｐｔが
実際に抵抗を低減する役割を果たす。これにより、上部
電極にバイアス電圧を印加する際のシート抵抗を低減す
ることができる。Next, on the CoSi 2 layer which is the first metal film 3, the film thickness is 5 to 30 nm and 100 to 100 nm, respectively.
A low resistance film 5 for reducing sheet resistance is formed by a lift-off method using Ti / Pt of about 500 nm. Ti is C
It is provided to improve the adhesion to oSi 2 . Pt actually plays a role in reducing the resistance. Thereby, the sheet resistance when applying a bias voltage to the upper electrode can be reduced.
【００２７】引き出しバイアス電源１１により、基板１
と表面電極を構成する第１の金属膜３であるＣｏＳｉ2
層との間にバイアス電圧を印加して、低抵抗膜５である
Ｔｉ／Ｐｔが存在しない部分から電子を真空中へ放出さ
せる。The substrate 1 is supplied by the extraction bias power supply 11.
And CoSi 2 that is the first metal film 3 constituting the surface electrode
A bias voltage is applied between the layers, and electrons are emitted into vacuum from the low resistance film 5 where Ti / Pt does not exist.
【００２８】本実施形態の冷陰極電子源は、上述のとお
り第１の絶縁膜２に基板１であるシリコンウェハと格子
整合するＣａＦ2 層を用い、表面電極を構成する第１の
金属膜３に第１の絶縁膜２であるＣａＦ2 層と格子整合
するＣｏＳｉ2 層を用いることで、第１の絶縁膜２，第
１の金属膜３の形成にエピタキシャル成長を用いること
ができ、膜厚の均一性に優れた膜構造を容易に得ること
ができる。As described above, the cold cathode electron source of this embodiment uses the first metal film 3 constituting the surface electrode by using the CaF 2 layer lattice-matched to the silicon wafer as the substrate 1 for the first insulating film 2 as described above. By using a CoSi 2 layer lattice-matched with the CaF 2 layer as the first insulating film 2, epitaxial growth can be used to form the first insulating film 2 and the first metal film 3. A film structure with excellent uniformity can be easily obtained.
【００２９】シート抵抗低減用の低抵抗膜５は特に単結
晶金属である必要はなく、表面電極を構成する第１の金
属膜３と直接接触し形成され、十分な膜厚を有していれ
ばよい。Ｔｉ／Ｐｔの他に例えば、Ｃｒ／Ａｕなども用
いることができる。The low-resistance film 5 for reducing the sheet resistance does not need to be a single-crystal metal, but is formed in direct contact with the first metal film 3 constituting the surface electrode and has a sufficient film thickness. I just need. In addition to Ti / Pt, for example, Cr / Au or the like can be used.
【００３０】尚、低抵抗膜５は金属に限る必要はない。
例えばポリシリコン膜のような導電性のある半導体膜で
も、上部電極のシート抵抗が十分小さくなるように断面
積を大きくすればよい。The low resistance film 5 need not be limited to metal.
For example, even for a conductive semiconductor film such as a polysilicon film, the cross-sectional area may be increased so that the sheet resistance of the upper electrode is sufficiently reduced.
【００３１】次に、本発明の第２の実施形態の冷陰極電
子源を説明する。Next, a cold cathode electron source according to a second embodiment of the present invention will be described.
【００３２】図２は、第２の実施形態の冷陰極電子源の
概略構造を模式的に示す斜視図である。FIG. 2 is a perspective view schematically showing the schematic structure of the cold cathode electron source according to the second embodiment.
【００３３】図２を参照すると、本実施形態の冷陰極電
子源は基板１として用いるシリコンウェハのシート抵抗
低減用の低抵抗膜２５を付加する部分に予めエッチング
加工等により溝が形成されており、この溝部分を含めた
基板１全面に第１の絶縁膜２としてＣａＦ2 層がエピタ
キシャル成長により堆積されている。Referring to FIG. 2, in the cold cathode electron source of the present embodiment, a groove is previously formed by etching or the like in a portion where a low resistance film 25 for reducing sheet resistance of a silicon wafer used as a substrate 1 is added. On the entire surface of the substrate 1 including the groove, a CaF 2 layer is deposited as a first insulating film 2 by epitaxial growth.
【００３４】次いで低抵抗膜２５であるＴｉ／Ｐｔをリ
フトオフ法により溝部分にのみ残して形成して基板２１
の表面が平面になるようにし、その上に第１の金属膜３
としてＣｏＳｉ2 層をエピタキシャル成長により堆積し
ている。Next, Ti / Pt, which is a low-resistance film 25, is formed only in the groove portion by a lift-off method to form the substrate 21.
Of the first metal film 3
A CoSi 2 layer is deposited by epitaxial growth.
【００３５】この構成により、本実施形態の冷陰極電子
源は、最終的に得られる電子放出面を平坦にすることが
できる。With this configuration, the cold cathode electron source of the present embodiment can make the finally obtained electron emission surface flat.
【００３６】本実施形態の冷陰極電子源は、上述の材料
構成に限定されることなく、最終的に冷陰極電子源の表
面が平坦になり、且つ表面電極である第１の金属膜３あ
るいはシート抵抗低減用の低抵抗膜２５と基板１との間
に第１の絶縁膜２を挟む構造になり、且つ溝以外の部分
では第１の絶縁膜２と第１の金属膜３とが接している構
造であればよい。The cold cathode electron source of the present embodiment is not limited to the above-described material composition, but the surface of the cold cathode electron source is finally flattened and the first metal film 3 or the surface electrode, The first insulating film 2 is sandwiched between the low-resistance film 25 for reducing sheet resistance and the substrate 1, and the first insulating film 2 and the first metal film 3 are in contact with each other in portions other than the grooves. Any structure is acceptable.
【００３７】次に、本発明の第３の実施形態の冷陰極電
子源を説明する。Next, a cold cathode electron source according to a third embodiment of the present invention will be described.
【００３８】図３は、第３の実施形態の冷陰極電子源の
概略構造を模式的に示す斜視図である。FIG. 3 is a perspective view schematically showing a schematic structure of a cold cathode electron source according to the third embodiment.
【００３９】図３を参照すると、本実施形態の冷陰極電
子源は、基板１の上に、第２の絶縁膜６，第２の金属膜
７，第１の絶縁膜２及び第１の金属膜３がこの順序で堆
積されている。具体的には、基板１にシリコンウェハ
を、第１の絶縁膜２と第１の絶縁膜６にＣａＦ2 層を、
第１の金属膜３と第２の金属膜７にＣｏＳｉ2 層をそれ
ぞれ用いている。更に、第１の実施形態の場合と同様に
第１の金属膜３の上に、Ｔｉ／Ｐｔを用いてシート抵抗
低減用の低抵抗膜４がリフトオフ法により形成されてい
る。Referring to FIG. 3, a cold cathode electron source according to the present embodiment includes a second insulating film 6, a second metal film 7, a first insulating film 2, and a first metal film on a substrate 1. The films 3 are deposited in this order. Specifically, a silicon wafer is used for the substrate 1, a CaF 2 layer is used for the first insulating film 2 and the first insulating film 6,
CoSi 2 layers are used for the first metal film 3 and the second metal film 7, respectively. Further, a low-resistance film 4 for reducing sheet resistance is formed on the first metal film 3 using Ti / Pt by a lift-off method, as in the case of the first embodiment.
【００４０】本実施形態では、ＣｏＳｉ2 層を第２の金
属膜７に、ＣａＦ2 層を第１の絶縁膜２と第２の絶縁膜
６にそれぞれ用いたことで、第２の金属膜７に量子井戸
層が形成されている。In the present embodiment, the CoSi 2 layer is used for the second metal film 7, and the CaF 2 layer is used for the first insulating film 2 and the second insulating film 6. A quantum well layer is formed.
【００４１】量子井戸構造中では、エネルギ準位が量子
化され、電子の進行方向のエネルギのバラツキを狭める
ことができる。第２の金属膜７で構成される量子井戸層
を用いることで、第２の金属膜７に電極を導入し、制御
バイアス電源１２により第２の金属膜７の所望の電圧を
印加することで量子井戸層の電位を調整することがで
き、放出電子のエネルギの制御を行うことができる。In the quantum well structure, the energy level is quantized, so that the energy variation in the direction in which electrons travel can be reduced. By using a quantum well layer composed of the second metal film 7, an electrode is introduced into the second metal film 7, and a desired voltage of the second metal film 7 is applied by the control bias power supply 12. The potential of the quantum well layer can be adjusted, and the energy of emitted electrons can be controlled.
【００４２】尚、第２の絶縁膜６，第２の金属膜７及び
第１の絶縁膜２は上述の材料に限定されることなく、そ
れぞれに良好な結晶構造を有し且つ互いに格子整合する
材料を選択することにより第２の金属膜７に量子井戸層
が形成される。The second insulating film 6, the second metal film 7, and the first insulating film 2 are not limited to the above-mentioned materials, but each have a favorable crystal structure and are lattice-matched to each other. By selecting a material, a quantum well layer is formed in the second metal film 7.
【００４３】[0043]
【発明の効果】以上述べたとおり、本発明の冷陰極電子
源は、第１の金属膜（表面金属）及び第１の絶縁膜（絶
縁体）に互いに格子整合した結晶構造の単結晶材料を用
いることで、電子放出効率を向上させながら放出電子の
エネルギのバラツキ幅を抑制できるという効果得られ
る。As described above, the cold cathode electron source of the present invention comprises a single crystal material having a crystal structure lattice-matched to the first metal film (surface metal) and the first insulating film (insulator). By using this, it is possible to obtain the effect that the variation width of the energy of the emitted electrons can be suppressed while improving the electron emission efficiency.
【００４４】また、第１の絶縁膜、第１の金属膜をエピ
タキシャル成長により成膜できるので、層構造を簡便に
作製でき、更に構造（例えば、電子放出面形状等）の設
計自由度が向上するという効果が得られる。Further, since the first insulating film and the first metal film can be formed by epitaxial growth, the layer structure can be easily manufactured, and the degree of freedom in designing the structure (for example, the shape of the electron emission surface) is improved. The effect is obtained.
【００４５】更に、第２の金属膜を用いて電子源に量子
井戸層を導入するとともに、第２の金属膜に電極を導入
して量子井戸層の電位を調整することで、放出電子のエ
ネルギを制御することができるという効果も得られる。Further, by introducing a quantum well layer into the electron source using the second metal film and introducing an electrode into the second metal film to adjust the potential of the quantum well layer, the energy of the emitted electrons is increased. Can be controlled.
【図１】本発明の第１の実施形態の冷陰極電子源の概略
構造を示す斜視図である。FIG. 1 is a perspective view showing a schematic structure of a cold cathode electron source according to a first embodiment of the present invention.
【図２】本発明の第２の実施形態の冷陰極電子源の概略
構造を示す斜視図である。FIG. 2 is a perspective view showing a schematic structure of a cold cathode electron source according to a second embodiment of the present invention.
【図３】本発明の第３の実施形態の冷陰極電子源の概略
構造を示す斜視図である。FIG. 3 is a perspective view showing a schematic structure of a cold cathode electron source according to a third embodiment of the present invention.
【図４】従来の冷陰極電子源の概略構造を示す斜視図で
ある。FIG. 4 is a perspective view showing a schematic structure of a conventional cold cathode electron source.
１ 基板 ２ 第１の絶縁膜 ３ 第１の金属膜 ４，５，２５ 低抵抗膜 ６ 第２の絶縁膜 ７ 第２の金属膜 １１ 引き出しバイアス電源 １２ 制御バイアス電源 ４１ 金属あるいは半導体からなる基板 ４２ 絶縁体層 ４３ 表面金属層 DESCRIPTION OF SYMBOLS 1 Substrate 2 1st insulating film 3 1st metal film 4,5,25 Low resistance film 6 2nd insulating film 7 2nd metal film 11 Leading bias power supply 12 Control bias power supply 41 Substrate 42 made of metal or semiconductor Insulator layer 43 Surface metal layer
Claims (10)
の絶縁膜と第１の金属膜とが前記基板側からこの順序で
積層されており、前記第１の絶縁膜と前記第１の金属膜
とはいずれも単結晶で且つ互いに格子整合しており、更
に前記第１の金属膜が真空中に電子を放出する表面電極
を構成していることを特徴とする冷陰極電子源。1. A method according to claim 1, wherein a first substrate is formed on a metal or semiconductor substrate.
The insulating film and the first metal film are laminated in this order from the substrate side, and the first insulating film and the first metal film are both single crystal and lattice-matched to each other. A cold cathode electron source, wherein the first metal film constitutes a surface electrode for emitting electrons in a vacuum.
る請求項１記載の冷陰極電子源。2. The cold cathode electron source according to claim 1, wherein the substrate and the first insulating film are lattice-matched.
の絶縁膜，第２の金属膜，第１の絶縁膜及び第１の金属
膜が前記基板側からこの順序で積層されており、（ａ）
前記第１の絶縁膜及び前記第１の金属膜はいずれも単結
晶で且つ互いに格子整合しており、（ｂ）前記第１の金
属膜が表面電極を構成する表面金属膜であり、（ｃ）前
記第２の絶縁膜及び第２の金属膜は結晶である、ことを
特徴とする冷陰極電子源。3. The method according to claim 1, wherein a second substrate is formed on a metal or semiconductor substrate.
An insulating film, a second metal film, a first insulating film, and a first metal film are laminated in this order from the substrate side.
The first insulating film and the first metal film are both single crystal and lattice-matched to each other; (b) the first metal film is a surface metal film constituting a surface electrode; (c) The cold cathode electron source, wherein the second insulating film and the second metal film are crystals.
に有する請求項３記載の冷陰極電子源。4. The cold cathode electron source according to claim 3, further comprising an electrode for applying a voltage to the second metal film.
る請求項３又は４記載の冷陰極電子源。5. The cold cathode electron source according to claim 3, wherein the second metal film forms a quantum well layer.
り、第１の絶縁膜が単結晶ＣａＦ2 からなる請求項１乃
至５のいずれか１項に記載の冷陰極電子源。6. The cold cathode electron source according to claim 1, wherein the first metal film is made of single crystal CoSi 2 , and the first insulating film is made of single crystal CaF 2 .
する低抵抗膜を更に有する請求項１乃至６のいずれか１
項に記載の冷陰極電子源。7. The semiconductor device according to claim 1, further comprising a low-resistance film in contact with the first metal film forming the surface electrode.
Item 8. The cold cathode electron source according to item 1.
に低抵抗膜を有する請求項７記載の冷陰極電子源。8. The cold cathode electron source according to claim 7, wherein a low resistance film is provided on the back surface of the first metal film opposite to the electron emission surface.
を有する請求項７記載の冷陰極電子源。9. The cold cathode electron source according to claim 7, further comprising a low resistance film on the electron emission surface side of the first metal film.
坦である請求項１乃至８のいずれか１項に記載の冷陰極
電子源。10. The cold cathode electron source according to claim 1, wherein the surface of the first metal film on the electron emission surface side is flat.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17304699A JP3501019B2 (en) | 1999-06-18 | 1999-06-18 | Cold cathode electron source |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17304699A JP3501019B2 (en) | 1999-06-18 | 1999-06-18 | Cold cathode electron source |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001006529A true JP2001006529A (en) | 2001-01-12 |
| JP3501019B2 JP3501019B2 (en) | 2004-02-23 |
Family
ID=15953217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17304699A Expired - Fee Related JP3501019B2 (en) | 1999-06-18 | 1999-06-18 | Cold cathode electron source |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3501019B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006126383A1 (en) * | 2005-05-24 | 2006-11-30 | Konica Minolta Holdings, Inc. | Field emission electron source and method for manufacturing same |
| US7342276B2 (en) * | 2001-10-17 | 2008-03-11 | Freescale Semiconductor, Inc. | Method and apparatus utilizing monocrystalline insulator |
| WO2020225991A1 (en) * | 2019-05-08 | 2020-11-12 | 国立研究開発法人産業技術総合研究所 | Electron emitting element and electron microscope |
-
1999
- 1999-06-18 JP JP17304699A patent/JP3501019B2/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7342276B2 (en) * | 2001-10-17 | 2008-03-11 | Freescale Semiconductor, Inc. | Method and apparatus utilizing monocrystalline insulator |
| WO2006126383A1 (en) * | 2005-05-24 | 2006-11-30 | Konica Minolta Holdings, Inc. | Field emission electron source and method for manufacturing same |
| WO2020225991A1 (en) * | 2019-05-08 | 2020-11-12 | 国立研究開発法人産業技術総合研究所 | Electron emitting element and electron microscope |
| JP2020184453A (en) * | 2019-05-08 | 2020-11-12 | 国立研究開発法人産業技術総合研究所 | Electron emitting element and electron microscope |
| CN113795902A (en) * | 2019-05-08 | 2021-12-14 | 国立研究开发法人产业技术综合研究所 | Electron emitting element and electron microscope |
| JP7272641B2 (en) | 2019-05-08 | 2023-05-12 | 国立研究開発法人産業技術総合研究所 | Electron-emitting device and electron microscope |
| US12051557B2 (en) | 2019-05-08 | 2024-07-30 | National Institute Of Advanced Industrial Science And Technology | Electron emission device and electron microscope |
| CN113795902B (en) * | 2019-05-08 | 2025-02-25 | 国立研究开发法人产业技术综合研究所 | Electron emission element and electron microscope |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3501019B2 (en) | 2004-02-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0750419A (en) | Diamond field effect transistor | |
| TW478074B (en) | Hetero-junction bipolar transistor and its manufacturing method | |
| JPH11274561A (en) | Method of forming semiconductor layer epitaxially grown on metal layer and light emitting semiconductor device manufactured using this method | |
| JP3944970B2 (en) | Method for manufacturing silicon carbide semiconductor device | |
| JP3501019B2 (en) | Cold cathode electron source | |
| EP0825652B1 (en) | Ohmic electrode and method of forming the same | |
| US5232862A (en) | Method of fabricating a transistor having a cubic boron nitride layer | |
| US6939728B2 (en) | Method of fabricating silicon emitter with a low porosity heavily doped contact layer | |
| JPH04233277A (en) | Transistor provided with layer of cubic boron nitride | |
| JP3789064B2 (en) | Electron emitter | |
| JP3235805B2 (en) | Semiconductor crystal growth method | |
| US5081053A (en) | Method for forming a transistor having cubic boron nitride layer | |
| JP3260502B2 (en) | Electron-emitting device | |
| JP2004119168A (en) | Semiconductor device structure, electron emitter, and method of manufacturing semiconductor device structure | |
| JP3392507B2 (en) | Small field emission cathode device | |
| JPH02101784A (en) | Manufacture of quantum well fine wire and quantum well box and quantum well fine wire laser | |
| JPH0778581A (en) | Monochromatic electron beam source and method of manufacturing the same | |
| JPH06120164A (en) | Ohmic electrode | |
| JP2804714B2 (en) | Method for manufacturing visible light semiconductor laser device | |
| JP2001338568A (en) | Electronic element | |
| JPS6154263B2 (en) | ||
| JP2001267268A (en) | Method for manufacturing semiconductor silicide film | |
| JP2804736B2 (en) | Visible light semiconductor laser device | |
| JP2001102632A (en) | Compound semiconductor device and manufacturing method therefor | |
| JP3121671B2 (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20031111 |
|
| LAPS | Cancellation because of no payment of annual fees |