JP2000354258A - Decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a motion compensation circuit and a decoder that can decode a coded image of a plurality of channels at a high-speed. SOLUTION: A motion compensation section 100 provided to this decoder includes a block 20 coping with a left eye image and a block 30 coping with a right eye image. The left eye block 20 conducts motion compensation arithmetic processing on the basis of left eye image (reference data) read from a memory 22 and difference data. The memory 22 and a memory 32 of the right eye block 30 store the decoded left eye image data as a result of the motion compensation arithmetic processing. The right eye block executes the motion compensation arithmetic processing according to the difference data on the basis of the right eye image (reference data) stored in the memory 32 and the transferred left eye decoded image data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder,
More specifically, the present invention relates to a decoder for reproducing a stereoscopic image composed of a plurality of channels by performing a motion compensation operation process.

[0002]

2. Description of the Related Art Conventionally, as a method for compressing and encoding moving images, the MPEG standard (Moving Picture Image Coding)
Experts Group).

[0003] The MPEG2 standard, which is one of the MPEG standards, has a feature that coded information can be exchanged between different applications. In particular, at present, an encoder compliant with the MPEG2 standard and a corresponding decoder have been developed. Is underway.

FIG. 36 is a diagram for explaining a process of encoding (decoding) a stereoscopic image conforming to MPEG2.
Referring to FIG. 36, MVP (Multi ViP
ew Profile) method will be described. Note that the arrows in the figure indicate the relationship between the screen to be coded and the screen to be referred to for coding. In FIG. 36, the left-eye screen is composed of an I picture, a P picture, and a B picture (hereinafter, a symbol I for an I picture, a symbol P for a P picture, and a symbol B for a B picture). Attached).

[0005] For example, the left-eye screen I0 encodes only information in a frame without using a reference image. The left-eye screen P0 is a screen subsequent to the I0 picture, and performs encoding using the I0 picture corresponding to the left eye as a reference screen. Left eye screen B0, B1, B2, ...
Performs encoding using left and right I-pictures and P-pictures corresponding to the left and right eyes.

[0006] The right eye screen is composed of P pictures and B pictures. The right eye screen Pr0 is the left eye screen I0.
Is used as a reference screen for encoding. Right eye screen Br
1 performs encoding using the left-eye screen B0 and the P picture Pr0. The right-eye screens Br2, Br3,... Are encoded using the corresponding left-eye screen and the B picture one frame before.

As shown in the figure, in the MPEG2 MVP method, a left-eye image is encoded using a left-eye image and a right-eye image is encoded using a right-eye image and a left-eye image. Do.

On the decoder side receiving such encoded image data, the difference data, which is the difference between certain pixel data on the screen at a certain time and certain pixel data on the screen one frame before, is used as the pixel of the reference screen. A motion compensation calculation process is performed to add the data (the above-described decoded pixel data corresponding to the previous frame of the frame) to the data. Thereby, the right-eye image and the left-eye image are decoded.

FIG. 37 is a diagram showing a configuration of a conventional motion compensator 900 for decoding the stereoscopic image shown in FIG. The motion compensation unit 900 illustrated in FIG. 37 includes a left-eye block 910 for decoding a left-eye image and a right-eye block 920 for decoding a right-eye image.

The left-eye block 910 includes a frame memory 902, a motion compensation operation unit 906, a memory control unit 904,
And a gate 908. The frame memory 902 is
Stores left eye image data.

The memory control unit 904 includes a frame memory 9
Address control accompanying the read (read) operation / write (write) operation of No. 02 is performed. The motion compensation calculation unit 906 includes:
A motion compensation calculation process for adding difference data to reference data (decoded left-eye image data) stored in the frame memory 902 is performed. Thereby, the left eye image is decoded. The decoded left-eye image is stored in the frame memory 902.

The right-eye block 920 includes a frame memory 912, a motion compensation operation unit 916, a memory control unit 914,
And a gate 918. The frame memory 912 is
Stores right eye image data.

The memory control unit 914 includes the frame memory 9
Twelve read operations / write operations and address control accompanying the frame memory 902 read operation are performed.
The gate 918 outputs an address signal for the frame memory 902 generated by the memory control unit 914 to the address line AL.
Output to INE. Gate 908 is connected to address line ALI.
An address signal on the NE is received as an input. The frame memory 902 performs a memory operation in accordance with an output of the memory control unit 904 or an address input to the gate 908.

When a data transfer is requested from the right-eye block 920, data is read from the frame memory 902, and the data is read from the right-eye block 9 via the data line DLINE.
20. The motion compensation operation unit 916 decodes the right-eye image using the reference data for the left eye transferred from the frame memory 902, the reference data for the right eye read from the frame memory 912, and the difference data.
The decoded right-eye image is stored in the frame memory 912.

With this configuration, a stereoscopic image can be restored and reproduced from a coded image of two channels (right and left eyes).

[0016]

However, in the conventional decoder described above, it is necessary to decode the right-eye image data in addition to the memory operation period for reading the left-eye and right-eye images as reference data. Further, a memory operation period for reading a left-eye image is required. Therefore, there is a problem that the time required for decoding is limited by the operation speed of the memory.

In particular, encoding is performed using signals of a plurality of channels (three or more channels) and information of another channel (a specific basic channel) in addition to data corresponding to each channel as in the above-described case. Assuming the case, while it is possible to compress and transmit a large amount of information, there arises a problem that the processing time for decoding increases during decoding.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a decoder which can decode a coded signal of a plurality of channels at a high speed to reproduce a stereoscopic image. Is to provide.

[0019]

A decoder according to one aspect of the present invention decodes encoded image data of a first channel and a second channel to reproduce a stereoscopic image. A motion compensator based on a first memory corresponding to the first channel, the first reference data read from the first memory, and the first difference data. A first arithmetic circuit for decoding image data of one channel,
The decoded image data output from the arithmetic circuit is stored in the first memory, and the decoded image data is stored in the first memory according to the first motion vector.
A first control circuit for reading the decoded first channel image data, which is the reference data of the first channel, from the first memory;
By performing motion compensation calculation processing based on a second memory corresponding to the second channel, and second reference data and second difference data read from the second memory, image data of the second channel is obtained. A second arithmetic circuit that decodes the image data, and stores the decoded image data output from the first arithmetic circuit and the decoded image data output from the second arithmetic circuit in a second memory; A second control circuit for reading the decoded first channel image data and the decoded second channel image data, which are the second reference data, from the second memory according to the second motion vector; And

[0020] Preferably, the first channel corresponds to a left-eye image and the second channel corresponds to a right-eye image.

Preferably, each of the first memory and the second memory stores a plurality of frames of image data, and the first control circuit and the second control circuit store the decoded first channel data. The image data is stored at the same position in the same frame in the first memory and the second memory, and is stored at the same position.

In particular, the first memory includes a first bank and a second bank that can be accessed independently of each other, and the second memory has a third bank that can be accessed independently of each other. A bank and a fourth bank. More specifically, each of the first bank, the second bank, the third bank, and the fourth bank has an area for storing image data for three frames.

A decoder according to a further aspect of the present invention is a decoder that reproduces a stereoscopic image by decoding encoded basic channel image data and encoded multiple channel image data, respectively. So,
A first motion compensation processing circuit corresponding to the basic channel;
A plurality of second motion compensation processing circuits provided corresponding to each of the plurality of channels, wherein the first motion compensation processing circuit includes a first memory for storing image data;
A first arithmetic circuit for decoding image data of the basic channel by performing a motion compensation arithmetic process based on the first reference data and the first difference data read from the memory of the first arithmetic circuit; The decoded image data to be output is stored in the first memory, and the decoded basic channel image data, which is the first reference data, is read out from the first memory according to the first motion vector. Each of the second motion compensation processing circuits includes a second memory for storing image data, a second reference data read from the second memory, and a second difference data. A second arithmetic circuit for decoding the image data of the corresponding channel by performing the motion compensation arithmetic processing based on the first and second arithmetic operations;
The decoded image data output from the arithmetic circuit and the decoded image data output from the second arithmetic circuit
And reads out, from the second memory, decoded image data of the decoded basic channel and decoded image data of the corresponding channel, which are the second reference data, according to the second motion vector. 2 control circuits.

Preferably, each of the first memory and the second memory stores a plurality of frames of image data, and the first control circuit and the second control circuit store the decoded image data of the basic channel. Is stored in the first memory and the second memory at relatively the same position in the same frame.

[0025]

[First Embodiment] A decoder 1000 for a stereoscopic image according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a schematic block diagram illustrating an overall configuration of a decoder 1000 according to Embodiment 1 of the present invention. The decoder 1000 is a 2-channel image data encoded according to MPEG2 (right eye, left eye)
Receive.

Referring to FIG. 1, a decoder 1000 includes a buffer 2, a variable length decoder 4, an inverse quantizer 6, an inverse DCT unit 8, a motion compensation unit 100, a format converter 12, and a digital / analog ( D / A) converter 14 is provided. The buffer 2 stores MPEG-compressed data (encoded data) sent from the transmission side. The variable-length decoder 4 outputs variable-length encoded data (variable-length codes of motion vectors and variable-length codes of transform coefficients) output from the buffer 2.
Is decrypted. The inverse quantizer 6 inversely quantizes the transform coefficients (quantized DCT coefficients) output from the variable length decoder 4 and transforms them into DCT coefficients (DCT: discrete cosine transform). The inverse DCT 8 generates the DDC generated by the inverse quantizer 6.
An inverse discrete cosine transform process is performed on the CT coefficients to generate difference data in units of one macroblock.

The motion compensator 100 decodes the image data based on the difference data output from the inverse DCT unit 8 and the motion vector output from the variable length decoder 4.

The decoded image data output from the motion compensating unit 100 is supplied to a format converter 12
/ A converter 14. In the D / A converter 14,
The input digital signal is converted into an analog signal and a video signal is output. Based on this, a stereoscopic image is reproduced.

FIG. 2 is a block diagram showing a specific configuration of the motion compensation unit 100 shown in FIG. Referring to FIG. 2, motion compensation section 100 includes a left-eye block 20 corresponding to a left-eye image and a right-eye block 30 corresponding to a right-eye image. The left-eye block 20 includes a frame memory 22, a memory control unit 24, a motion compensation operation unit 26, and a data output unit 28. The right eye block 30 is a frame memory 3
2, including a memory control unit 34, a motion compensation operation unit 36, and a data output unit 38. Frame memory 22 is L memory 2
2, and the frame memory 32 is referred to as an R memory 32.

The L memory 22 stores pixel data of a plurality of frames. L memory 22 is composed of bank B0 # L and bank B1 # L. Bank B0♯L, B1
♯L operates in parallel. Each of the banks B0 # L and B1 # L includes 16 SRAMs. One SRA
M is assigned corresponding to one pixel. Each bank performs a read operation / write operation collectively for 16 pixels in the horizontal direction. That is, at the same address, 1
Six pixels are read / written at a time.

The R memory 32 stores pixel data of a plurality of frames. R memory 32 includes banks B0 # R and B1 # R. These configurations correspond to bank B0
♯L and bank B1♯L.

The memory controller 24 performs a read operation / read operation based on the motion vector output from the variable length decoder 4 and the like.
The address of the L memory 22 to be written is specified.

The motion compensation calculating section 26 has a 16 pixel extracting section 4
0 and an adder 41 are included. The 16-pixel extracting unit 40 outputs a macroblock unit MB from each of the banks B0♯L and B1♯L.
Is performed to extract data of continuous 16 pixels corresponding to. The extracted data becomes reference data (reference image). More specifically, as shown in FIG. 3, the read operation is repeated twice for each bank. This allows
For each bank, data of 16 pixels in a certain horizontal direction (assuming address = A) and data of 16 pixels in a horizontal direction (address = A + 1) continuous with the data are read. 16
The pixel extracting unit 40 extracts data of continuous 16 pixels (hatched portion in the drawing) from the read data of continuous 32 pixels. In the following description, a read operation for extracting reference data is referred to as a reference data read operation.

The adder 41 adds the reference data output from the 16-pixel extracting unit 40 and the difference data output from the inverse DCT unit 8 to decode the image data. Note that the inverse D
If the data output from the CT unit 8 corresponds to an intra-frame prediction code (I picture), the data is output as decoded data without adding difference data. The decoded image data is stored in the L memory 22. The decoded image data is output to the subsequent stage via the data output unit 28.

In the right-eye block 30, the motion compensation calculation unit 36 performs a motion compensation calculation process for decoding the image data by adding the reference data and the difference data.
The motion compensation calculation unit 36 includes a 16 pixel extraction unit 42 and an addition unit 43. These functions are the same as those of the 16-pixel extracting unit 40 and the adding unit 41, respectively. The decoded right-eye image data is stored in the R memory 32.
The decoded right-eye image data is output to the subsequent stage via the data output unit 38.

The memory control unit 34 specifies an address of the R memory 32 to be read / written based on a motion vector or the like. In the right eye block 30,
The decoded right-eye image data or the decoded left-eye image data stored in the R memory 32 is used as reference data. Therefore, the R memory 32 is connected to the data line DLIN.
The output of the motion compensation operation unit 26 is received via E1. As a result, the image data decoded by the left-eye block 20 is simultaneously written into the L memory 22 and the R memory 32 at relatively the same position within the same frame.

Here, a specific configuration of the memory control unit 24 according to the first embodiment of the present invention will be described with reference to FIG. FIG. 4 is a diagram showing a specific configuration of the memory control unit 24 according to the first embodiment of the present invention. Referring to FIG.
The memory control unit 24 controls the block 6 corresponding to the bank B0 @ L.
0 and a block 62 corresponding to the bank B1 @ L. The block 60 includes a reference address generation circuit 50, a computing unit 51,
Write address generation circuit 52, display address generation circuit 5
3 and the selector 54.

Reference address generation circuit 50 and operation unit 5
1 is arranged to read the decoded left-eye image data stored in the bank B0 # L. The reference address generation circuit 50 generates an address (reference address) AR1 for the first reference data read operation based on a motion vector received from the outside. The arithmetic unit 51 generates a reference address AR2 (= AR1 + 1) corresponding to the second reference data read operation by adding 1 to the output of the reference address generation circuit 50.

The write address generation circuit 52 generates an address (write address) for writing the decoded left-eye image data to the bank B0 # L. The display address generation circuit 53 generates an address (display address) for reading display data (decoded left-eye image data) to be displayed from the bank B0 # L. The selector 54 outputs one of the reference addresses AR1, AR2, the write address, or the display address in a predetermined order in synchronization with the synchronization signal CLK. The selector 54 sequentially outputs four addresses within one cycle (4 × CLK). The selector 54 repeats such an operation. Thus, the read operation / write operation of bank B0 # L is controlled.

The block 62 includes a reference address generation circuit 5
5, an arithmetic unit 56, a write address generation circuit 57, a display address generation circuit 58, and a selector 59.

Reference address generation circuit 55 and operation unit 5
No. 6 is arranged to read the decoded left-eye image data stored in the bank B1 @ L. The reference address generation circuit 55 generates a reference address AR3 for the first reference data read operation based on a motion vector received from the outside. Arithmetic unit 56 adds 1 to the output of reference address generation circuit 55 to obtain reference address AR4 (= A) for the second reference data read operation.
R3 + 1).

The write address generation circuit 57 generates a write address for writing the decoded left-eye image data to the bank B1 # L. Display address generation circuit 58
Generates a display address for reading display data to be displayed (decoded left-eye image data) from the bank B1 # L. The selector 59 synchronizes with the synchronization signal CLK and, in a predetermined order, sets the reference addresses AR3, AR3
4. Output one of the write address or the display address. One cycle (4 × CL
In K), four addresses are sequentially output. Selector 59 repeatedly performs such an operation. This allows
Read operation / write operation of bank B1 # L is controlled.

FIG. 5 is a flowchart for explaining the operation of the L memory 22 based on the control of the memory control unit 24. In the drawing, symbols CLK1 to CLK4 represent synchronization signals. The L memory 22 sets CLK1 to CLK4 (4 clocks in total) as one cycle and performs steps S1 to S4.
Is repeated for a total of four steps.

First, in order to extract left-eye image data serving as reference data, two images are output between two clocks (CLK1, CLK2).
The reference data read operation is performed twice. Specifically, data of 16 pixels out of 32 pixels is read to extract reference data (step S1). Then, the above 3
The data of the remaining 16 pixels is read out of the two pixels (step S2). The 16-pixel extracting unit 40 receiving these data extracts 16-pixel data used as reference data from the 32-pixel data.

At the third clock (CLK3), the left-eye image data decoded by the motion compensation calculation process using the reference data read several cycles before is written (step S3). Subsequently, the fourth clock (CLK
In 4), the decoded left-eye image data as display data is read (step S4).

Next, a specific configuration of the memory control unit 34 according to the first embodiment of the present invention will be described with reference to FIG.
FIG. 6 shows memory control unit 3 according to the first embodiment of the present invention.
4 is a diagram showing a specific configuration of FIG. Referring to FIG. 6, memory control unit 34 includes a block 90 corresponding to bank B0 @ R and a block 92 corresponding to bank B1 @ R.

The block 90 includes a reference address generation circuit 7
0, 71, computing units 72, 73, display address generating circuit 7
4, including write address generation circuits 75 and 76 and selectors 77 # 1 to 77 # 3 and 78.

Reference address generation circuit 70 and operation unit 7
2 is arranged to read the decoded right-eye image data stored in the bank B0 @ R. The reference address generation circuit 70 generates a reference address AR5 corresponding to the first reference data read operation based on a motion vector received from the outside. The arithmetic unit 72 adds 1 to the output of the reference address generation circuit 70, thereby obtaining the reference address AR6 corresponding to the second reference data read operation.
(= AR5 + 1).

Reference address generation circuit 71 and arithmetic unit 7
No. 3 is arranged to read the decoded left-eye image data stored in the bank B0 @ R. The reference address generation circuit 71 generates a reference address AR7 corresponding to the first reference data read operation based on a motion vector received from the outside. Arithmetic unit 73 adds 1 to the output of reference address generation circuit 71 to obtain reference address AR8 corresponding to the second reference data read operation.
(= AR7 + 1). Reference address AR7, A
By R8, the decoded pixel data of the left-eye image stored in the R memory 32 is read.

The display address generation circuit 74 generates a display address for reading the decoded right-eye image data as display data from the bank B0 # R. The write address generation circuit 75 generates a write address AR for writing the decoded right-eye image data to the bank B0 @ R.
9 is generated. The write address generation circuit 76 decodes the decoded left-eye image data (transferred from the left-eye block 20).
Write address A for writing data to bank B0 @ R
Generates R10.

Selector 77 # 1 outputs either reference address AR5 or AR7 in response to synchronization signal CLK. Selector 77 # 2 outputs one of reference addresses AR6 or AR8 in response to synchronization signal CLK. Selector 77 # 3 outputs synchronization signal CLK
In response to the display address or the write address AR1.
Either 0 is output.

Selector 78 outputs any one of selectors 77 # 1-77 # 3 and write address AR9 in a predetermined order in synchronization with synchronization signal CLK. The selector 78 sequentially outputs four addresses within one cycle (4 × CLK). Selector 78 repeatedly performs such an operation. Based on the output of selector 78, bank B0 # R performs a read operation / write operation.

The block 92 includes a reference address generation circuit 8
0, 81, computing units 82, 83, display address generating circuit 8
4, including write address generation circuits 85 and 86 and selectors 87 # 1 to 87 # 3 and 88.

Reference address generation circuit 80 and operation unit 8
No. 2 is arranged to read the decoded right-eye image data stored in the bank B1 @ R. The reference address generation circuit 80 generates a reference address AR11 for the first reference data read operation based on a motion vector received from the outside. Arithmetic unit 82 adds 1 to the output of reference address generation circuit 80 to obtain address AR12 (=) corresponding to the second reference data read operation.
AR11 + 1).

Reference address generation circuit 81 and arithmetic unit 8
No. 3 is arranged to read the decoded left-eye image data stored in the bank B1 @ R. The reference address generation circuit 81 generates a reference address AR13 corresponding to the first reference data read operation. Arithmetic unit 83
Generates a reference address AR14 (= AR13 + 1) corresponding to the second reference data read operation by adding 1 to the output of the reference address generation circuit 81. The decoded pixel data of the left-eye image stored in the R memory 32 is read based on the reference addresses AR13 and AR14.

The display address generating circuit 84 generates a display address for reading the decoded right-eye image data, which is display data, from the bank B1 @ R. The write address generation circuit 85 writes a write address AR for writing the decoded right-eye image data to the bank B1 @ R.
Generate 15. The write address generation circuit 86 generates a write address AR16 for writing the decoded left-eye image data (transferred from the left-eye block 20) to the bank B1 @ R.

Selector 87 # 1 outputs either reference address AR11 or AR13 in response to synchronization signal CLK. Selector 87 # 2 outputs one of reference addresses AR12 and AR14. Selector 87 # 3 outputs one of display address and write address AR16.

Selector 88 outputs any one of selectors 87 # 1-87 # 3 and write address AR15 in a predetermined order in synchronization with synchronization signal CLK. Within one cycle (4 × CLK), 4
Addresses are sequentially output. The selector 88 repeatedly performs such an operation. Based on the output of selector 88, bank B1 # R performs a read operation / write operation.

FIG. 7 is a flowchart for explaining the operation of the R memory 32 based on the control of the memory control unit 34. In the figure, symbols CLK1 to CLK4 represent synchronization signals. The R memory 32 repeats the processing of steps S5 to S6 or the processing of steps S7 to S8, the processing of step S9 or step S10, and the operation of step S11 for a total of four steps with CLK1 to CLK4 (four clocks in total) as one cycle. .

First, when performing the processing of steps S5 and S6, in order to extract the right-eye image data serving as reference data, two clocks (CLK1, CLK
In 2), two reference data read operations are performed. Specifically, data of 16 pixels out of 32 pixels is read to extract reference data (step S5). Subsequently, data of the remaining 16 pixels out of the 32 pixels is read (step S6).

On the other hand, when performing the processing of steps S7 and S8, the left-eye image data serving as reference data is taken out for two clocks (CLK1, CLK2).
In 2), two reference data read operations are performed. Specifically, in order to extract left-eye image data, data of 16 pixels out of the corresponding 32 pixels is read (Step S).
7). Subsequently, data of the remaining 16 pixels out of the 32 pixels is read (step S8).

At the third clock (CLK3), display data to be displayed (decoded right-eye image data) is read (step S9). Both the right-eye block 30 and the left-eye block 20 read data at relatively the same position in the same frame as display data.

In the R memory 32, while display data is read from one bank, the other bank performs a write operation. Therefore, the decoded left-eye image data transferred from the left-eye block 20 is written to the other bank (step S10). The transferred left-eye image data is written at the same position in the same frame in the right-eye block 30 and the left-eye block 20.

At the fourth clock (CLK4), the right-eye image data decoded by the motion compensation operation using the reference data read several cycles earlier is written (step S11). The decoded right-eye image data and the decoded left-eye image data are written at the same position in the same frame in the right-eye block 30 and the left-eye block 20, respectively.

The left eye block 20 and the right eye block 30
Although the read timing of the display data is different between the two, the display timing is adjusted by, for example, arranging a flip-flop on the read path.

Here, in order to explain the effectiveness of the present invention,
Another example of the motion compensation unit will be described. FIG. 8 is a diagram illustrating another example of the motion compensation unit that decodes a right-eye image using a left-eye image. The motion compensation unit 500 illustrated in FIG. 8 includes a left-eye block 520 corresponding to a left-eye image and a right-eye block 530 corresponding to a right-eye image. The left-eye block 520 includes a frame memory 522, a memory control unit 52
4, including a motion compensation calculation unit 526, a gate 596, and a data output unit 528. The right-eye block 530 includes a frame memory 532, a memory control unit 534, a motion compensation operation unit 536, a gate 598, and a data output unit 538. The frame memory 522 is referred to as an L memory 522, and the frame memory 532 is referred to as an R memory 532.

L memory 522 is composed of bank B2 # L and bank B3 # L. R memory 532 is composed of bank B2 @ R and bank B3 @ R. The basic configuration of bank B2 @ L and bank B3 @ L
0L and the same as bank B1L. Bank B2
The basic structure of {R and bank B3} R is bank B0
Same as R and bank B1 @ R.

The motion compensation calculation section 526 includes a 16 pixel extraction section 540 and an addition section 541. 16 pixel take-out unit 54
The basic configuration of 0 and the adder 541 is the 16 pixel take-out unit 4
0 and the same as the adder 41. Motion compensation calculation unit 53
Reference numeral 6 includes a 16-pixel extracting unit 542 and an adding unit 543. The basic configurations of the 16-pixel extracting unit 542 and the adding unit 543 are the same as those of the 16-pixel extracting unit 42 and the adding unit 43.

The memory control unit 524 specifies an address of the L memory 522 to be read / written based on a motion vector or the like. On the other hand, the memory control unit 5
34 performs an address control associated with a read operation / write operation of the R memory 532 and an address control associated with a read operation of the L memory 522 based on a motion vector or the like.

The address AR0 corresponding to the L memory 522 output from the memory control unit 534 is input to the gate 598. The gate 598 connects the address AR0 to the address line A.
Output to LINE1. On the other hand, gate 596 receives address AR0 on address line ALINE1, and outputs the same to L memory 522. The L memory 522 stores the address AR
Data is read based on 0. The read data is transferred to the right-eye block 53 via the data line DLINE2.
0 is transferred to the motion compensation calculator 536. The right-eye block 530 uses the transferred data as reference data.

The specific configuration of the memory control unit 524 is shown in FIG.
This will be described with reference to FIG. FIG. 9 is a diagram showing a specific configuration of the memory control unit 524. Referring to FIG. 9, memory control unit 524 includes a block 560 corresponding to bank B2 @ L and a block 570 corresponding to bank B3 @ L. Block 5
Reference numeral 60 denotes a reference address generation circuit 563, a computing unit 564,
Non-selection circuits 561 and 562, write address generation circuit 5
65, display address generating circuit 567 and selector 56
8 inclusive.

Reference address generating circuit 563 and arithmetic unit 564 are arranged to read the decoded left-eye image data stored in bank B2 # L. The reference address generation circuit 563 generates a reference address AR50 for the first reference data read operation based on a motion vector received from the outside. Arithmetic unit 564 generates reference address AR51 (= AR50 + 1) corresponding to the second reference data read operation by adding 1 to the output of reference address generation circuit 563.

Write address generation circuit 565 generates a write address for writing the decoded left-eye image data to bank B2 # L. Display address generation circuit 5
67 generates a display address for reading the decoded left-eye image data as display data from the bank B2 @ L.

The selector 568 synchronizes the reference addresses AR50, AR5 in a predetermined order in synchronization with the synchronization signal CLK.
1. Output one of the output of the non-selection circuit 561, the output of the non-selection circuit 562, the write address or the display address. One cycle (6 × C
LK), the outputs of these six circuits are sequentially selected. Selector 568 repeatedly performs such an operation. When the outputs of the non-selection circuits 561 and 562 are selected, there is no output from the selector 568. At this timing, the bank B2 @ L is set to the right-eye block 530.
Of the reference data read operation is received.

The block 570 includes a reference address generation circuit 573, a computing unit 574, non-selection circuits 571 and 572, a write address generation circuit 575, and a display address generation circuit 5.
77 and a selector 578.

Reference address generating circuit 573 and arithmetic unit 574 are arranged to read the decoded left-eye image data stored in bank B3 # L. The reference address generation circuit 573 generates a reference address AR52 for the first reference data read operation based on a motion vector received from the outside. The arithmetic unit 574 generates a reference address AR53 (= AR52 + 1) corresponding to the second reference data read operation by adding 1 to the output of the reference address generation circuit 573.

The write address generation circuit 575 generates a write address for writing the decoded left-eye image data in the bank B3 @ L. Display address generating circuit 57
Numeral 7 generates a display address for reading the decoded left-eye image data as display data from the bank B3 # L.

The selector 578 synchronizes the reference addresses AR52, AR5 in a predetermined order in synchronization with the synchronization signal CLK.
3. Output one of the output of the non-selection circuit 571, the output of the non-selection circuit 572, the write address or the display address. One cycle (6 × C
LK), the outputs of these six circuits are sequentially selected. Selector 578 repeatedly performs such an operation. When the outputs of the non-selection circuits 571 and 572 are selected, there is no output from the selector 578. At this timing, the bank B3 @ L is set to the right-eye block 530.
Of the reference data read operation is received.

The specific configuration of the memory control unit 534 is shown in FIG.
Explanation will be made using 0. FIG. 10 is a diagram showing a specific configuration of the memory control unit 534. Referring to FIG. 10, memory control unit 534 includes bank B2 @ R and L memory 522
Block 580 corresponding to bank B2 @ L and bank B3
ＢR and L memory 522 and a block 590 corresponding to bank B3♯L. The block 580 includes reference address generation circuits 581 and 583, arithmetic units 582 and 584, a write address generation circuit 586, and a display address generation circuit 58.
7 and a selector 588.

The reference address generation circuit 581 and the operation unit 582 are arranged to read the decoded right-eye image data stored in the bank B2 @ R. The reference address generation circuit 581 generates a reference address AR54 for the first reference data read operation based on a motion vector received from the outside. Arithmetic unit 582 generates address AR55 (= AR54 + 1) corresponding to the second reference data read operation by adding 1 to the output of reference address generation circuit 581.

Reference address generating circuit 583 and arithmetic unit 584 are arranged to read the decoded left-eye image data stored in bank B2 # L. The reference address generation circuit 583 generates a reference address AR56 corresponding to the first reference data read operation based on a motion vector received from the outside. Arithmetic unit 584 generates reference address AR57 (= AR56 + 1) corresponding to the second reference data read operation by adding 1 to the output of reference address generation circuit 583. Based on the reference addresses AR56 and AR57, the decoded pixel data of the left-eye image is read from the bank B2 # L of the L memory 522 and transferred to the right-eye block 530.

Write address generating circuit 586 generates a write address for writing the decoded right-eye image data to bank B2 # R. The display address generating circuit 587 generates a display address for reading the decoded right-eye image data, which is display data, from the bank B2 # R. The selector 588 supplies the reference addresses AR54 and AR5 in a predetermined order in synchronization with the synchronization signal CLK.
5. Output one of AR56, AR57, write address or display address. The selector 588 sequentially outputs six signals within one cycle (6 × CLK). Selector 588 repeatedly performs such an operation. Thereby, the read operation of bank B2 @ R /
Write operation, or bank B2 in L memory 522
The read operation of ♯L is controlled.

The block 590 includes reference address generation circuits 591 and 593, arithmetic units 592 and 594, a write address generation circuit 596, a display address generation circuit 597, and a selector 598.

Reference address generating circuit 591 and arithmetic unit 592 are arranged to read the decoded right-eye image data stored in bank B3 # R. The reference address generation circuit 591 generates a reference address AR58 for the first reference data read operation based on a motion vector received from the outside. The arithmetic unit 592 generates an address AR59 (= AR58 + 1) corresponding to the second reference data read operation by adding 1 to the output of the reference address generation circuit 591.

Reference address generating circuit 593 and arithmetic section 594 are arranged to read the decoded left-eye image data stored in bank B3 # L. The reference address generation circuit 593 generates a reference address AR60 corresponding to the first reference data read operation. The arithmetic unit 594 generates a reference address AR61 (= AR60 + 1) corresponding to the second reference data read operation by adding 1 to the output of the reference address generation circuit 593. Based on the reference addresses AR60 and AR61, the decoded pixel data of the left-eye image is read from the bank B3 # L of the L memory 522 and transferred to the right-eye block 530.

Write address generation circuit 596 generates a write address for writing the decoded right-eye image data to bank B3 # R. The display address generation circuit 597 generates a display address for reading the decoded right-eye image data as display data from the bank B3 # R. The selector 598 outputs the reference addresses AR58, AR5 in a predetermined order in synchronization with the synchronization signal CLK.
9. Output one of AR60, AR61, write address or display address. The selector 598 sequentially outputs six signals within one cycle (6 × CLK). Selector 598 repeatedly performs such an operation. As a result, the read operation of bank B3 @ R /
Write operation or bank B3 in L memory 522
The read operation of ♯L is controlled.

FIG. 11 is a flowchart for explaining the operation of L memory 522 based on the control of memory control unit 524. In the drawing, symbols CLK1 to CLK6 represent synchronization signals. The L memory 522 includes CLK1 to CLK
6 (6 clocks in total) as one cycle, and step S
The operation of a total of 6 steps consisting of 20 to S25 is repeated.
First, to extract the left-eye image data as reference data,
Two reference data read operations are performed between two clocks (CLK1, CLK2). Specifically, data of 16 pixels out of 32 pixels is read to extract reference data (step S20). Subsequently, data of the remaining 16 pixels out of the 32 pixels is read (step S).
21).

Between the following two clocks (CLK3, CLK4)
In response to a request from the right-eye block 530, the left-eye block 520 performs two reference data read operations. Specifically, data of 16 pixels out of 32 pixels is read (step S22). Subsequently, the aforementioned 32
Data of the remaining 16 pixels is read from the pixels (step S23). The read data is transferred to the right-eye block 530.

At the fifth clock (CLK5), the motion compensating operation is performed using the reference data read several cycles before and the decoded left-eye image data is written (step S24). The following sixth clock (CLK
In 6), the decoded left-eye image data, which is the display data, is read (step S25).

FIG. 12 is a flowchart for explaining the operation of R memory 532 based on the control of memory control unit 534. In the drawing, symbols CLK1 to CLK6 represent synchronization signals. The R memory 532 includes CLK1 to CLK
6 (6 clocks in total) as one cycle, and step S
The operation of a total of 6 steps consisting of 26 to S31 is repeated.
First, to extract the right-eye image data as reference data,
Two reference data read operations are performed between two clocks (CLK1, CLK2). Specifically, 1 out of 32 pixels
Data of six pixels is read (step S26). Subsequently, data of the remaining 16 pixels out of the 32 pixels is read (step S27).

Between the following two clocks (CLK3, CLK4)
In, left-eye image data serving as reference data is read in the left-eye block 520 and transferred to the right-eye block 530. During this period, no memory operation is performed (steps S28 and S29).

At the fifth clock (CLK5), the motion compensating operation is executed using the reference data read several cycles before and the right-eye image data decoded is written (step S30). The decoded right-eye image data and the decoded left-eye image data are divided into a right-eye block 5
30 and the left eye block 520 are written at relatively the same position in the same frame.

At the subsequent sixth clock (CLK6), the decoded right-eye image data as display data is read (step S31). Note that both the right-eye block 530 and the left-eye block 520 read data at relatively the same position in the same frame as display data.

Based on the above description, a comparison between the motion compensation unit 100 and the motion compensation unit 500 will be made with reference to FIGS. FIG. 13 is a timing chart for explaining the operation of the motion compensating unit 100, and FIG. 14 is a diagram conceptually illustrating a state of pixel data accompanying the operation of FIG. FIG. 15 is a timing chart for explaining the operation of the motion compensating unit 500, and FIG. 16 is a diagram conceptually illustrating a state of pixel data associated with the operation of FIG.

In FIG. 13 to FIG. 16, a symbol R indicates a reference data read operation for reading reference data, and a symbol W
Represents a write operation for writing pixel data, and the symbol D represents
This shows a read operation for reading display data. Each operation is performed in synchronization with the synchronization signal CLK. Also,
In FIGS. 14 and 16, for simplicity, description will be made focusing on the movement of a certain pixel.

Referring to FIGS. 13 and 14, motion compensation unit 1
00 repeats a reference data read period of two clocks, a write period of one clock, and a display period of one clock.
That is, one cycle is composed of four clocks. The left-eye block 20 extracts the pixel data L1 and the pixel data L2 by a reference data read operation of two clocks (CLK1, CLK2). The left-eye block 20 performs a motion compensation operation based on the extracted pixel data L1 and L2, and decodes the left-eye pixel data L4 (not shown).

The right-eye block 30 receives two clocks (CL
In the reference data read operation of (K1, CLK2), the pixel data L0 and the pixel data R1 are extracted. Thereby, the right-eye pixel data R3 (not shown) is decoded. Here, the pixel data L0 is the decoded left-eye pixel data stored one frame before.

At the third clock (CLK3), the left-eye pixel data L3 decoded using the reference data read several cycles ago is stored in the bank B0 # of the L memory 22.
L or B1 @ L and R are simultaneously stored in the same frame of the R memory 32 at relatively the same position. The left-eye pixel data stored in the R memory 32 is used as reference data in the next cycle. In the R memory 32, while one bank is performing a write operation, display data (decoded right-eye pixel data) is read from the other bank.
Is led.

At the fourth clock (CLK4), display data (decoded left-eye pixel data) to be displayed is read from the L memory 22. On the other hand, the right-eye pixel data R2 decoded using the reference data read several cycles before is stored in the bank B0 # R or B1 # R.

Referring to FIGS. 15 and 16, motion compensation unit 5
In 00, two (4 clocks) reference data read periods, one clock write periods, and one clock display periods are repeated. That is, one cycle is composed of six clocks.

The left-eye block 520 receives two clocks (C
LK1, CLK2), the pixel data L10 and the pixel data L11 are extracted by the reference data read operation. Based on the extracted pixel data L10 and L11, the left-eye pixel data L
14 (not shown) are decoded. Right eye block 53
0 takes out the right eye image data R10.

In the following two clocks (CLK3 and CLK4), the left-eye pixel data L13 in the left-eye block 520 is extracted and transferred to the right-eye block 530 based on a request for a reference data read operation from the right-eye block 530. . Note that the R memory 532 does not perform a read operation / write operation during this time. Right eye block 530
Performs a motion compensation operation based on the right-eye pixel data R10 and the transferred left-eye pixel data L13,
The right-eye pixel data R12 (not shown) is decoded.

At the fifth clock (CLK5), the left-eye pixel data L12 decoded by using the reference data read several cycles ago is stored in the bank B of the L memory 522.
It is stored in 2 @ L or B3 @ L. Further, the right-eye pixel data R11 decoded using the reference data read in advance a plurality of cycles ago is stored in the R memory 532 as B2♯R
Alternatively, it is stored in B3 @ R.

At the sixth clock (CLK6), display data (decoded left-eye pixel data) is read from the L memory 522.
Is read, and display data (decoded right-eye pixel data) is read from the R memory 532.

As described above, both the motion compensation unit 100 and the motion compensation unit 500 can decode the stereoscopic image defined in FIG. However, the motion compensation unit 100 that stores the decoded left-eye image data in the left-eye block and the right-eye block at the same time is different from the motion compensation unit 500 that requests the reference data read operation of the decoded left-eye image data. Thus, the reference data read period can be reduced. Therefore, according to decoder 1000 and motion compensator 100 in Embodiment 1 of the present invention,
The processing time in the motion compensation calculation processing is reduced. Further, a gate, an address line, and the like for requesting a reference data read operation to the left-eye block corresponding to the basic channel are not required.

[Second Embodiment] In a second embodiment of the present invention, an improved example of the decoder 1000 shown in FIG. 1 will be described. In the second embodiment, a decoder for a plurality of channels (three or more channels) will be described. FIG. 17 is a diagram for describing an image encoding state according to Embodiment 2 of the present invention. The image of the first channel (1ch: basic channel) includes an I picture I0, a P picture P0,
.. Are composed of B pictures B0, B1,. The images of the second to n-th channels are composed of P pictures and B pictures. For example, the second channel includes P picture Pro # 2, B picture Br1 # 2, Br2 # 2, B picture
, r3 # 2, Br4 # 2, Br5 # 2,..., and the n-th channel includes a P picture Pro @ n and a B picture B
r1♯n, Br2♯n, Br3♯n, Br4♯n, Br
5♯n,... The screens of the second to n-th channels are respectively decoded using a reference screen corresponding to each channel and a reference screen of the first channel which is a basic image.

By performing such encoding, it is possible to compress and transmit, for example, a video image of a scene taken from a plurality of angles.

On the other hand, on the decoder side, it is necessary to decode a plurality of channel images at high speed. FIG.
FIG. 8 is a diagram illustrating a configuration of a motion compensation unit 200 according to Embodiment 2 of the present invention. The motion compensation unit 200 is used instead of the motion compensation unit 100 shown in FIG.

The motion compensating section 200 includes blocks corresponding to each of a plurality of channels (generally referred to as channel corresponding blocks 210). In FIG. 18, the basic block 210 # corresponding to the basic channel (1ch)
Block 210 for 2ch corresponding to 1, 2nd channel
# 2, nch block 21 corresponding to the nth channel
0♯n is representatively described.

Each of the channel corresponding blocks 210 includes a frame memory, a memory control unit, and a motion compensation operation unit. Specifically, the basic block 210 # 1 is
A frame memory 212 # 1, a memory control unit 214 # 1,
A motion compensation operation unit 216 # 1 is included. 2ch block 2
10 # 2 includes a frame memory 212 # 2, a memory control unit 214 # 2, and a motion compensation calculation unit 216 # 2. nch
Block 210 # n includes a frame memory 212 # n,
A memory control unit 214 # n and a motion compensation calculation unit 216 # n are included.

Frame memories 212 # 1 to 212 # n
(Generally referred to as a frame memory 212) includes two banks B0 and B1. These bank configurations are the same as those described in the first embodiment.

Motion compensation operation units 216 # 1 to 216 # n
The motion compensation calculator 216 (generally referred to as a motion compensation calculator 216) has the same configuration as the motion compensation calculator 26 described above.

Memory control section 214 # 1 has the same configuration as memory control section 24 described above. Memory control unit 214♯
2-214 # n has the same configuration as the memory control unit 34 described above.

The image data decoded in basic block 210 # 1 is stored in frame memory 212 # 1, and transferred to other channel corresponding blocks 210 via data line DLINE3. Each channel corresponding block 210 stores the transferred data in the corresponding frame memory 212.

The motion compensation operation section 216 # 1 decodes the image data corresponding to the basic channel based on the decoded image data and the difference data stored in the frame memory 212 # 1. Motion compensation calculator 216 # 2-21
Each of 6♯n decodes the image data based on the decoded image data of the corresponding channel read from each frame memory 212, the decoded image data of the basic channel, and the difference data. In addition,
The channel corresponding blocks 210 # 2 to 210 # n store the decoded image data in the corresponding frame memory 212.
To be stored.

Here, in order to explain the effectiveness of the present invention,
Another example of the motion compensation unit will be described with reference to FIG. FIG. 19 is a diagram illustrating another example of the motion compensation unit that decodes an image of a plurality of channels based on a basic image of a basic channel. The motion compensating unit 300 illustrated in FIG. 19 includes blocks corresponding to each of a plurality of channels (collectively referred to as channel corresponding blocks 310). In FIG. 19, the basic channel (first channel: 1ch)
, A 2ch block 310 # 2 corresponding to the second channel, and an nch block 310 # n corresponding to the nth channel.

Each of the channel corresponding blocks 310 includes a frame memory, a memory control unit, a gate, and a motion compensation operation unit. Specifically, the basic block 310 #
1 is a frame memory 312 # 1, a memory control unit 314
{1, motion compensation operation unit 316 # 1 and gate 318}
Including 1. The 2ch block 210 # 2 includes a frame memory 312 # 2, a memory control unit 314 # 2, a motion compensation operation unit 216 # 2, and a gate 318 # 2. nch
Block 310 # n includes a frame memory 312 # n,
Memory control unit 314 # n, motion compensation operation unit 316 # n, and gate 318 # n are included.

Frame memories 312 # 1 to 312 # n
The frame memory (generally referred to as a frame memory 312) includes the two banks B0 and B1 described above.

Motion compensation operation units 316 # 1-316 # n
Of the motion compensation calculation units 316 # 1 (collectively referred to as a motion compensation calculation unit 316),
6 and the motion compensation operation units 316 # 2-31.
6♯n has the same configuration as the motion compensation calculation unit 536.

Memory control section 314 # 1 has the same configuration as memory control section 524 described above. Memory control unit 314
{2 to 314} n have the same configuration as the memory control unit 534 described above. Memory control unit 314 # 2-314 # n
Requests the basic block 310 # 1 to perform a reference data read operation in order to use the image data of the basic block as reference data. Memory control unit 314 # 2-314
The address output from each of $ n is input to corresponding gate 318 # 2-318 # n. Gate 318
Each of {2 to 318} n outputs the corresponding address to address line ALINE2.

The gate 318 # 1 is connected to the address line ALIN
In response to the address on E2, the frame memory 312 # 1
Output to The frame memory 312 # 1 reads the decoded image data based on the address. The read data is transferred to the motion compensation operation unit 316 of the channel corresponding block 310 that has issued the transfer request via the data line DLINE4. The request for the reference data read operation is sequentially performed for each channel corresponding block 310. The motion compensation calculation unit 316 performs a motion compensation calculation process using the transferred data, the decoded image data read from the corresponding frame memory 312, and the difference data. As a result, desired image data is decoded. Note that the decoded image data is stored in the corresponding frame memory 312.

Based on the above description, a comparison between the motion compensation unit 200 and the motion compensation unit 300 will be made with reference to FIGS. FIG. 20 is a timing chart for explaining the operation of the motion compensation unit 200, and FIG. 21 is a timing chart for explaining the operation of the motion compensation unit 300. 20 to 21, a symbol R indicates a reference data read operation for reading reference data, a symbol W indicates a write operation for writing pixel data, and a symbol D indicates a read operation for reading display data. . Each action is
This is performed in synchronization with the synchronization signal CLK.

Referring to FIG. 20, motion compensation section 200
The reference data read period of two clocks, the write period of one clock, and the display period of one clock are repeated. That is, one cycle is composed of four clocks.

Each channel corresponding block 210 stores image data to be referred to in a reference data read operation of two clocks (CLK1, CLK2) in an internal frame memory 212.
Lead from. Each channel corresponding block 210 includes:
A motion compensation operation is performed based on the read image data. Here, the channel corresponding block 210 # 2
.About.210 # n execute the motion compensation calculation process based on the reference data corresponding to the basic block and the reference data corresponding to each channel stored in advance.

At the third clock (CLK3), the image data decoded using the reference data read in advance in the basic block 210 # 1 a plurality of cycles earlier is stored in the basic block 210 # 1 and the other channel corresponding blocks. They are stored simultaneously in the same position in the same frame. The image data corresponding to the basic block stored in the channel corresponding blocks 210 # 2 to 210 # n is used as reference data in the next cycle. In each of the channel corresponding blocks 210 # 2 to 210 # n, while one bank is performing a write operation, decoded image data of a corresponding channel is read as display data from the other bank.

At the fourth clock (CLK4), the decoded image data as display data is transferred to the basic block 210.
# 1 is read from the frame memory 212 # 1. As for the display data, the data at the relatively same position in the same frame is read for all the channels.

On the other hand, the channel corresponding block 210 # 2
In each of .about.210 @ n, the image data decoded using the reference data read in advance several cycles before is stored in the bank B0 or B1.

The read timing of the display data differs between the basic block 210 # 1 and the block corresponding to the other channels. For example, the display timing is adjusted by arranging a flip-flop on the read path.

Referring to FIG. 21, motion compensating section 300 performs n (2 × n clock) reference data reading periods,
The write period of one clock and the display period of one clock are repeated. That is, one cycle is composed of (2n + 2) clocks.

Each channel corresponding block 310 extracts the reference data stored therein by the reference data read operation of two clocks (CLK1, CLK2). The basic block 310 # 1 performs a motion compensation calculation process based on the extracted image data and the difference data.

Between the following two clocks (CLK3, CLK4)
Then, based on the request for the reference data read operation from the 2ch block 310 # 2, the basic block 310 # 1
The reference data read operation is performed twice. The decoded image data of the basic block is a 2ch block 310 # 2
Is forwarded to The 2ch block 310 # 2 stores the image data (C) of the second channel stored in the block.
Using LK1 and CLK2) and the transferred image data (write with CLK3), a motion compensation calculation process is performed. As a result, an image corresponding to 2ch is decoded.

Thereafter, the reference data read operation is performed in accordance with the request for the reference data read operation for each channel corresponding block 310. As a result, each channel corresponding block 310 takes in the image data, and performs a motion compensation calculation process using the internal reference data and the transferred image data.

At the 2n + 1th clock (CLK2n + 1), in each channel corresponding block 310, the image data decoded using the reference data read in advance a plurality of cycles before is written to the corresponding frame memory. Then, the (2n + 2) th clock (CLK2 (n +
In 1)), display data (decoded image data) to be displayed is read from each channel corresponding block 310.

As described above, both the motion compensating unit 200 and the motion compensating unit 300 can decode an image of a plurality of channels specified in FIG. However, the motion compensation unit 200 that stores the decoded image data of the basic channel in the all-channel corresponding block 210 at the same time,
The reference data read period can be reduced as compared with the motion compensation unit 300 which requests the reference data read operation for the basic channel for each channel. Therefore,
According to the decoder and the motion compensation unit 200 according to Embodiment 2 of the present invention, the processing time in the motion compensation calculation processing is reduced. Further, since the data corresponding to the basic channel read by the reference data read operation is simultaneously stored in a predetermined position of the memory corresponding to all the channels, a gate for requesting the memory corresponding to the basic channel to read the reference data is provided. , Address lines and the like become unnecessary.

[Embodiment 3] Embodiment 3 of the present invention shows an improved example of the decoder 1000 shown in FIG. In the third embodiment, a decoder for decoding a stereo image using a multi-view profile will be described. FIG. 22 is a conceptual diagram illustrating the timing of the decoding process and the image display according to the third embodiment of the present invention. The symbol Li indicates a left-eye image corresponding to the first channel, and the symbol Ri indicates a right-eye image corresponding to the second channel (i = 1, 2, 3,...). Note that the left-eye image Li and the right-eye image Ri are images acquired at the same time.

As described above, the left-eye image is used as a basic image, and the decoded right-eye image and left-eye image are used as reference images for decoding the right-eye image. Further, for the left-eye image, dual prime prediction (Dual Prime) is performed with reference to pixel data at two different points one time earlier.

At time t0, the left-eye image L1 is decoded. At time t1, the left-eye image L2 is decoded using the restored left-eye image L1. Also, the right eye image R1
Is decoded using the restored left-eye image L1.

At time t2, the left-eye image L3 is decoded using the restored left-eye image L2. In addition, the right-eye image R2 is the restored left-eye image L2 and right-eye image R1.
Is decrypted using At this point, the decoded left-eye image L1 and right-eye image R1 are read from the frame memories (L memory and R memory) and displayed on the screen.

At time t3, the left-eye image L4 is restored using the restored left-eye image L3. Also, the right-eye image R3 is replaced with the restored left-eye image L3 and right-eye image R
2 is decoded. At this point, the decoded left-eye image L2 and right-eye image R2 are read from the frame memory and displayed on the screen.

FIG. 23A and FIG. 2 show an example of a frame memory for realizing the operation shown in FIG.
This will be described with reference to FIG. Referring to FIG.
The L memory has areas a1 to 3 for storing images for three frames.
a3 bank (L memory 80
2). With reference to FIG.
It is composed of a bank B4 @ R having areas b1 to b4 for storing images for frames (referred to as an R memory 803). Each of bank B4 # L and bank B4 # R can be accessed independently of each other.

Memory access to L memory 802 and R memory 803 will be described with reference to FIG. In FIG. 24, symbol R indicates a reference read operation for reading a reference image, symbol W indicates a write operation for storing a decoded image, and symbol D extracts a decoded image for image display. Each of them represents a reference read operation.

At time t0, the decoded left-eye image L1 is written to the area a1 of the bank B4 @ L and the area b1 of the bank B4 # R (one access per bank).

At time t1, the L memory 802 has the bank B4 @ L for decoding the left-eye image L2.
Perform a dual prime prediction read. Specifically, the area a1 of the bank B4 @ L is accessed four times,
Two different pixel data of the left eye image L1 are read. The decoded left-eye image L2 is written to the area a2 of the bank B4 @ L (one-time access).

Regarding the R memory 803, the right eye image R1
To read the left-eye image L1 from the area b1 of the bank B4 @ R (access twice). The decrypted right-eye image R1 is written to the area b3 of the bank B4 @ R (one-time access). The decoded left-eye image L2 is
Write to area b2 of bank B4 @ R (one-time access).

At time t2, with respect to the L memory 802, a dual prime prediction read is performed on the bank B4 # L for decoding the left-eye image L3. Specifically, the area a2 of the bank B4 # L is accessed four times, and two different pixel data of the left-eye image L2 are read. The decoded left-eye image L3 is written to the area a3 of the bank B4 @ L (one-time access). On the other hand, for image display, the left eye image L1 is displayed and read from the area a1 of the bank B4 @ L (one access).

As for the R memory 803, the right eye image R2
To read the left-eye image L2 from the region b2 of the bank B4 @ R and the right-eye image R1 from the region b3 (access twice each [total four times]). The decrypted right-eye image R2 is written to the area b4 of the bank B4 @ R (one-time access). The decoded left-eye image L3 is written to the area b1 of the bank B4 @ R (one-time access). On the other hand, for image display, the right-eye image R1 is displayed and read from the area b3 of the bank B4 @ R (one-time access).

At time t3, with respect to the L memory 802, a dual prime prediction read is performed on the bank B4 # L for decoding the left eye image L4. In particular,
The area a3 of the bank B4 # L is accessed four times to read out two different pixel data of the left eye image L3. The decoded left-eye image L4 is written to the area a1 of the bank B4 @ L (one-time access), and the left-eye image L2 is displayed and read from the area a2 of the bank B4 @ L for image display (one-time access).

As for the R memory 803, the right eye image R3
, The left-eye image L3 is read from the region b1 of the bank B4 @ R and the right-eye image R2 is read from the region b4 (each access is performed twice [a total of four times]). The decoded right-eye image R3 is written to the area b3 of the bank B4 @ R (one-time access). The decoded left-eye image L4 is written to the area b2 of the bank B4 @ R (one-time access).
For image display, the right eye image R2 is displayed and read from the area b4 of the bank B4 @ R (one-time access).

As described above, the L memory 802 is constituted by a bank having an area for storing images for three frames, and the R memory 803 is constituted by a bank having an area for storing images for four frames. The decoding and display processing of the image shown in FIG.

By the way, when such a configuration is used,
1 for each of the dual prime prediction read for the L memory and the reference read for restoration for the R memory
Four accesses per bank and two accesses per bank are required for writing the left-eye image / reading the right-eye image to the R memory.

An example of the configuration of a frame memory for realizing higher-speed processing will be described with reference to FIGS. 25A and 25B. Referring to FIG. 25A, an L memory is constituted by banks B5 # L1 and B5 # L2 each having areas a1 to a3 for storing images for three frames (referred to as L memory 602). FIG.
Referring to FIG. 5 (B), the R memory is divided into banks B5 # each having areas b1 to b4 for storing images for four frames.
R1 and bank B5 @ R2 (R memory 60
3). Bank B5♯L1, B5♯L2, B5♯R
Each of the banks B5 @ R2 can be accessed independently of each other.

Memory access to L memory 602 and R memory 603 will be described with reference to FIG. In FIG. 26, symbol R indicates a reference read operation for reading a reference image, symbol W indicates a write operation for storing a decoded image, and symbol D extracts a decoded image for image display. The display read operation is shown.

At time t0, as for L memory 602, area a1 of bank B5 # L1 and bank B5 # L
The decoded left-eye image L1 is written in the area a1 of No. 2 (accessed once per bank). As for the R memory 603, the decoded left-eye image L1 is written to the area b1 of the bank B5 @ R1 (accessed once).

At time t1, dual prime prediction reading is performed on the L memory 602 to decode the left eye image L2. In this case, the bank B5 @ L1 and the bank B5 @ L2 are accessed twice, respectively, and two different pixel data of the left-eye image L1 are read from each (access twice per bank). The decoded left-eye image L2 is transferred to the area a2 of the bank B5♯L1 and the bank B
Write to area a2 of 5♯L2 (access once per bank).

As for the R memory 603, the right eye image R1
Is read from the area b1 of the bank B5 @ R1 with reference to the left eye image L1 (accessed twice per bank). The decoded left-eye image L2 is stored in bank B5♯R2
In the area b2 (accessed once per bank). The decoded right-eye image R1 is stored in the bank B5♯R1
And the area b3 of the bank B5♯R2 (access once per bank).

At time t2, the L memory 602 performs dual prime prediction reading for decoding the left eye image L3. In this case, each of the banks B5 # L1 and B5 # L2 is accessed twice, and two different pixel data of the left-eye image L2 are read from each of the banks (access twice per bank). The decoded left-eye image L3 is written to the area a3 of the bank B5 @ L1 and the area a3 of the bank B5 @ L2 (1 per bank).
Times access). On the other hand, for image display, bank B4 @ L
The left eye image L1 is displayed and read from 1 (one access).

Regarding the R memory 603, the right eye image R2
To read the right-eye image R1 from the region b3 of the bank B5 @ R1 and the left-eye image L2 from the region b2 of the bank B5 @ R2 (access twice per bank). The decoded right-eye image R2 is stored in a bank B5♯R1.
Is written in the area b4 of the bank B5 and the area b4 of the bank B5 @ R2 (access once per bank). On the other hand, the decoded left-eye image L3 is written in the area b1 of the bank B5 @ R1, and the image of the bank B5 @ R2 is displayed for image display.
Display read of the right-eye image R1 from the area b3 (access once per bank).

At time t3, regarding the L memory 602, the banks B5♯L1, B2 for decoding the left-eye image L4
Perform a dual prime prediction read for 5 @ L2. Specifically, each area a3 of each of the banks B5 # L1 and B5 # L2 is accessed twice, and two different pixel data of the left-eye image L3 are read. The decoded left-eye image L4 is stored in the area a1 of the bank B5 @ L1 and the area a1 of the bank B5 # L2 (accessed once per bank). On the other hand, for image display, the left eye image L2 is read from the area a2 of the bank B4 @ L1 (one access).

With respect to the R memory 603, the right eye image R3
To read the left-eye image L3 from the region b1 in the bank B5 @ R1 and the right-eye image R2 from the region b4 in the bank B5 @ R2 (access twice per bank). The decoded right-eye image R3 is converted to a bank B5♯R1.
And the area b3 of the bank B5♯R2 (access once per bank). On the other hand, the decoded left-eye image L4 is written in the area b2 of the bank B5 @ R2, and the image of the bank B5 @ R1 is displayed for image display.
Display read of the right-eye image R2 from the area b4 (accessed once per bank).

Therefore, each of the dual prime prediction read for the L memory 602 and the reference read for the restoration for the R memory 603 is 2 per bank.
This is realized by one access per bank, including the left access to the R memory 603 and the right eye image display / read to the R memory 603. That is, by configuring each of the L memory 602 and the R memory 603 as a two-bank configuration, high-speed reproduction processing is realized.

The outline of the configuration of the motion compensator 600 including the L memory 602 and the R memory 603 will be described with reference to FIG. As shown in FIG. 27, the motion compensator 600
Includes a left-eye block 620 including an L memory 602 and a right-eye block 630 including an R memory 603. FIG.
Each of the memory control units 604 and 605 shown in FIG. 7 performs control for realizing the above-described memory access.

Next, another example of the configuration of the frame memory which realizes high-speed processing and has a small memory capacity is shown in FIG.
This will be described with reference to FIG. FIG.
Referring to (A), L memory is divided into banks B6 # L each having areas a1 to a3 for storing images for three frames.
1 and bank B6 # L2 (L memory 702
Described). Referring to FIG. 28B, the R memory is composed of banks B6 # R1 and B6 # R2 each having areas b1 to b3 for storing images for three frames (referred to as R memory 703). Bank B6 {L1, B6}
Each of L2, B6 @ R1 and B6 @ R2 can be accessed independently of each other.

Memory access to L memory 702 and R memory 703 will be described with reference to FIG. In FIG. 29, a symbol R indicates a reference read operation for reading a reference image, a symbol W indicates a write operation for storing a decoded image, and a symbol D extracts a decoded image for image display. The display read operation is shown.

At time t0, as for L memory 702, area a1 of bank B6 # L1 and bank B6 # L
The decoded left-eye image L1 is written in the area a1 of No. 2 (accessed once per bank). As for the R memory 703, the decoded left-eye image L1 is written to the area b1 of the bank B6♯R1 (one access).

At time t1, dual prime prediction reading is performed on the L memory 702 to decode the left eye image L2. Bank B6 @ L1 and Bank B6
$ Each of L2 is accessed twice. The decoded left-eye image L2 is written to the area a2 of the bank B6 # L1 and the area a2 of the bank B6 # L2 (one access per bank).

With respect to the R memory 703, the right eye image R1
Is read from the area b1 of the bank B6 @ R1 with reference to the left eye image L1 (accessed twice per bank). The decoded left-eye image L2 is stored in bank B6♯R2
Is written to the area b1 (accessed once per bank). The decoded right-eye image R1 is obtained by bank B6♯R1
And the area b2 of the bank B6 @ R2 is written (accessed once per bank).

At time t2, dual prime prediction reading is performed on L memory 702 to decode left eye image L3. Bank B6 @ L1 and Bank B6
$ L2 is accessed twice (accessed twice per bank). The decoded left-eye image L3 is divided into an area a3 of bank B6♯L1 and an area a3 of bank B6♯L2.
Write 3 (access once per bank). On the other hand, for image display, the left-eye image L from bank B6 @ L1 is displayed.
1 is displayed and read (accessed once).

As for the R memory 703, the right eye image R2
To read the right-eye image R1 from the region b2 of the bank B6 @ R1 and the left-eye image L2 from the region b1 of the bank B6 @ R2 (access twice per bank). The decoded right-eye image R2 is stored in a bank B6♯R1.
Is written to the area b3 of the area B3 and the area b3 of the bank B6♯R2 (accessed once per bank). On the other hand, the decoded left-eye image L3 is written in the area b1 of the bank B6 @ R1, and the image of the bank B6 @ R2 is displayed for image display.
Display read of the right-eye image R1 from the region b2 of (1) (access once per bank).

At time t 3, the L memory 702 has the bank B 6 ♯L 1, B 6 for decoding the left-eye image L 4.
6. Perform a dual prime prediction read on L2. Specifically, each area a3 of each of the banks B6 # L1 and B6 # L2 is accessed twice, and two different pixel data of the left-eye image L3 are read. The decoded left-eye image L4 is stored in the area a1 of the bank B6 # L1 and the area a1 of the bank B6 # L2 (accessed once per bank). On the other hand, for image display, the left eye image L2 is displayed and read from the area a2 of the bank B6 @ L1 (one access).

As for the R memory 703, the right eye image R3
To read the left-eye image L3 from the region b1 of the bank B6 @ R1 and the right-eye image R2 from the region b3 of the bank B6 @ R2 (access twice per bank). The decoded right-eye image R3 is stored in the bank B6♯R1.
And the area b2 of the bank B6 @ R2 is written (accessed once per bank). On the other hand, the decoded left-eye image L4 is written in the area b1 of the bank B6 @ R2, and the image of the bank B6 @ R1 is displayed for image display.
Display read of the right-eye image R2 from the area b3 (accessed once per bank).

Here, transition of memory access to L memory 702 will be described with reference to FIGS.
This will be described with reference to FIG. FIG. 30 and FIG.
In (C), symbols a1 to a3 represent banks B6♯L1
And an access area in the bank B6 # L2. The symbol "-" indicates a state where no memory access has been made. Note that FIG.
(C) shows the state transition of the memory access in the steady state.

With respect to bank B6 # L1, memory access is repeated in the order of area a1, area a2, and area a3 for reading the reference image (reference reading). Further, for storing (writing) the decoded image, the memory access is repeated in the order of the area a1, the area a2, and the area a3. Further, for reading the display image (display read), the memory access is repeated in the order of the area a1, the area a2, and the area a3. At each time, different areas are subject to reference read, write, and display read.

With respect to bank B6 # L2, memory access is repeated in the order of area a1, area a2, and area a3 for reading the reference image (reference reading). Further, for storing (writing) the decoded image, the memory access is repeated in the order of the area a1, the area a2, and the area a3. At each time, different areas are subject to reference read / write.

Next, transition of memory access to the R memory 703 will be described with reference to FIGS. 32, 33 (A) to (D), and FIGS. 34 (A) to (D). FIG.
In FIGS. 33 (A) to (D) and FIGS. 34 (A) to (D), symbols b1 to b3 indicate access areas in the banks B6 # R1 and B6 # R2. The symbol "-" indicates a state where no memory access has been made. 33 (A) to (D) show the state transition of memory access to bank B6 # R1 in the steady state, and FIGS. 34 (A) to (D) show the state transition of memory access to bank B6 # R2 in the steady state. Each state transition is shown.

For bank B6 # R1, areas b1 and b2 are alternately accessed to read out a reference image (reference read). Further, the area b2 and the area b3 are alternately accessed for storing (writing) the decoded right-eye image. In addition, the area b3 is accessed at a predetermined interval to read an image for display (display read).
Further, storage of the decoded left-eye image (L image light)
Therefore, the area b1 is accessed at a predetermined interval. At each time, different areas are referred to as read / write /
It is the target of the display lead.

For bank B6 # R2, areas b1 and b3 are alternately accessed for reading out a reference image (reference reading). Further, the area b2 and the area b3 are alternately accessed for storing (writing) the decoded right-eye image. Further, the area b2 is accessed at a predetermined interval for reading out a display image (display read). Further, the area b1 is accessed at predetermined intervals to store the decoded left-eye image (L image write). At each time, different areas are subject to reference read, write, and display read.

Therefore, for each of the dual prime prediction read for the L memory 702 and the reference read for restoration for the R memory 603, 2 per bank is used.
This is achieved by one access per bank, including the left access to the R memory 703 and the right eye image display / read to the R memory 703. That is, an L memory 702 including two banks each having an area for storing an image of three frames,
By using the R memory 703 including two banks each having an area for storing a frame image, high-speed reproduction processing is realized. In addition, compared to the L memory 602 and the R memory 603, the memory capacity can be reduced, the layout area can be reduced, and the memory configuration can be the same between the L memory 602 and the R memory 603.

Here, the L memory 702 and the R memory 7
The configuration of the motion compensating unit 700 including No. 03 will be described with reference to FIG. As shown in FIG. 35, the motion compensation unit 700
Includes a left-eye block 720 including an L memory 702 and a right-eye block 730 including an R memory 703. FIG.
Each of the memory control units 704 and 705 shown in FIG. 5 performs control for realizing the above-described memory access.

As described above, high-speed reproduction processing is realized by configuring each of the L memory and the R memory with two banks. Further, by using the L memory 702 and the R memory 703, the memory capacity can be reduced,
The layout area can be reduced. Furthermore, by using the L memory 702 and the R memory 703, the right-eye block and the left-eye block can be designed with the same memory configuration.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0181]

As described above, according to the decoder of the present invention, a basic channel to be referred to for a coded stereo image of a plurality of channels (more specifically, based on the MVP method of MPEG2). Are simultaneously stored in the memories of all the channels that refer to the image of the image. Therefore, at the time of decryption,
Blocks corresponding to channels other than the basic channel need not separately request a reference data read operation from the memory corresponding to the basic channel, and the processing time in the motion compensation calculation processing is reduced. Therefore, high-speed operation is possible as the whole system. So, for example,
It is also possible to use a low-speed memory, in which case the cost can be reduced.

Further, since the data to be referred to is stored at a predetermined position in the memories of all the necessary channels, gates and address lines are not required. For this reason, the circuit scale is reduced, and downsizing is realized.

Further, by configuring each of the L memory and the R memory in a two-bank configuration, it is possible to realize a high-speed stereo image reproduction process using a multi-view profile. In particular, each of the L memory and the R memory is capable of storing an image of three frames.
By using a bank and performing address control, a high-speed reproduction process can be performed, and the hardware configuration can be easily designed.

[Brief description of the drawings]

FIG. 1 shows a decoder 10 according to a first embodiment of the present invention.
FIG. 1 is a schematic block diagram showing the overall configuration of a 00.

FIG. 2 is a block diagram showing a specific configuration of a motion compensation unit 100 shown in FIG.

FIG. 3 is a conceptual diagram for describing a macroblock MB.

FIG. 4 is a diagram showing a specific configuration of a memory control unit 24 according to the first embodiment of the present invention.

FIG. 5 shows an L memory 2 based on control of a memory control unit 24.
6 is a flowchart for explaining the operation of FIG.

FIG. 6 is a diagram illustrating a specific configuration of a memory control unit according to the first embodiment of the present invention.

7 is an R memory 3 based on the control of a memory control unit 34. FIG.
6 is a flowchart for explaining the operation of FIG.

FIG. 8 is a diagram illustrating another example of the motion compensation unit that decodes a right-eye image using a left-eye image.

FIG. 9 is a diagram showing a specific configuration of a memory control unit 524.

FIG. 10 is a diagram showing a specific configuration of a memory control unit 534.

FIG. 11 is a flowchart for explaining the operation of the L memory 522 based on the control of the memory control unit 524.

FIG. 12 is a flowchart illustrating an operation of an R memory 532 based on control of a memory control unit 534.

FIG. 13 is a timing chart for explaining the operation of the motion compensation unit 100.

14 is a diagram conceptually illustrating a state of pixel data according to the operation of FIG.

FIG. 15 is a timing chart for explaining the operation of the motion compensation unit 500.

16 is a diagram conceptually illustrating a state of pixel data according to the operation of FIG.

FIG. 17 is a diagram for explaining an image encoding state according to Embodiment 2 of the present invention.

FIG. 18 is a diagram illustrating a configuration of a motion compensation unit 200 according to Embodiment 2 of the present invention.

FIG. 19 is a diagram illustrating another example of the motion compensation unit that decodes an image of a plurality of channels based on a basic image of a basic channel.

FIG. 20 is a timing chart for explaining the operation of the motion compensation unit 200.

FIG. 21 is a timing chart for explaining the operation of the motion compensation unit 300.

FIG. 22 is a conceptual diagram for describing the timing of decoding processing and image display according to Embodiment 3 of the present invention.

FIGS. 23A and 23B are an L memory 802 and an R memory 803 for realizing the operation shown in FIG.
It is a figure which shows each structure of.

FIG. 24 is a diagram for describing memory access to an L memory 802 and an R memory 803.

FIGS. 25A and 25B show Embodiment 3 of the present invention.
FIG. 3 is a diagram showing a configuration of each of an L memory 602 and an R memory 603 according to the first embodiment.

FIG. 26 is a diagram for describing memory access to an L memory 602 and an R memory 603.

FIG. 27 is a block diagram illustrating a configuration of a motion compensation unit 600 including an L memory 602 and an R memory 603.

FIGS. 28A and 28B show Embodiment 3 of the present invention.
FIG. 3 is a diagram showing a configuration of each of an L memory 702 and an R memory 703 according to the first embodiment.

FIG. 29 is a diagram for describing memory access to an L memory 702 and an R memory 703.

FIG. 30 is a diagram showing a state of memory access in the L memory 702.

FIGS. 31A to 31C are conceptual diagrams showing transition of an access state of the L memory 702 in a steady state.

FIG. 32 is a diagram showing a state of memory access in the R memory 703.

FIGS. 33A to 33D are conceptual diagrams showing transition of the access state in the bank B6 # R1 of the R memory 703 in the steady state.

FIGS. 34A to 34D are conceptual diagrams showing transition of the access state in the bank B6 # R2 of the R memory 703 in the steady state.

FIG. 35 is a block diagram showing a configuration of a motion compensation unit 700 including an L memory 702 and an R memory 703.

FIG. 36 is a diagram illustrating a process of encoding (decoding) a stereoscopic image conforming to MPEG2.

FIG. 37 is a diagram illustrating a configuration of a conventional motion compensation unit 900 that decodes the encoded screen illustrated in FIG. 36.

[Explanation of symbols]

2 buffers, 4 variable length decoders, 6 inverse quantizers,
8 inverse DCT unit, 12 format converter, 14 D /
A converter, B0♯L, B1♯L, B0♯R, B1♯R,
B4♯L, B4♯L, B5♯L1, B5♯L2, B5♯
R1, B5♯R2, B6♯L1, B6♯L2, B6♯R
1, B6 @ R2 bank, 22,32,212 @ 1-2
12♯n frame memory, 24, 34, 214♯1
214 @ n, 604, 605, 704, 705 Memory control unit, 26, 36, 216 @ 1-216 @ n Motion compensation operation unit, 40, 42 16 pixel extraction unit, 41, 43 addition unit, 28, 38 Data output Part, 20, 620, 72
0 Block for left eye, 30, 630, 730 Block for right eye, 50, 55, 70, 71, 80, 81 Reference address generation circuit, 52, 57, 75, 76, 85, 86
Write address generation circuit, 53, 58, 74, 84 Display address generation circuit, 54, 59, 78, 77 # 1-7
7♯ selector, 100, 200, 600, 700 motion compensator, 210♯1♯210♯n channel corresponding block, 1000 decoder.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Ryuji Kaneda 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. F-term (reference) 5C059 KK11 KK15 KK19 MA00 MA23 ME01 NN01 NN11 PP04 PP13 SS00 UA05 UA38 5C061 AA29 AB11 AB12 AB24

Claims (7)

[Claims] 1. A decoder that reproduces a stereoscopic image by decoding encoded image data of a first channel and a second channel, respectively, wherein a first image corresponding to the first channel is reproduced. A first reference data read from the first memory and a first reference data;
A first arithmetic circuit that decodes the image data of the first channel by performing a motion compensation arithmetic process based on the difference data of A first control for storing the decoded first channel image data as the first reference data from the first memory in accordance with a first motion vector, storing the decoded image data in the first memory in the first memory; A circuit; a second memory corresponding to the second channel; second reference data read from the second memory;
A second arithmetic circuit that decodes the image data of the second channel by performing a motion compensation arithmetic process based on the differential data of the second arithmetic circuit; and decoded image data output by the first arithmetic circuit. The decoded image data output from the second arithmetic circuit is stored in the second memory, and the decoded first channel as the second reference data is stored in accordance with a second motion vector. And a second control circuit for reading the decoded image data of the second channel from the second memory. 2. The decoder according to claim 1, wherein the first channel corresponds to a left-eye image, and the second channel corresponds to a right-eye image. 3. The first memory and the second memory each store a plurality of frames of image data, and wherein the first control circuit and the second control circuit 2. The decoder according to claim 1, wherein image data of one channel is stored in the first memory and the second memory at relatively the same position within the same frame. 3. 4. The first memory includes a first bank and a second bank that can be accessed independently of each other, and the second memory has a first bank that can be accessed independently of each other. Decoder according to claim 1 or 2, comprising a third bank and a fourth bank. 5. The first bank, the second bank,
The decoder according to claim 4, wherein each of the third bank and the fourth bank has an area for storing image data for three frames. 6. A decoder for reproducing a stereoscopic image by respectively decoding encoded image data of a basic channel and encoded image data of a plurality of channels, the decoder corresponding to the basic channel. A first motion compensation processing circuit; and a plurality of second motion compensation processing circuits provided corresponding to each of the plurality of channels, wherein the first motion compensation processing circuit stores image data. 1 memory; first reference data read from the first memory;
A first arithmetic circuit that decodes the image data of the basic channel by performing a motion compensation arithmetic process based on the differential data of the first channel and the decoded image data output by the first arithmetic circuit. And a first control circuit for reading out from the first memory the decoded image data of the basic channel, which is the first reference data, according to a first motion vector. A second memory for storing image data, a second reference data read from the second memory, and a second memory.
A second arithmetic circuit that decodes the image data of the corresponding channel by performing a motion compensation arithmetic process based on the differential data of the second arithmetic circuit; and the decoded image data output by the first arithmetic circuit and the second arithmetic circuit. 2 is stored in the second memory, and in accordance with a second motion vector, the decoded image data of the basic channel, which is the second reference data, is stored in the second memory. A second control circuit for reading the decoded image data of the corresponding channel from the second memory. 7. Each of the first memory and the second memory stores image data of a plurality of frames, and the first control circuit and the second control circuit store the decoded basic data. 7. The decoder according to claim 6, wherein image data of a channel is stored at a relatively same position in the same frame in the first memory and the second memory.