JP2000351242A - Image forming device - Google Patents

Abstract

(57) Abstract: A circuit scale of an image processing circuit that performs image processing including neighborhood processing in an image processing unit provided in an image forming apparatus is reduced. SOLUTION: Image data input for each pixel line is divided by a line / tile converter 500 into image data of a rectangular pixel range, and image processing including neighborhood processing is performed on the divided image data. To the image processing circuit 420
The image data that has been subjected to the image processing in (1) to (N) is converted into image data for each pixel line by the tile / line conversion unit 600, and an image is formed by the image output unit 800.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus for forming an image from image data, and more particularly, to an image forming apparatus for forming an image from image data input line by line.

[0002]

2. Description of the Related Art An image forming apparatus which forms an image from image data, and displays or records the image is used. In many cases, image data is input to such an image forming apparatus on a line-by-line basis. According to the present inventor, it has been considered that the image forming apparatus performs image processing in accordance with the input data of the image forming apparatus or the specification of the image forming apparatus itself. Further, as such image processing, image processing including neighborhood processing for obtaining a value of an output pixel using information of neighboring pixels is under study.

Referring to FIG. 8, an image forming apparatus having a conventional image processing unit for performing image processing including neighborhood processing on image data input in units of lines will be described.

The image processing unit 30 has N stages of image processing circuits 32 (1) to 32 (N). Each stage of the image processing circuit 32 includes a line buffer memory and a calculation unit (not shown). The image processing unit 30
In, image processing including neighborhood processing is performed on the image data. Examples of the neighborhood processing include character enhancement processing, moiré removal processing, and sharpness enhancement processing. As a process other than the proximity process, for example, a color conversion process is performed.

[0005] On the other hand, in the neighborhood processing, the arithmetic unit outputs data using pixels in the vicinity of the output pixel in addition to the pixel at the position corresponding to the output pixel (hereinafter, these are referred to as neighbor pixels). An operation for obtaining data at the pixel is performed.

For this reason, the line buffer memory provided in the image processing circuit 32 of each stage performing the neighborhood processing has a configuration capable of storing a plurality of lines of image data in line units.

[0007] The image processing section 30 outputs the data of the processed image to the image forming section 40 line by line to form an image.

[0008]

However, the number of pixels required to store data in the line buffer memory is increased by increasing the number of pixels in one line and expanding the range of neighboring pixels in each neighborhood process. It increases according to.

For example, when performing neighborhood processing using neighboring K × K pixels, information on pixels for at least the (K−1) line is required. Therefore, the line buffer memory is required to have a storage capacity corresponding to the number of pixels of (K-1) [line] × [pixel / line].

For example, if the size of the formed image is A3 size, the formed width of the image is about 13 inches. Therefore, in the case of an image forming apparatus having a resolution of 300 dpi, the number of pixels required to perform neighborhood processing on 5 × 5 neighboring pixels is approximately 300 [pixels / inch] × 13 [inch] × (5-1) ) [Line] = 15,600 [pixels].

Further, when performing the neighborhood processing in a plurality of stages, it is required to store the image data of the above-mentioned number of pixels in the line buffer memories of the respective image processing circuits 32 which perform the neighborhood processing. Therefore, the required number of pixels increases in proportion to the number of stages for performing the neighborhood processing.

Further, in the case of an image forming apparatus in which the number of gradation colors in input image data is 8 bits for each of RGB (red, green, blue), 24-bit image data is required for each pixel. For this reason, the storage capacity required for each line buffer memory is 15,600 [pixels] × 24 [bit / pixel] = 377,40 from the number of pixels described above.
It becomes 0 [bit].

[0013] Further, increasing the image forming size,
In addition, the required buffer memory increases in proportion to the increase in the resolution. For example, if the resolution is 300d
In order to increase the resolution from pi to 600 dpi, the storage capacity required for the line buffer memory is further doubled.

On the other hand, in order to speed up image processing, it is required that each image processing circuit 32 access all image data in neighboring pixels in parallel from the corresponding line buffer memory. For this reason, it is required that each image processing circuit also ensure a large data transfer bus width. For example, if the image processing circuit performs a neighborhood process on 5 × 5 pixels in the neighborhood, 25 (= 5)
X5) A bus width that can transfer image data corresponding to a pixel at one time is required.

As described above, when an image forming apparatus having a conventional image processing section is configured, a line buffer memory for a plurality of lines is required for each stage of image processing, so that a plurality of stages of image processing are performed. In this case, the storage capacity required for the line buffer memory increases in proportion to the number of stages.

Further, a large bus width is required for data transfer in the image processing circuit.

[0017] These requirements cause a problem that the circuit scale of the image processing circuit is enlarged. this is,
For example, it is difficult to integrate the image processing circuit into one chip, which leads to strict restrictions on system design.

Further, the above-mentioned problems are required to improve the performance of the image forming apparatus, for example, to increase the size of the formed image, to increase the resolution, to increase the number of gradations, and to increase the number of stages of the neighborhood processing. It is expected that this will become more noticeable as a result.

Therefore, there is a problem that the cost is increased and the whole apparatus is increased in size when mounted on the image forming apparatus.

An object of the present invention is to provide an image forming apparatus in which the circuit scale of an image processing unit is reduced.

[0021]

According to a first aspect of the present invention, there is provided an image forming apparatus for receiving image data on a line-by-line basis to form an image. A first storage unit for storing image data for a predetermined number of pixel lines, an input unit for writing image data to the first storage unit, and a first storage unit. In each of the above pixel lines, a readout unit for reading out image data of a partial section having a predetermined number of pixels H, and an image processing unit for performing image processing on the readout image data And an image forming means for receiving the image data subjected to the image processing and forming an image.

According to this aspect, it is possible to obtain an image forming apparatus including image processing means for taking in a part of the image data of the pixel line and performing image processing.

In the above aspect, the image processing means includes:
One or more image processing circuits for performing neighborhood processing are provided, each of the image processing circuits is provided with a line buffer for storing the image data read by the reading means, and the i-th image processing circuit is provided with a neighborhood Ki. When performing neighborhood processing using × Ki pixels, the line buffer of the i-th image processing circuit has at least a storage capacity capable of storing image data of {H × (Ki−1)} pixels. Alternatively, the line buffer of the i-th image processing circuit is divided into (Ki-1) pieces, and each of the divided line buffers stores image data of H pixels. It may have a possible storage capacity.

Thus, the image processing circuit does not need to include a line buffer for all images, and the capacity of the line buffer can be reduced.

Further, in the above aspect, a second storage means for storing image data for a predetermined number of pixel lines, and a data arrangement in which the partial section is continuous along the pixel line. Writing means for writing the image data subjected to the image processing to the second storage means, wherein the image forming means comprises:
An image may be formed for each pixel line.

Thus, by providing the second storage means for storing the image data subjected to the image processing, the image data can be reconfigured into the pixel lines.

In order to achieve the above object, the second aspect of the present invention
According to the aspect, there is provided an image forming apparatus for receiving image data on a line basis and forming an image, having a plurality of storage areas for storing image data of pixels, and an address of each storage area being: First storage means for storing image data of one pixel line in the storage area which is managed by a two-dimensional array consisting of rows and columns and to which addresses of the same row are allocated; Means for reading out the image data stored in the storage means by dividing the image data into a plurality of times for every m rows and n columns; and for reading the image data for each m rows and n columns read by the read means. Image processing means for performing processing, and image forming means for receiving the image data subjected to the image processing and forming an image.

According to the above aspect, there is provided an image forming apparatus having an image processing apparatus capable of dividing line-shaped pixel data into a rectangular shape having m rows and n columns and performing image processing in units of m rows and n columns. Obtainable.

In the above aspect, when reading out the image data in each of the m rows and n columns, the reading means reads the m rows and n columns.
The image data of the pixel stored at the peripheral address of the address of the storage area where the image data of the column is added is read out, and the image processing means uses the added and read out image data. Alternatively, pixel processing including neighborhood processing may be performed to generate image data of m rows and n columns.

Thus, even when the entire image is divided into m rows and n columns and subjected to image processing, the data added to the m rows and n columns of image data and read out are used to obtain the entire image. It is possible to obtain the same result as when processing is performed on the same.

Further, in the above aspect, the image processing means performs the neighborhood processing in N times, and in the i-th neighborhood processing, when the pixel data of the pixel in the Ki row and the Ki column is used, the additional processing is performed. The width of the read image data is
at least

(Equation 2) It may be the number of pixels.

Further, in the above aspect, a second storage means for storing image data for a predetermined number of pixel lines, and storing the image data subjected to the image processing in m rows and n columns A writing unit for writing the data into the second storage unit in a data arrangement corresponding to the pixel arrangement in which the pixel ranges are arranged may be further provided.

Further, the second storage means has two storage areas capable of storing image data for the pixels having the predetermined number of lines, and stores one of the two storage areas. The configuration may be such that writing of data to the area and reading of data from the other storage area are performed independently.

Thus, the image data of the pixel lines read out in a divided manner can be reconstructed, and the input / output to / from the second storage area can be performed in parallel.

According to a third aspect of the present invention, there is provided an image forming apparatus for receiving an image data on a line-by-line basis to form an image, comprising an image of two or more predetermined pixel columns. A first storage unit for storing data, and image data of a plurality of pixel columns stored in the first storage unit, each of data of a predetermined number of pixels from a start point of each column. Reading means for reading the plurality of pixel columns, image processing means for performing image processing for each image data read by the reading means, and receiving the image data subjected to the image processing to form an image. And an image forming unit for performing the operation.

[0036]

Embodiments of the present invention will be described below with reference to the drawings.

First, an image forming apparatus according to a first embodiment of the present invention will be described with reference to FIG.

In FIG. 1, an image forming apparatus 800 includes an image processing unit 400 for performing image processing on input image data, and an image forming unit 804 for forming an image from the processed image data. And is configured.

The image processing unit 400 is a line / tile converter for dividing a predetermined number of lines of line images into a plurality of rectangular image data (hereinafter, referred to as tile images). 500 and an N-stage image processing circuit 42 for performing image processing on each of the divided tile images
0 (1) to (N) and tiles for converting the tiled image subjected to the image processing into a row of linear images.
A line conversion unit 600 is provided. Note that the tiled image is obtained by dividing the line-shaped image into a plurality of rectangular images as described above, that is, an image composed of pixel groups arranged in m rows and n columns in real space. Means

Some of the image processing circuits 420 are circuits for performing image processing using an image in the vicinity of the pixel to be processed. Image processing is performed on the pixels in the K columns.

The image forming section 804 is for forming an image from image data. Image forming apparatus 804
Can be roughly classified into those for hard copy and those for soft copy depending on the form of the image to be formed.

The hard copy image forming apparatus is for recording a formed image in a storable form.
For example, hard copies include films, photographs, printed matter, and the like. Examples of the hard copy image forming apparatus include a printer, a photo output device, and an imagesetter. More specifically, examples of the printer include a line printer, a serial printer, and a page printer.

The image forming apparatus for soft copy is for visualizing the formed image with a short time delay. As an image forming apparatus for soft copy, typically, a display device (Visual Display Unit: VD
U). Examples of the display device include a CRT, a liquid crystal display, a plasma display, and the like.

The image forming apparatus 804 receives image data on a line-by-line basis from the image processing unit 400 and forms an image.

When the image forming apparatus 804 takes the form of a printer, the data in units of lines may be printed out and printed serially, or a plurality of lines may be connected and printed as a page. When page printing is performed, image data may be received in units of a row of line-shaped images in which the tile-shaped images are arranged. As a result, the efficiency of data transfer for configuring one page of data can be improved.

When printing can be performed not only for an entire page but also for a plurality of lines, image data is received in units of a line-shaped image column of the corresponding number of lines, thereby enabling data transfer. It is needless to say that the efficiency can be improved. In this case, it is possible to omit the tile / line conversion unit 600,
It can be configured as shown in FIG.

Next, the line / tile converter 500 and the tile / line converter 600 will be described with reference to FIG. Since the line / tile converter 500 and the tile / line converter 600 have a configuration and a function that are paired with each other, first, the line / tile converter 5
00, and then the tile / line conversion unit 60
0 will be described focusing on differences from the line / tile converter 500.

In FIG. 3, a line / tile converter 50
0 includes a buffer memory 510, a start address designating unit 520, and an address generating circuit 550.

The buffer memory 510 stores image data for one line of pixels for a plurality of lines. For example, the buffer memory 510 can be configured using a line buffer memory corresponding to the number of lines to be stored. .
In this case, the address of the storage area for storing the image data of each pixel included in the buffer memory 510 may be managed as a two-dimensional array having rows and columns.

The start address designating section 520 and the address generating circuit 550 are provided in the buffer memory 510.
In order to read out the image data for a plurality of lines stored in the form of a tile in a tile shape.

The start address instructing section 520 is for instructing a start address (start point) of a range from which image data is to be read, and the address generating circuit 550 determines a vertical size and a vertical size from the instructed start address. This is for reading out image data of pixels whose horizontal size belongs to a predetermined range.

The address generating circuit 550 includes a horizontal start address register 5 for storing the horizontal start address specified by the start address specifying unit 520.
52, a horizontal address counter 554 for incrementing the horizontal address, a horizontal size register 556 storing the horizontal size of a predetermined read range, and a horizontal address register 556 for counting the horizontal address incremented by the horizontal address counter. Horizontal size counter 558
A vertical start address register 562 for storing the vertical start address designated by the start address designating section 520, a vertical address counter 564 for incrementing the vertical address, and a vertical size of a predetermined read range. Stored vertical size register 5
66, and a vertical size counter 568 for counting the vertical address incremented by the vertical address counter 564.

In the address generation circuit 550, the address is incremented in the horizontal direction (the direction along the line) from the start address designated by the start address designating section 520. Then, when the horizontal address is incremented by the horizontal size counter 558 to the size stored in the horizontal size register 556, the horizontal address in the horizontal address counter 554 is reset to the horizontal start address, while the vertical address in the vertical address counter 564 is reset. Is incremented with respect to the vertical start address. That is, in the direction in which the lines are arranged (vertical direction), the address is changed for reading,
Further, the horizontal address at that time is reset to the horizontal start address. As a result, it is possible to read image data relating to the pixels of the next line. By repeating this operation, the horizontal size stored in the horizontal size register 556 and the vertical size register 56
6, the pixels belonging to the vertical size range can be read by raster scanning. And
When the vertical address reaches the address stored in the vertical size register 566, the vertical address is reset by the vertical size counter 568, and the end signal is sent to the start address instructing section 520 as an end signal. Can be

The start address designating section 520 receives this end and designates a starting point of a tile-shaped pixel range to be read next. By sequentially changing the starting point so as to be divided into tiles, tiled divided readout of image data is realized.

At this time, the horizontal size (1) stored in the horizontal size register 556 and the vertical size (1) stored in the vertical size register 556 are respectively defined by a rectangular range written in the buffer memory 610. By making S larger than the horizontal size (2) and the vertical size (2), it is possible to read out image data related to pixels belonging to a range including the overlapping range. That is,
When the image data is read from the buffer memory 510, the data of the peripheral pixels of the image of the rectangular range S written to the buffer memory 610 are also read. The data to be added is also read when the adjacent rectangular range S is read. Therefore, the added pixel data is read from the buffer memory 510 twice or more. Thus, even if image processing including neighborhood processing is independently performed on each block of image data cut into tiles, consistency with processing using the entire image data can be maintained. That is, in the boundary processing between the images divided into tiles, it is possible to divide the image by overlapping a certain number of pixels, and to transfer the overlapped portion in addition to the rectangular area S. Therefore, it is possible to use the image data on the neighboring pixels in the processing of the peripheral pixels in the tiled image.

Here, the respective widths W in the vertical direction and the horizontal direction of the additional portion which is read out in an overlapping manner depend on the size of the filter used in each image processing circuit 420 which performs the neighborhood processing. That is, the i-th image processing circuit 4
20, if a filter of Ki × Ki size is used, the width W of the overlap portion cut out from the buffer memory 510 is:

(Equation 3) [Pixel]. In addition, as shown in FIG.
The rectangular area S is surrounded by a width of (W / 2).

For example, the rectangular range S to be written to the buffer memory 610 is 256 × 256 pixels, that is, both the vertical size (2) and the horizontal size (2) are 256 pixels, and the image processing circuit 420 that performs the neighborhood processing is Consider the case where there are three stages. The first stage of the image processing circuit 420 is 3 × 3,
Assuming that neighborhood processing is performed using a 5 × 5 filter in the second stage and a 7 × 7 filter in the third stage, the width W of the overlap portion is ｛(3-1) + (5-1) + (7-1)｝
= 12 pixels. As a result, the vertical size (1) and the horizontal size (1) of the tiled image read from the buffer memory 510 are each 256 + 12 = 268 pixels.

Here, the configuration of the buffer memory 510 will be described in detail with reference to FIGS. 9 and 10. FIG.
9 is a diagram for explaining an input / output unit of data to / from the buffer memory 510. FIG.

In the buffer memory 510, the horizontal size of the entire image read by the image input device 200, ie, 1
A ring buffer having a width equal to or greater than the data length of the pixel line is used. The buffer memory 510 stores the image input device 20
The linear image sent from 0 is written, and the tiled image obtained by dividing the line image is read. The writing of the line image and the reading of the tile image will be described. Here, a rectangular range S to be written to the buffer memory 610 is assumed to be V × H pixels.

First, the first buffer memory 510
In the writing process (input), a linear image having the number of lines corresponding to (V + W / 2) pixels is written. Second
After the writing process (input), a linear image having the number of lines of V pixels is written.

In a first read processing group (output) from the buffer memory 510, a line image having a line width of (V + W / 2) pixels written in the first write processing is divided into tile images. Read out. After the second read processing group (output), a linear image having a line width of V pixels written in the second write processing and a linear image written in the first write processing adjacent thereto (W /
2) A line-shaped image with a line width of pixels is divided into tile-shaped images and read. In addition, as for the most peripheral image of the entire image, data of (W / 2) pixels are extrapolated by an arbitrary method.

FIG. 10 is a timing chart of the input and output processing described above. When the linear image is written as input,..., The output process is started when the input is completed, and the output and the input are performed in parallel. Output and input are performed in parallel in the same manner. Therefore, the capacity of the buffer memory 510 is
If more than {(2 × V) + W} pixels, output and
Entering the following data will not be overwritten. That is, the buffer memory 510 needs to use a ring buffer having a width equal to or larger than the horizontal size of the entire image and having a length equal to or more than {(2 × V) + W} pixels. Note that the ring buffers used for the buffer memory 510 may be configured as one-dimensional buffers as long as they have the same storage capacity.

By transferring the image data in an overlapping manner (by adding the pixels in the overlapping range), the image data relating to the same pixel is repeatedly transferred. Therefore, the vertical size (2) of the rectangular area S (here, V)
Is not set so as to be sufficiently larger than the width W (= Σ (Ki−1)) of the overlapped portion, the efficiency of data transfer is reduced.

For example, the line number V of the output block size
But

(Equation 4) If it is about 10 times, the data transfer time of the line corresponding to the neighboring pixel range is about 10% of the whole. More preferably, the number of lines V of the output block size is

(Equation 5) If the buffer memory 510, which is about 20 times as large as the above, is used, the data transfer time of the line corresponding to the neighboring pixel range is about 5% of the whole, and can be effectively ignored.

If the total number of lines of the image is known, the number of lines in the line buffer memory is set to be sufficiently smaller than the total number of lines. As a result, the time required to start image processing from the first reception of image data can be made negligible with respect to the entire processing time. That is, the time from the start of reception of the image data to the time when the line buffer memory is filled (buffer fill) (the time during which the image processing result cannot be sent to the output device) is added to the copy of the original. It can be negligible compared to the total time required.

In order to obtain the total number of lines of the image,
For example, a detector for detecting the document size is provided, and the total number of lines can be obtained by multiplying the detected document size by the resolution in a direction orthogonal to the lines.

The image data taken in line units by the scanner is first stored in the line buffer 510 (see FIG. 3) in units of tens to hundreds of lines. For example,
Assuming that 256 lines are stored at one time, in the case of a color copy system having a document size of A3, a resolution of 300 dpi, and a 24-bit color, approximately 300 [pixels / inch] × 13 [inch] × 24 [bit / pixel]
A buffer memory of × 256 [lines] = 23,961,600 [bits] is required.

The image processing circuit 420 processes the received image data as if it were an image of 256 × 256 pixels, and sends the result to the next stage. In this case, the neighborhood 5 ×
For image processing of 5 pixels, only 256 [pixels] × 24 [bit / pixel] × (5-1) [line] =
Only a 24,576 [bit] line buffer memory is required.

Even if the number of stages of image processing increases, it is sufficient that each stage is provided with a buffer memory having the above-mentioned capacity, so that an increase in circuit scale can be suppressed.

Further, for example, even if the system has a resolution of 600 dpi, the line buffer 510 (see FIG. 3)
This can be dealt with only by adding a line buffer 610 (see FIG. 3) described later.

Through the processing in the image processing circuit 420 of a plurality of stages (N stages), the tiled image is transferred to the line buffer 61.
0 (see FIG. 3) and, when the line buffer 610 is filled, output to the printer in line units.

Next, the tile / line converter 600 will be described. The tile / line conversion unit 600 has substantially the same configuration as that of the line / tile conversion unit 500. The tile / line conversion unit 600 converts a tiled image including image data belonging to pixels in a rectangular range obtained by performing processing into a pixel line. A buffer memory 610 capable of arranging a number of pieces, a start address designating section 620 for writing a tiled image in the buffer memory, and an address generating circuit 650.

The operation of each section in start address designating section 620 and address generating circuit 650 is the same, except that the generated address is a write address in buffer memory 610 and stored in horizontal size register 566. Horizontal and vertical size registers 6
The difference is that the vertical size stored at 66 matches the size of the rectangular range.

The buffer memory 610 has a double buffer configuration including a first buffer and a second buffer. Each buffer has a line capable of storing image data in a predetermined number of pixels for each line. A buffer memory may be provided, or, similarly to the buffer memory 510, a ring buffer may be used.

Note that the tile / line conversion 600 is the same as that shown in FIG.
Can be realized with a simpler configuration.
In FIG. 4, the vertical size and the horizontal size are each 25.
Pixel data relating to pixels in a rectangular range of 6 pixels is 3
The case where two are arranged to form image data having a line size of 8192 pixels is illustrated.

In FIG. 4, 8192 pixels in each line and each pixel in image data of 256 lines can be designated by using 21-bit addresses A0 to A20. That is, the lower 13 bits (A [12: 0]) are associated with the horizontal address, the upper 8 bits (A [20:13]) are associated, and the lower 13 bits are included in one line (8192 pixels). It is possible to specify which address and which of the 256 lines is specified by the upper 8 bits.

In the addressing of the tiled image,
A [12: 8] using a 5-bit address, 32 bits in the horizontal direction
Specify which of the tiled images divided into pieces,
The vertical address in each image is A [15: 8] and the horizontal address is A
It is possible to specify by [7: 0].

Next, the duplication processing in data division will be described. A state in which image data for one page is divided into tile images including a rectangular area S and an overlapping area is illustrated. Here, even in the divided boundary B (joint), the image data of the boundary is read in an overlapping manner so as to enable the neighborhood processing. When dividing image data into tiles, it is necessary to overlap and divide certain pixels, and to repeatedly transfer overlapping portions. This is because the processing of the peripheral pixels of the tiled image also requires information on the neighboring pixels.

In the case of performing N stages of image processing, the number of pixels in the neighborhood processing performed in each stage may be different. Therefore, it can be generally expressed by using Ki × Ki pixels. Therefore, the number of overlapping pixels is, as already mentioned,

(Equation 6) [Pixel].

In the above description, the line buffer 51
This is why the number of lines to be stored in 0 is set to be sufficiently large with respect to the neighboring pixel size in image processing. That is, this is to prevent the transfer time of the pixel to be repeatedly transferred from being an overhead for the entire processing time.

The reason that the number of overlapping pixels is set to be sufficiently small with respect to the total number of lines of the image is that the processing time until the line buffers 510 and 610 are filled for the first time depends on the processing result on the output side. (E.g., an image forming apparatus), so that this time is negligible with respect to the entire processing time. However, this is not a problem in practice.

At first glance, line buffers 510 and 610
It seems that the circuit size is not reduced because of the large capacity of the line buffers 510 and 610.
Satisfies the requirement only by supporting sequential access, and its data bus width may be the same as the input image. For this reason, it is possible to use a memory that can obtain a large capacity at a low cost, such as a synchronous DRAM. Therefore, the circuit scale can be reduced as a whole.

Next, referring to FIG. 5, image processing circuit 42
0 will be described. Here, an image processing circuit that performs neighborhood processing of neighboring 5 × 5 pixels will be described. However, even when the size of the neighborhood pixel range is different, it is needless to say that the same concept can be used for designing.

The image processing circuit 420 includes a neighborhood area access section 430 for accessing a neighborhood pixel area in input data, a register 440 in which pixel data is arranged and stored in a matrix, and a characteristic of neighborhood processing. The configuration includes a kernel table 450 to be given, and an operation unit 460 for performing an operation for obtaining a value of an output pixel using neighboring pixels.

The neighborhood area access unit 430 includes one transfer line 432 and four line buffer memories 435.
It is configured to have (1) to (4). The size of each line buffer memory 435 is the horizontal size (1) of the tiled image read from the buffer memory 510, that is,
It is equal to the number of pixels for one line of the tiled image. Since the data of the tiled image is serially transferred via the transfer line 432, the data is two-dimensionally formed again using the line buffer memory 435 functioning as a FIFO memory.

Specifically, the transferred serial data is first stored in the line buffer memory 435 (1). Then, the transferred serial data pushes out the already stored data,
It is stored in the line buffer memory 435 (1).
The data pushed out from the line buffer memory (1) moves to the line buffer memories 435 (2), (3), and (4) in such a way as to be pushed out into data coming later. Finally, data for four lines of the tiled image are stored in the line buffer memories (1) to (4). Then, 25 pixels obtained by combining the first five pixels of each line buffer memory 435 and the data of the first five pixels of the fifth line transferred from the transfer line 432 are
Transfer to 5 × 5 register 440. Line buffer 43
5 (1) to (3) are stored in the line buffers 435 (2) to (4), and the pixel data transferred from the transfer line 432 is stored in the line buffer (1). .

5 × 5 register 44 receiving data transfer
0 stores image data arranged in a matrix. The operation unit 460 uses the image data of the pixels of each array element in the 5 × 5 register 440 and the data of the corresponding array element in the kernel table 450.
And the value of the output pixel is obtained. For example, in the case of a smoothing filter, the value of each kernel element is a non-negative value that is normalized so that the sum of the array elements is 1. Used.

Next, a processing procedure in the copy system will be described with reference to FIG.

First, in process 1, image data is taken in line by line. That is, in step S11, the image data of the line unit is received from the image input device. Then, in step S22, data is written to the line buffer 510 in the line / tile converter 500 in line units.

Next, in processing 2, image processing is performed on the tiled image. In the process 2, first, image data is read from the line buffer 510 in a tile shape (step S31). Then, N-stage image processing ｛S32
(1) to (N)} are sequentially applied. Next, the image data that has been subjected to the image processing is written in a tile shape into the line buffer 610 in the tile / line conversion unit.

Next, in process 3, the buffer memory 6
The ten banks are inverted (step S40).

Then, in process 4, the image data is output in line units. In the process 4, first, image data is read from the buffer memory 610 line by line (step S51). Next, image data is transmitted to the image forming apparatus in line units.

Next, a data flow in the processing according to the present embodiment will be described with reference to FIG.

First, image data 1001 in line units is input and stored in the buffer memory 510 of the line / tile converter 500. Buffer memory 510
Is a ring buffer, and at the same time, data already stored is divided into a pieces of tiles, and areas 1310 (1), 1310 (2), 1310 (3),
, 1310 (a) are sequentially read out.

As described above, since the input / output timing is controlled as shown in FIG. 10, the area already output is newly overwritten with data.

The read data is subjected to image processing for each tile. For example, the tiled image 1410 ⁰ (1) read from the area 1310 (1) is subjected to the first-stage image processing 1 and becomes the tiled image 1410 ¹ (1). The tiled image 1410 ^N (1) on which the image processing of the step has been performed is obtained.

The tiled image 1410 ⁰ (1) is stored in the buffer memory 61 of the tile / line converter 600.
Region 1510 (1) of first bank 1500 at 0
Is written to.

Similarly, the areas 1310 (2) to 1310 (a)
Are also subjected to N-stage image processing, and are respectively written in the areas 1510 (2) to 1510 (a) in the buffer 610.

On the other hand, when the first bank 1500 is buffer-filled, the bank is inverted (double buffer inversion), the first bank 1500 is used for reading data, and the second bank 1600 receives the data.

Then, the image data is output line by line from the buffer-filled first bank 1500.

In the image forming apparatus according to the present embodiment,
Since image processing is performed in a state of being divided into tiles, the circuit scale of the image processing circuit can be reduced. It has a configuration that converts a line image into a tiled image and converts a tiled image into a line image, but the memory provided for them is only required to support sequential access, and the data bus width is Since the image may be the same as that of the image, a memory such as a synchronous DRAM which can obtain a large capacity at a low cost can be used. Therefore, the circuit scale can be reduced as a whole.

Further, since the image processing circuit only needs to process a predetermined small tile image, the image processing circuit can easily cope with the enlargement of the formed image size and the improvement of the resolution in the image forming apparatus. It becomes possible.

Some image forming units have an image forming unit that can form an image on a plurality of lines in parallel. An example of such an image forming unit is an ink-jet printing unit. In this case, it is not necessary to convert the image-processed tile image into a line image. In such a case, as described with reference to FIG. 2, the image forming apparatus can be configured by omitting the tile / line conversion unit. According to this aspect, it is possible to provide an image forming apparatus having an image processing function with a simpler configuration.

[0104]

According to the present invention, when an image processing unit is mounted on an image forming apparatus, the size of an image to be held by an image processing circuit in the image processing unit can be reduced. Therefore, the storage capacity of the buffer memory of the image processing circuit can be reduced.

Further, it is possible to easily configure systems having different formed image sizes and resolutions.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image forming apparatus to which the present invention is applied.

FIG. 2 is a block diagram of another embodiment of the image forming apparatus to which the present invention is applied.

FIG. 3 is an explanatory diagram showing components of a line / tile conversion unit and a tile / line conversion unit to which the present invention is applied, and a block configuration of an address generation circuit.

FIG. 4 is an explanatory diagram showing another configuration of the tile / line conversion unit to which the present invention is applied.

FIG. 5 is a block diagram of an image processing circuit to which the present invention is applied.

FIG. 6 is a flowchart showing a processing procedure in an image forming unit to which the present invention is applied.

FIG. 7 is a data flow diagram showing a data flow in an image processing unit to which the present invention has been applied.

FIG. 8 is a block diagram of an image forming apparatus to which conventional image processing is applied.

FIG. 9 is a diagram illustrating a tile image read from a buffer memory 510 in the image forming apparatus to which the present invention is applied.

FIG. 10 is a diagram showing a timing chart of input and output of a buffer memory 510 in an image forming apparatus to which the present invention is applied.

[Explanation of symbols]

30 image processing unit 32 (1) to (N) image processing circuit 40 image forming unit 400 image processing unit 420 (1) to 420 (N) image processing circuit 430 ... neighboring area access unit 432 ... transfer Lines 435 (1) to (4) Line buffer memory 440 5 × 5 register 450 Kernel table 460 Arithmetic unit 500 Line-to-tile conversion unit 600 Tile-to-line conversion unit 520, 520 Start address instruction unit 550 , 650... Address generating circuit 552, 652... Horizontal start address register 554, 654... Horizontal address counter 556, 656... Horizontal size register 558, 658... Horizontal size counter 562, 662... Vertical start address register 564, 664. 566, 666 ... vertical size register 568, 68 ... vertical size counter 800,801,803 ... image forming apparatus 804, 805 ... image forming unit 1001 ... input pixel line 1002 ... output pixel line 1310 (1) ~ (a) ... pixel tile 1410 ... tiled image 1410 ⁱ ( i = 0, 1, 2,..., N) Cut-out tile-shaped image (subscript i indicates the number of steps subjected to image processing) 1510 (1) to (a): Tile-shaped image 1500: Pixel tile Buffer bank in which group is stored 1600... Buffer bank in which pixel line group is stored

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference)

Claims (10)

[Claims] 1. An image forming apparatus for receiving image data on a line-by-line basis to form an image, comprising: first storage means for storing image data for a predetermined number of pixel lines; Input means for writing image data to the first storage means; and a predetermined number of pixels in one or more pixel lines from the first storage means.
H, reading means for reading image data of a partial section, image processing means for performing image processing on the read image data, and receiving the image data on which the image processing has been performed. And an image forming means for forming an image. 2. The image forming apparatus according to claim 1, wherein said image processing means includes one or more image processing circuits for performing neighborhood processing, and each of said image processing circuits includes image data read by said reading means. When the i-th image processing circuit performs neighborhood processing using neighboring Ki × Ki pixels, the line buffer of the i-th image processing circuit has at least ΔH × (Ki-1)｝ An image forming apparatus having a storage capacity capable of storing pixel image data. 3. The image forming apparatus according to claim 2, wherein the line buffer of the i-th image processing circuit is divided into (Ki-1), and each of the divided line buffers is An image forming apparatus having a storage capacity capable of storing image data of H pixels. 4. An image forming apparatus according to claim 1, wherein said second storage means stores image data for a predetermined number of pixel lines; A writing unit for writing the image data on which the image processing has been performed in the second storage unit in a data arrangement in which the sections are continuous along the pixel line; and the image forming unit includes: An image forming apparatus for forming an image for each pixel line. 5. An image forming apparatus for receiving image data on a line-by-line basis to form an image, comprising a plurality of storage areas for storing image data of pixels, wherein an address of each storage area is a line address. First storage means for storing image data of one pixel line in the storage area which is managed by a two-dimensional array consisting of A reading unit that reads out the image data stored in the storage unit by dividing the image data into a plurality of times every m rows and n columns, and an image processing unit that reads out the image data in the m rows and n columns read by the reading unit. An image forming apparatus comprising: an image processing unit that performs image processing; and an image forming unit that receives the image data subjected to the image processing and forms an image. 6. The image forming apparatus according to claim 5, wherein said reading means reads said m rows and n columns of image data.
The image data of the pixel stored at the peripheral address of the address of the storage area in which the image data of the row n column is stored is read by adding the image data. An image forming apparatus that performs pixel processing including neighborhood processing to generate image data of m rows and n columns. 7. An image forming apparatus according to claim 6, wherein said image processing means performs said neighborhood processing in N times, and in i-th neighborhood processing, pixel data of a pixel in a Ki row and a Ki column is obtained. When used, the width of the image data that is additionally read is at least: An image forming apparatus comprising: pixels. 8. The image forming apparatus according to claim 4, wherein a second storage means for storing image data for a predetermined number of pixel lines, and wherein said image processing is performed. Writing means for writing the obtained image data in the second storage means in a data arrangement corresponding to a pixel arrangement in which the pixel range of m rows and n columns is arranged. And an image processing apparatus for forming an image for each pixel line. 9. The image forming apparatus according to claim 8, wherein said second storage means has two storage areas capable of storing image data for the pixels having the predetermined number of lines. An image forming apparatus having a configuration in which writing of data to one of two storage areas and reading of data from the other storage area are performed independently. 10. An image forming apparatus for receiving an image data on a line-by-line basis to form an image, comprising: first storage means for storing image data of two or more predetermined pixel columns; Reading means for dividing the image data of the plurality of pixel rows stored in the first storage means into data of a predetermined number of pixels from the starting point of each row and reading out the plurality of pixel rows; An image processing unit that performs image processing for each image data read by the reading unit; and an image forming unit that receives the image data subjected to the image processing and forms an image. Image processing apparatus.