JP2000340773A - Nonvolatile semiconductor memory storage and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify manufacturing process of a nonvolatile semiconductor device. SOLUTION: A floating gate 3 is formed on the polysilicon gate of a logic part, and a control gate 6 is composed of a diffusion layer formed on a silicon substrate 1 by implantion of ions. A prescribed section 3a of the floating gates 3 is provided in extended form in the prescribed width, the ions implanted on both sides in the width direction of the prescribed section 3a are diffused, they are coupled under the prescribed section 3a, and a tunnel region is formed. In such a structure, it is not necessary to form a polysilicon layer in two layers, because a control gate 6 is formed on the surface of a substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor device having an electrically rewritable nonvolatile memory and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a conventional nonvolatile memory, EEPR
The manufacturing process of the OM is shown in FIGS. 5 to 9 and a conventional method of manufacturing the EEPROM will be described with reference to these drawings. In addition,
A manufacturing process of a PchMOS transistor and an NchMOS transistor which are usually formed as a logic part together with the EEPROM is also shown.

[Step shown in FIG. 5 (a)] First, after an oxide film 52 is formed on a silicon substrate 51, a PchMOS transistor formation region of a MOS transistor region is covered with a mask 53, and p-type impurities are ionized. By implantation, a p-type well layer 54 is formed in a region where an Nch-type MOS transistor is to be formed in the EEPROM region and the MOS transistor region.

[Step shown in FIG. 5B] Next, the mask 5
After removing 3, the region where the p-type well layer 54 is formed is further covered with a mask 55, and an n-type impurity is ion-implanted to form an n-type well layer 56 in a region where a PchMOS transistor is to be formed. Then, the mask 55 is removed.

[Step shown in FIG. 5 (c)]
An n ⁺ -type diffusion layer 58 is formed by covering the silicon substrate 51 with a mask 57 having an opening at a predetermined position in the ROM region and ion-implanting n-type impurities.

[Step shown in FIG. 6A] After removing the mask 57, a so-called LOCOS step is performed.
The LOCOS oxide film 59 allows the EEPROM area, MO
Each of the PchMOS transistor formation region and the NchMOS transistor formation region in the S transistor region is isolated.

[Step shown in FIG. 6 (b)]
A gate oxide film 60 is formed on each surface of the ROM region and the MOS transistor region.

Further, the silicon substrate 51 is covered with a resist 61 having an opening in a predetermined region on the n ⁺ type diffusion layer 58, and the gate oxide film 60 is formed on the gate oxide film 60 by photoetching.
An opening 60a communicating with the ⁺ type diffusion layer 58 is formed.

[Step shown in FIG. 6C] After the resist 61 is removed, a tunnel oxide film 62 is formed by thermal oxidation or the like.

[Step shown in FIG. 7A] Silicon substrate 5
After depositing polysilicon on 1, a resist 63 is arranged in a predetermined area of the EEPROM area, and the polysilicon is patterned to form a floating gate 64.

[Step shown in FIG. 7B] After the resist 63 is removed, a thermal oxidation step is performed, and a gate oxide film (intermediate oxide film) 6 is formed on the surface of the floating gate 64.
5 is formed.

[Step shown in FIG. 7 (c)] After a polysilicon 66 is deposited on the silicon substrate 51 including the floating gate 64, the polysilicon 66, the gate oxide film 65 and the polysilicon 66 are formed using a resist 67 having a predetermined pattern. The floating gate 64 is patterned. This allows
A two-layer gate structure in which the floating gate 64 and the control gate 66a are sequentially stacked via the gate oxide film 65 is formed. After that, the resist 67 is removed.

[Step shown in FIG. 8 (a)] Subsequently, the polysilicon 66 is patterned using a resist 68 having a predetermined pattern to form a Pch MOS transistor formation region of an EEPROM region, a MOS transistor region, and Nch.
A polysilicon gate 66b is formed in each of the regions where the MOS transistors are to be formed.

[Step shown in FIG. 8B] Next, after removing the resist 68, a thermal oxidation step is performed to cover the floating gate 64, the control gate 66a, and the polysilicon gate 66b with a thermal oxide film 69.

Then, ions are implanted using the gates 64, 66a, 66b as a mask, and a source 70 and a drain 71 are formed in each of the EEPROM region and the MOS transistor region. The ion implantation at this time is performed by E
An EPROM region and a PchMOS transistor formation region are separately formed, and an NchMOS transistor formation region is separately performed. An n-type impurity is implanted into the former and a p-type impurity is implanted into the latter.

[Step shown in FIG. 8C] Then, after an interlayer insulating film 72 is arranged so as to cover the silicon substrate 51, contact holes communicating with each source / drain, each gate and the like are formed in the interlayer insulating film 72. 72a is formed.

[Step shown in FIG. 9A] Subsequently, a metal film such as aluminum is disposed, and the metal wiring 73 is patterned.

[Step shown in FIG. 9B] Then, a protective film 74 is formed so as to cover the silicon substrate 51 including the metal wiring 73, thereby forming a MOS to be a logic part.
An EEPROM is formed with the transistors.

[0019]

In the above-mentioned conventional nonvolatile memory, a control gate and a floating gate having a two-layer polysilicon structure are required, and an n ⁺ type diffusion layer for filling is required. However, there is a problem that an increase in the number of processes is inevitable with respect to a general microcomputer process.

In US Pat. No. 5,132,239, EEPRO having a single-layered gate electrode is disclosed.
Although M is shown, since it is necessary to form an n ⁺ -type diffusion layer for filling, a photoresist pattern formation, an ion implantation step, and the like for forming the n ⁺ -type diffusion layer are required.

The present invention has been made in view of the above problems, and has as its object to provide a nonvolatile semiconductor device having a structure capable of simplifying the number of manufacturing steps and a method of manufacturing the same.

[0022]

In order to solve the above problems,
In the invention according to claim 1, the semiconductor substrate (1)
And a tunnel film (2) formed on a semiconductor substrate
A floating gate (3) formed in a predetermined region on the tunnel film and having a portion (3a) extended to a predetermined width in the tunnel region; and a floating gate (3) formed in a surface layer portion of the semiconductor substrate and having a predetermined overlap with the floating gate. A control gate (6) having a wrap portion; and an impurity formed in a surface layer of the semiconductor substrate and implanted on both sides in the width direction of a portion of the floating gate extending to a predetermined width. Thereby, the first semiconductor layer (4) formed by being connected to each other below the floating gate, and the first semiconductor layer (4) formed on the surface layer portion of the semiconductor substrate and having an overlapping portion with the floating gate, And a second semiconductor layer (5) formed on the opposite side to the semiconductor layer.

In such a configuration, since the control gate is formed on the surface of the semiconductor substrate, it is not necessary to form two conductive layers. At this time, in the tunnel region, the impurity may be laterally diffused so as to be connected below the floating gate.

Specifically, in the case where a field effect transistor is formed as a logic part together with a memory region as described in claim 2, various steps can be reduced by also serving as a manufacturing step of the field effect transistor. Can be.

For example, by combining the tunnel film forming step and the gate oxide film forming step, the tunnel film and the gate oxide film are formed to have the same thickness.

Further, by combining the first and second semiconductor layer forming steps and the control gate forming step, the first and second semiconductor layers and the control gate have the same depth. You.

In the nonvolatile semiconductor device having such a structure, as described in claim 5, the length (L) of the overlap portion between the control gate and the floating gate is determined.
2) If the width (W1) of the overlapping portion between the floating gate and the first semiconductor layer is set based on the electric field intensity (Eox) applied to the tunnel film, an electric field intensity corresponding to the writing speed can be obtained. it can.

According to the present invention, a step of forming a tunnel film (2) on the semiconductor substrate (1) in the memory area and a step of forming a gate insulating film (26) on the semiconductor substrate in the transistor area. And forming an electrode layer on a semiconductor substrate including a tunnel film and a gate insulating film, and patterning the electrode layer to form a floating gate of a nonvolatile memory and a gate electrode of a field effect transistor. Forming an insulating film (2) on the surfaces of the floating gate and the gate electrode.
Forming a source (4, 31) and a drain (5, 32) on both sides of a floating gate and both sides of a gate electrode in a surface layer portion of a semiconductor substrate, and overlapping with the floating gate. And forming a control gate (6).

As described above, the control gate is formed of the diffusion layer, and the source and the memory region and the transistor region are formed.
By forming the control gate when forming the drain, these manufacturing steps can be combined,
The manufacturing process can be simplified. In this case, the step of forming the floating gate may be combined with the step of forming the gate electrode of the field-effect transistor.

As described in claim 7, the step of forming a tunnel film and the step of forming a gate insulating film can be combined.

The symbols in the parentheses indicate the correspondence with the symbols described in the drawings which will be described in the embodiments described later.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiment shown in the drawings will be described below.

FIG. 1 shows an EEP according to an embodiment of the present invention.
1 shows the structure of a ROM. FIG. 1 shows a plurality of Es
FIG. 2 shows one unit cell of an EPROM;
(A) is a diagram showing a layout of an EEPROM,
(B) is a schematic cross-sectional view taken along the line AA of (a), (c).
FIG. 3A is a schematic cross-sectional view taken along the line BB in FIG.

As shown in FIG. 1B, a silicon substrate 1
A floating gate 3 is formed on the upper side via a tunnel film 2. This floating gate 3 is shown in FIG.
As shown in (a), it has two portions extending with a predetermined width, one of which (the left side in the drawing) forms a portion for forming a tunnel region.

On the surface layer of the silicon substrate 1 located on both sides of the other part, a source 4 and a drain 5 are provided, respectively.
Are formed. The source 4 is configured to be connected by laterally diffusing an ion-implanted impurity on both sides in the width direction of the portion below the portion where the tunnel region is formed.

As described above, the configuration is such that the floating gate 3 and the source 4 overlap. The overlap length between the floating gate 3 and the source 4 is set to L1.

Although not shown in the figure, the EEPROM shown in this embodiment has an MO as a logic unit.
The gate oxide film of the MOS transistor and the tunnel film 2 of the present EEPROM are formed in a common manufacturing process, and have a common thickness (FIG. 3A described later). reference).

Further, as shown in FIG.
Are narrowed in the vicinity of the connection point, and are configured such that the overlap width with the floating gate 3 becomes the width W1.

On the other hand, as shown in FIG. 1A, the control gate 6 is arranged at a predetermined distance from the tunnel region in a direction perpendicular to the arrangement direction of the source 4 and the drain 5. As shown in FIG. 1C, the control gate 6 is formed as an n ⁺ type diffusion layer in the surface layer of the silicon substrate 1. This control gate 6
It is configured to overlap with the floating gate 3 with the tunnel film 2 interposed therebetween. Specifically, the overlap length between the control gate 6 and the floating gate 3 is set to L2, and the overlap width is set to W2.

As shown in FIG. 1C, the tunnel region (at least the portion where the floating gate 3 and the source 4 overlap) and the vicinity of the control gate 6 (at least the portion where the floating gate 3 and the control gate 6 overlap). In (2), a thin tunnel film 2 is formed on the surface of the silicon substrate 1 so that the distance between the floating gate 3 and the surface of the silicon substrate 1 is reduced. Since the thick LOCOS oxide film 7 is formed on the surface of the silicon substrate 1 in other regions, that is, between the tunnel region and the vicinity of the control gate 6, the region between the floating gate 3 and the surface of the silicon substrate 1 is formed. The distance is getting longer.

In this embodiment, the floating gate 3
T1 is the thickness of the tunnel film 2 in the overlap portion between the gate electrode 4 and the source 4, and T2 (= T1) is the thickness of the tunnel oxide film 2 in the overlap portion between the floating gate 3 and the control gate 6.

As described above, the EEPRO shown in this embodiment is
In the case of M, the floating gate 3 is made of single-layer polysilicon, and the control gate 6 is made of an n ⁺ -type diffusion layer formed in the surface layer of the silicon substrate 1.

For this reason, as described later, the EEPROM
In this manufacturing process, various manufacturing processes conventionally required can be omitted, and the manufacturing process can be simplified.

Here, the respective size settings will be specifically described.

As described above, the floating gate 3
And the overlap length of the source 4 is L1, and the overlap length of the floating gate 3 and the control gate is L2. In addition, the floating gate 3 and the source 4
Is an overlap width of W1, and an overlap width of the floating gate 3 and the control gate 6 is W2. The thickness of the tunnel at the overlapping portion between the floating gate 3 and the source 4 is T1, and the thickness of the gate oxide at the overlapping portion between the floating gate 3 and the control gate 6 is T2.

The capacitance at the overlap between the floating gate 3 and the source 4 is Cfs, the capacitance at the overlap between the floating gate 3 and the control gate 6 is Cfg, and the capacitance at the overlap between the floating gate 3 and the drain 5 is Cfd. The capacitance of the overlapping portion between the floating gate 3 and the silicon substrate 1 (excluding the overlapping portion between the source 4 / drain 5 and the control gate 6 and the floating gate 3) is represented by Cfb. Then, the total capacity Ctotal is represented by Expression 1.

[0047]

Ctotal = Cfs + Cfg + Cfd + Cfb Further, the capacitance Cfs and the capacitance Cfd are represented by Expressions 2 and 3, respectively.
Have a relationship.

[0048]

## EQU2 ## Cfs２ (L1 × W1) ÷ T1

[0049]

Cfg∝ (L2 × W2) ÷ T2 Here, the bias applied at the time of writing, which will be described later, is
When the source applied voltage Vs is a constant voltage Vpp, the control gate applied voltage Vcg is a ground potential (GND), the drain 5 is OPEN (floating state), and the applied voltage Vsub to the silicon substrate 1 is a ground potential (GND), floating The potential Vfg of the gate 3 is shown by Expression 4.

[0050]

Vfg = (Vs × Cfs) ÷ Ctotal Then, the electric field intensity Eox applied to the tunnel oxide film at the time of writing is represented by Expression 5.

[0051]

Eox = (Vs−Vfg) ÷ T1 Therefore, the design point is the source applied voltage Vs, the floating gate potential Vfg, and the thickness T1 of the tunnel film 2.

In the EEPROM shown in this embodiment, the tunnel film 2 and the gate oxide film 26 in the MOS transistor region (see FIG. 3A) are shared, and the source applied voltage Vs is constant. Since the voltage is Vpp, the electric field strength Eox is set based on the floating gate potential Vfg.

Therefore, the floating gate potential Vf
Since g is given by Equation 5, the electric field strength Eox according to the required writing speed is obtained by reducing the capacitance Cfs of the overlapping portion between the floating gate 3 and the source 4 or increasing the total capacitance Ctotal. Can be.

As to the above, the overlap width W1 between the source 4 and the floating gate 3 may be reduced within an allowable range, and the capacitance Cfg of the overlapping portion between the floating gate 3 and the control gate 6 may be increased, that is, This can be realized by increasing the overlap length L2 between the floating gate 3 and the control gate 6.

As described above, the overlap width W1 and the overlap length L2 are set according to the required writing speed.

Next, the operation of the EEPROM having such a configuration will be described.

First, during a write operation, a high voltage is applied to the source 4 and the control gate 6 is set to the ground state (GND).

As a result, the tunnel film 2 in the region overlapping with the floating gate 3 has a high electric field, and electrons are emitted to the source 4. Thereby, EEP
Electrical writing to the ROM is performed.

On the other hand, during the erasing operation, a high voltage is applied to the control gate 6 and the source 4 is set to the ground state (GND).

As a result, the tunnel film 2 in a region where the floating gate 3 and the source 4 overlap each other has a high electric field, and electrons are injected into the floating gate 3. As a result, the EEPROM is erased.

Next, an EEPRO having such a structure will be described.
The manufacturing process of M is shown in FIGS. 2 to 4, and a method of manufacturing the EEPROM will be described with reference to these drawings.

The manufacturing steps of a PchMOS transistor and an NchMOS transistor usually formed together with an EEPROM are also shown.

[Step shown in FIG. 2 (a)] First, after an oxide film 21 is formed on the silicon substrate 1, a region of the MOS transistor region where a PchMOS transistor is to be formed is covered with a mask 22, and p-type impurities are ionized. By implantation, a p-type well layer 23 is formed in an Nch-type MOS transistor formation region of the EEPROM region and the MOS transistor region.

[Step shown in FIG. 2B] Next, the mask 2
After removing 2, the region where the p-type well layer 23 is formed is further covered with a mask 24, and an n-type impurity is ion-implanted to form an n-type well layer 25 in a region where a PchMOS transistor is to be formed.

[Step shown in FIG. 2C] After removing the mask 24, a so-called LOCOS step is performed.
EEPROM area, MOS by LOCOS oxide film 7
Each of the PchMOS transistor formation region and the NchMOS transistor formation region in the transistor region is isolated.

[Steps shown in FIG. 3 (a)]
The tunnel film 2 and the gate oxide film 26 are simultaneously formed on the respective surfaces of the ROM region and the MOS transistor region.

[Step shown in FIG. 3B] Silicon substrate 1
After polysilicon is deposited thereon, a resist 27 is disposed in a predetermined area of the EEPROM area and a predetermined area of the MOS transistor area, and the polysilicon is patterned to form a resist pattern.
A floating gate 3 is formed in the EPROM area, and a polysilicon gate 28 is formed in each of the PchMOS transistor formation area and the NchMOS transistor formation area.

[Step shown in FIG. 3C] Next, after removing the resist 27, a thermal oxidation step is performed to remove the floating gate 3 and the polysilicon gate 28 from the thermal oxide film 29.
Cover with.

After ion implantation using the gates 3 and 28 as a mask, the implanted ions are thermally diffused, so that the source 4, 31 and the drain 5, 32 are respectively provided in the EEPROM region and the MOS transistor region.
To form

At this time, although not shown in the cross section of FIG. 3C, n ⁺
A mold diffusion layer is formed at the same time.

At this time, by performing ion implantation obliquely or controlling thermal diffusion, the source 4 is connected below the portion constituting the tunnel region of the floating gate 3 and the control gate 6 is connected. And the floating length of the floating gate 3 is L2.

At this time, the ion implantation is performed by using EEPRO.
An M region and a region where a PchMOS transistor is to be formed;
The process is performed separately for each NchMOS transistor formation region. An n-type impurity is implanted into the former and a p-type impurity is implanted into the latter.

[Step shown in FIG. 4A] After the interlayer insulating film 33 is disposed so as to cover the silicon substrate 1,
A contact hole communicating with each source 4 / drain 5 and each gate is formed in the interlayer insulating film.

[Step shown in FIG. 4B] Subsequently, a metal film such as aluminum is disposed, and the metal wiring 34 is patterned.

[Step shown in FIG. 4C] Then, the protective film 3 is formed so as to cover the silicon substrate 1 including the metal wiring 34.
By forming 5, an EEPROM is formed together with a MOS transistor serving as a logic part.

As described above, the EEPR in this embodiment is
The OM manufacturing process can reduce the following processes as compared with the above-described conventional EEPROM manufacturing process.

That is, the EEPRO shown in FIG.
The step of forming an n ⁺ type diffusion layer for M and the step of forming the tunnel film 2 shown in FIGS. 6A to 6C can be reduced.
Further, since the step of forming the floating gate 3 shown in FIG. 7A can be combined with the step of forming the polysilicon gate 28 in the MOS transistor region (see FIG. 3B), only the floating gate 3 is formed. It is also possible to reduce the number of steps required to perform the process.

As described above, the EEPROM according to the present embodiment can be manufactured with a smaller number of steps than in the related art.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an EEPROM according to an embodiment of the present invention.

FIG. 2 is a view showing a manufacturing process of the EEPROM shown in FIG. 1;

FIG. 3 is a diagram showing a manufacturing process of the EEPROM following FIG. 2;

FIG. 4 is a view showing a manufacturing process of the EEPROM following FIG. 3;

FIG. 5 is a view showing a manufacturing process of a conventional EEPROM.

FIG. 6 is a view showing a manufacturing process of the EEPROM following FIG. 5;

FIG. 7 is a view showing a manufacturing step of the EEPROM following FIG. 6;

FIG. 8 is a view showing a manufacturing process of the EEPROM following FIG. 7;

FIG. 9 is a view showing a manufacturing process of the EEPROM following FIG. 8;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Tunnel film, 3 ... Floating gate, 4 ... Source, 5 ... Drain, 6 ... Control gate, 7 ... LOCOS oxide film.

Continued on front page F-term (reference) 5F001 AA01 AA25 AA30 AB02 AB06 AB09 AC01 AD12 AD14 AD15 AE02 AE07 AE08 AG02 AG12 5F083 EP02 EP03 EP13 EP15 EP22 EP38 EP42 ER03 ER06 ER14 ER16 ER21 GA28 PR12 PR36 PR37 PR37

Claims (7)

[Claims] 1. A semiconductor substrate (1), and a tunnel film (2) formed on the semiconductor substrate.
A floating gate (3) formed in a predetermined region on the tunnel film and having a portion (3a) extending at a predetermined width in the tunnel region; and a floating gate (3) formed in a surface layer portion of the semiconductor substrate, A control gate (6) having a predetermined overlap portion; and a control gate (6) formed on a surface layer of the semiconductor substrate and injected into both sides in the width direction of a portion of the floating gate extending to the predetermined width. A first semiconductor layer (4) configured to be connected to each other below the floating gate by laterally diffusing the impurities, and formed in a surface layer portion of the semiconductor substrate and having an overlapping portion with the floating gate. A second semiconductor layer (5) formed on a side of the floating gate opposite to the first semiconductor layer; And a non-volatile semiconductor device comprising: 2. A nonvolatile semiconductor memory comprising a nonvolatile memory having a floating gate (3) and a control gate (6) and a field effect transistor having a single-layer gate structure formed on a semiconductor substrate (1). In the device, a memory region in which the nonvolatile memory is formed and a transistor region in which the field-effect transistor is formed are separated by an insulating film (7) formed on the semiconductor substrate. A tunnel film (2) formed on the semiconductor substrate;
A floating gate formed in a predetermined region on the tunnel film and having a portion extending to a predetermined width in the tunnel region; and a predetermined overlapping portion formed in a surface layer portion of the semiconductor substrate and overlapping the floating gate. And a control gate formed on the surface of the semiconductor substrate, the impurity being implanted on both sides in the width direction of a portion (3a) of the floating gate extending to the predetermined width. A first semiconductor layer (4) configured to be connected to each other below the floating gate by being diffused; a first semiconductor layer (4) formed in a surface layer portion of the semiconductor substrate; A second semiconductor layer (5) formed on the side opposite to the first semiconductor layer. In the transistor region, a gate insulating film (2) formed on the semiconductor substrate is provided.
6), a gate electrode (28) formed in a predetermined region on the gate insulating film, and a source (31) and a drain formed on a surface layer of the semiconductor substrate so as to be located on both sides of the gate electrode. (32) A non-volatile semiconductor device comprising: 3. The non-volatile semiconductor device according to claim 2, wherein said tunnel film and said gate oxide film are formed with the same thickness. 4. The non-volatile semiconductor device according to claim 1, wherein the first and second semiconductor layers and the control gate have the same depth. 5. A length (L2) of an overlapping portion between the control gate and the floating gate and a width (W1) of an overlapping portion between the floating gate and the first semiconductor layer are different from each other in the tunnel film. The nonvolatile semiconductor device according to claim 1, wherein the non-volatile semiconductor device is set based on the electric field strength (Eox). 6. A nonvolatile semiconductor memory comprising a nonvolatile memory having a floating gate and a control gate, and a field effect transistor having a single-layer gate structure formed on a semiconductor substrate. In the method for manufacturing a device, a step of element-isolating a memory region forming the non-volatile memory and a transistor region forming the field-effect transistor in the semiconductor substrate; and forming a tunnel on the semiconductor substrate in the memory region. Forming a film (2); forming a gate insulating film (26) on the semiconductor substrate in the transistor region; and forming an electrode layer on the semiconductor substrate including the tunnel film and the gate insulating film. And the electrode layer is patterned to form the floating gate and the non-volatile memory of the nonvolatile memory. Forming a gate electrode (28) of the field effect transistor; forming an insulating film (29) on the surface of the floating gate and the gate electrode; and forming a floating gate on a surface portion of the semiconductor substrate. And the source (4,
31) and a step of forming the drain (5, 32) and forming the control gate overlapping with the floating gate. 7. The method according to claim 6, wherein the step of forming the tunnel film and the step of forming the gate insulating film are performed in the same step.