JP2000340573A - Bipolar transistor and manufacturing method thereof - Google Patents

Abstract

[PROBLEMS] To provide a power bipolar transistor capable of increasing a switching time and increasing a current amplification factor while widening a base width and a safe operation area, and a method of manufacturing the same. . SOLUTION: A base layer 2 of a second conductivity type (p-type) is provided in contact with a collector layer 1 made of a semiconductor of a first conductivity type (n-type). ) Emitter region 3 is provided. And the base layer 2
Are formed such that the impurity concentration at the junction with the collector layer 1 is higher than the impurity concentration at the junction with the emitter region 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a bipolar transistor. More specifically, the present invention relates to a bipolar transistor that can increase the current amplification factor and shorten the switching time even when the base width is increased in order to widen the safe operation area by using a power bipolar transistor or the like.

[0002]

2. Description of the Related Art Conventional power bipolar transistor
Is, for example, n as shown in FIG. ⁺On the shape layer 21a
To 10¹²-10¹⁶atm / cm^Three(Hereinafter simply cm^-3When
N) of impurity concentration of about^-The shape layer 21 is formed
P-type layer by diffusion on the front side of FZ wafer to be
Is formed to a depth of about 30 to 50 μm to form a base region 22.
Then, an n-type impurity is diffused into the base
It is configured by forming a mitter region 23.
The impurity profile of this structure is as shown in FIG.
The emitter layer (n⁺Type) high impurity concentration, base
The region 22 (p-type) becomes lower, and the collector
Layer (n^-Shape) and the semiconductor substrate (n⁺Shape) is high concentration
It is formed every time.

In a power bipolar transistor, 18
Since a wide safe operation area that does not break even at a high voltage of about 00 to 2000 V is required, the base region 22 is formed deep as described above, and is usually formed by long-time diffusion. When the base region 22 becomes deeper (greater base width W _B is), the minority carrier concentration when turning off the transistor, as minority carriers concentration in each region in FIG. 7 is shown, the minority carriers in the base region Since the concentration is large and the running time of the minority carrier is also long, the switching time is long. In FIG. 7, portions surrounded by broken lines indicate a depletion layer between the emitter and the base and between the base and the collector, respectively.

[0004]

As described above, in a bipolar transistor having a high breakdown voltage, the base width is increased,
There is a problem that the elimination of minority carriers takes a long time and the switching time is delayed. On the other hand, if the impurity concentration in the base region is increased in order to shorten the running time of minority carriers, the current injection efficiency is reduced, and the current amplification factor is reduced. Further, if the base width is narrowed (shallow the depth of the base region) in order to reduce the minority carriers in the base region, the breakdown voltage becomes weak and the device cannot be used for high power. Therefore, there is a problem that a power bipolar transistor having a large current amplification factor and a high switching speed cannot be obtained.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and it is an object of the present invention to increase the switching time and increase the current amplification factor while widening the base width and widening the safe operation area. And a method for manufacturing the same.

[0006]

SUMMARY OF THE INVENTION A bipolar transistor according to the present invention has a collector layer made of a semiconductor of a first conductivity type, a base layer of a second conductivity type provided in contact with the collector layer, and a base layer formed in the base layer. The base layer is formed such that an impurity concentration at a junction side with the collector layer is higher than an impurity concentration at a junction side with the emitter region.

Since the difference in impurity concentration is provided in the base layer as described above, the difference in impurity concentration from the emitter region can be increased to improve the current injection efficiency, and the layer having a higher impurity concentration can be provided on the collector layer side. Is provided, minority carriers when the operation of the transistor is turned off can be quickly captured and eliminated, and the switching speed can be increased. Moreover, since the base layer is composed of both the high impurity concentration layer and the low impurity concentration layer, a sufficient thickness can be secured.
As a result, a high breakdown voltage, a high switching speed, and a high current amplification factor can be achieved even for high power.

Since the base layer is formed in a laminated structure including at least an epitaxially grown layer having a high impurity concentration and an epitaxially grown layer having a low impurity concentration, a layer having a high impurity concentration and a thin layer can be easily formed on the base layer. can do.

By mesa etching the periphery of the operation region of the base layer, even if the base layer is formed by the epitaxial growth layer, the operation region can be partitioned.

The method of manufacturing a bipolar transistor according to the present invention is directed to a method of manufacturing a bipolar transistor, comprising the steps of: forming a second conductive type having a high impurity concentration on a low impurity concentration semiconductor layer of a semiconductor wafer having a first impurity type semiconductor layer serving as a collector layer on the surface; A semiconductor layer is epitaxially grown, and a low impurity concentration second conductivity type semiconductor layer is epitaxially grown on the second conductivity type semiconductor layer. High impurity concentration first emitter region
Forming a conductive type semiconductor region and forming a mesa groove in the second conductive type semiconductor layer on the outer peripheral side of the emitter region so as to reach the collector layer, thereby operating with the second conductive type semiconductor layer as a base layer; It is characterized in that it is divided into regions to be divided.

A high impurity concentration second conductivity type semiconductor layer is further epitaxially grown on the low impurity concentration second conductivity type semiconductor layer, and the emitter region penetrates the high impurity concentration second conductivity type semiconductor layer. And the low impurity concentration of the second
By forming the conductive type semiconductor layer and the pn junction, the emitter electrode can be formed with good ohmic contact without fluctuation of the impurity concentration due to the diffusion step.

[0012]

Next, a bipolar transistor and a method of manufacturing the same according to the present invention will be described with reference to the drawings.

The bipolar transistor according to the present invention is shown in FIG.
As shown in FIG.
A base layer 2 of a second conductivity type (p-type) is provided in contact with collector layer 1 made of a conductivity type (for example, n-type) semiconductor;
A first conductivity type (n-type) emitter region 3 is provided in the base layer 2. The base layer 2 is characterized in that the impurity concentration at the junction with the collector layer 1 is higher than the impurity concentration at the junction with the emitter region 3.

The collector layer 1 has, for example, a high impurity concentration (low resistance) layer 1a doped with phosphorus to a thickness of about 10 μm to about 10 ¹⁸ to 10 ²⁰ cm ⁻³ , and a thickness of about 10 μm to about 10 ¹² μm. An n ⁻ -type low-impurity-concentration (high-resistance) layer 1 b doped with, for example, phosphorus at about 10 ¹⁶ cm ⁻³ is formed. For this, what is called a normal FZ wafer can be used.

In the example shown in FIG.
A first layer 2a made of a p ^{+ -type} high impurity concentration layer of about 10 ¹³ to 10 ¹⁷ cm ^-3 doped with diborane or the like and having a thickness of about 20 μm, for example, 20 μm; thick, such as diborane p 10 ^12-10 about ¹⁶ cm ^-3 is doped ^- a second layer 2b consisting form low impurity concentration layer, about 1 to 20 [mu] m, for example, a thickness of 10 [mu] m, diborane and the like Doped 10 ¹⁵
And a third layer 2c formed of a p ^{++ type} high impurity concentration layer of about 10 to ¹⁸ cm ^-3 . The first layer 2a is a layer for making it easier to capture electrons remaining in the base region 2 and shortening the switching time when the operation of the transistor is turned off, as described later. By increasing the concentration difference at the boundary with the emitter region 3,
A layer for improving the current amplification factor h _FE to improve the injection efficiency of the current. The third layer 3c is a layer for maintaining ohmic contact with the semiconductor layer when the electrode 8 is formed of Al or the like. Even when the third layer 3c is not an epitaxial growth layer, the third layer 3c can A diffusion region having a high impurity concentration may be formed only in a portion to be formed.

The base layer 2 has a high impurity concentration layer on the collector layer 1 side and a low impurity concentration layer at a junction with the emitter region 3 as described above. These layers do not need to be clearly defined, and the impurity of the first layer 2a may be diffused during the growth of the second layer 2b with a low impurity concentration to form a gentle impurity concentration gradient. In short,
As described above, it is only necessary to provide a layer that can capture minority carriers as easily as possible when the operation of the transistor is turned off, and that a low impurity concentration region for increasing current injection efficiency is provided on the emitter region 3 side. And other concentration distributions are not so limited. However, it is preferable that the concentration of the lower layer on the collector layer 1 side is as high as possible, and it is difficult to increase the depth to about 30 to 50 μm and increase the concentration above the depth by a normal diffusion method. However, the above-described profile of the impurity concentration can be formed by epitaxial growth. Further, since the base layer 2 is formed of an epitaxial growth layer, it is formed in a wide range similarly to the collector layer 1, and a section of an operation region as a base of the transistor is:
As shown in FIG. 1, a mesa groove 4 is formed around the periphery of the mesa groove, and a glass protective film 5 is provided in the groove to form a base layer serving as an operation region.

The emitter region 3 is formed by diffusion of phosphorus or the like into the base layer 2, and penetrates through the third layer 2c to form the second region.
At a depth of, for example, about 15 μm, the impurity concentration on the surface is set to, for example, 1 × 10 ¹⁹ , such that the bottom of the layer 2b covers the layer 2b.
It is formed to about cm ^-3 . The emitter region 3 has an emitter electrode 9 formed of Al or the like on the surface thereof as in the case of the above-described base region, so that it is necessary to obtain an ohmic contact. It is formed with a high impurity concentration. Reference numeral 6 denotes an insulating film such as SiO ₂ provided on the surface of the semiconductor layer, and a collector electrode 7 is formed on the back surface of the semiconductor substrate (collector layer 1) by vapor deposition of Al or the like.

FIG. 2 shows a profile of the impurity concentration from the emitter region 3 to the collector layer 1 having this structure. That is, the n ^{+ type} region on the surface side is the emitter region 3 and the next p ^{− type} region is the second
A layer 2b, a p ^{+ type} region is a first layer 2a of the base layer 2, and an n ^{− type} layer is a low impurity concentration layer 1b of the collector layer 1.
The n ^{+ -type} layer is the high impurity concentration layer 1a of the collector layer 1. In addition, since the profile of the impurity concentration in the depth direction of the portion where the emitter region 3 is formed is shown, the third layer 2c of the base layer 2 does not appear to be offset by the emitter region 3, but is not offset. The profile of the state is indicated by a broken line.

Next, a method of manufacturing the bipolar transistor will be described with reference to FIG.

First, a p-type impurity such as diborane is doped on the low impurity concentration layer 1b of the FZ wafer made of a semiconductor substrate having the low impurity concentration layer 1b formed on the high impurity concentration layer 1a as described above. After growing silicon, the first layer 2a of the p ^{+ -type} base layer 2 having the impurity concentration described above is
For example, epitaxial growth of about 20 μm is performed (FIG. 3
(See (a)).

Next, as shown in FIG. 3 (b), similarly to silicon is grown while doping p-type impurities such as diborane, p impurity concentration of the above ^- the second layer of the base layer 2 in the form 2b is epitaxially grown, for example, by about 20 μm. The impurity amount is further increased, and the p ⁺⁺ -type third layer 2c having the impurity concentration described above is grown, for example, to about 10 μm.

Next, as shown in FIG. 3 (c), a mask 11 of SiO ₂ or the like is provided on the surface, and only the location where the emitter region is to be formed is opened. Heat treatment at ~ 1230 ° C
By diffusing phosphorus for about a time, the emitter region 3 having an impurity concentration of a profile as shown in FIG.
To form An oxide film is further formed on the semiconductor layer exposed on the opening and on the mask 11 during this heat treatment.

Thereafter, an insulating film 12 of SiO ₂ or the like is further formed on the surface, and only a portion where a mesa groove for defining a base region at a predetermined interval from the emitter region 3 is formed is opened. Then, the base layer 2 is etched by an etchant such as hydrofluoric nitric acid to reach the collector layer 1 to form a mesa groove 4. Thereafter, a glass paste is applied to the mesa groove 4 by a doctor blade method or the like, and
By sintering at about ° C, a glass protective film 5 is formed on the surface of the mesa groove 4 (see FIG. 3D).

Thereafter, patterning for forming an electrode is formed on the insulating film 12, and Al or the like is deposited and patterned to form a base electrode 8 and an emitter electrode 9, thereby forming a semiconductor substrate (collector layer) 1. By forming Al and the like on the back surface by vapor deposition and the like to form the collector electrode 7, the bipolar transistor having the structure shown in FIG. 1 can be obtained.

In the above-described example, a p ⁺⁺ -type high impurity concentration layer is formed on the surface of the base layer 2 by epitaxial growth, but this layer is formed with a high impurity concentration in order to obtain an ohmic contact with the emitter electrode 8. Therefore, it is needless to say that a high impurity concentration region may be formed by diffusion only in a portion where an electrode is to be formed, as in the related art. Further, although the base layer 2 is formed by an epitaxial growth layer and a mesa groove is formed to divide the region, the base layer 2 may be formed by selectively epitaxially growing only at a position where the base region is formed. Alternatively, a buried layer of ap ^{+ -type} high-concentration impurity may be formed in advance in the collector layer, and the base region may be formed by diffusion so as to reach the buried layer. Next, the operation of the bipolar transistor of the present invention will be described. The current amplification factor h _FE of the transistor is given by the following equation (1).

H_FE= I_C/ I_B= (D_n/ D_p) ・ (Q_E/ Q_B(1) where I_CIs the collector current, I_BIs the base current, D_n
Is the diffusion coefficient of electrons through the base layer, D_pThrough the base layer
Hole diffusion coefficient, Q_EIs the charge of the emitter, Q _BIs
The charge amount is the impurity concentration of each region.
Is proportional to D_n/ D_pIs the impurity concentration of the p-type base layer
The lower the is, the larger the_E/ Q_BIs the emitter
High impurity concentration in the region and low impurity concentration in the base layer
It gets bigger. Therefore, it contacts the emitter region
The current amplification factor h decreases as the impurity concentration of the base layer decreases._FEIs large
It will be good.

On the other hand, the switching time t _stg is related to the _transit time τ _F of the minority carrier base layer by the following equation (2), and the transit time τ _F is given by τ _F = W _B / ( 2
D _n ). Therefore, as the base width W _B is small, also the larger the impurity concentration of the base layer D _n
Becomes large, and the traveling time can be shortened.

T _stg = K · (0.6 / ω _t + τ _F / 2) (2) where K is a proportional constant and ω _t is a time constant. To speed the switching time is required as soon as possible remove minority carriers in the base region when further turning off the current, from the point of view, the base width W _B is the thickness of the base region Should be as small as possible and the impurity concentration for capturing minority carriers should be as high as possible.

Therefore, it is preferable that the impurity concentration of the base layer is lower (lower) from the viewpoint of the current amplification factor. However, the impurity concentration is higher (higher) from the viewpoint of the switching time.
Further, the narrower the base width, the better. However, when the base width is reduced, the breakdown voltage is reduced as described above,
To obtain a high breakdown voltage of about 000V, it is necessary to increase the base width W _B.

According to the present invention, the base layer is formed to be thick with different impurity concentrations so that the base layer has a high impurity concentration layer on the collector layer side and a low impurity concentration layer at the junction with the emitter region. I have. Therefore, Q _E / Q _B related to the current amplification factor can be made sufficiently large because the junction with the emitter region is formed in the base layer having a low impurity concentration, so that a large current amplification factor can be obtained. it can. On the other hand, with respect to the switching time, the high impurity concentration layer provided on the collector layer side increases the electron diffusion speed D _{n and} can reduce the transit time τ _F , and the minority carriers are reduced by the high impurity concentration. Capture becomes easier, and the switching time can be shortened. Further, since the base layer is formed to be thicker with the low impurity concentration layer and the high impurity concentration layer, the breaking strength can be sufficiently improved. In other words, in other words, in the transistor of the present invention, the base layer is formed to be thicker with the low impurity concentration layer and the high impurity concentration layer. Since the layer is made faster by a layer with a higher impurity concentration (dense), it acts as a small base width for the switching time. As a result, a bipolar transistor having a large current amplification factor and a short switching time is obtained.

[0031] The bipolar transistor of the present invention shown in FIG. 1, the results were examined by simulating the relationship between the switching time and the current amplification factor, as indicated by A in FIG. 4, the current amplification at the switching time t _stg of 3μs A rate h _FE of about 50 is obtained, and the current amplification rate is significantly improved from about 30 at a switching time of 3 μs of the conventional relation B. If the current amplification rate is about 30 in the transistor of the present invention, 1.5μ switching time
s. Regarding the breakdown voltage BV _CBO , the transistor of the present invention has a thickness of 1800 to 2000
The distribution was about V, which was almost the same as that of the transistor having the conventional structure. Therefore, even when a layer having a high impurity concentration is provided in the base layer, the withstand voltage is improved by the thickness thereof, and the withstand voltage is not affected at all.

In the above-described example, the bipolar transistor is used alone. However, it goes without saying that a bipolar transistor incorporated in an IC or the like can be incorporated as a transistor having a similar structure.

[0033]

As described above, according to the present invention,
A power bipolar transistor with high characteristics that can increase the current amplification factor and / or shorten the switching time (faster switching speed) while maintaining a safe operation area wide and withstanding voltage as high as before. A transistor is obtained.

[Brief description of the drawings]

FIG. 1 is an explanatory cross-sectional view of one embodiment of a bipolar transistor of the present invention.

FIG. 2 is a view showing a profile of an impurity concentration of each semiconductor layer having the structure of FIG. 1;

FIG. 3 is an explanatory diagram illustrating a manufacturing process of the transistor in FIG. 1;

FIG. 4 is an explanatory diagram showing the relationship between the current amplification factor and the switching time of the transistor of the present invention in comparison with the characteristics of a conventional transistor.

FIG. 5 is an explanatory diagram showing a structure of a conventional bipolar transistor.

6 is an explanatory diagram showing a profile of an impurity concentration of each semiconductor layer of the transistor in FIG.

FIG. 7 is an explanatory diagram showing a state of minority carriers when the transistor in FIG. 5 is off.

[Explanation of symbols]

 Reference Signs List 1 collector layer 2 base layer 2a first layer 2b second layer 3 emitter region 4 mesa groove

Claims (5)

[Claims] 1. A semiconductor device comprising: a collector layer made of a semiconductor of a first conductivity type; a base layer of a second conductivity type provided in contact with the collector layer; and an emitter region of a first conductivity type provided in the base layer. Wherein the base layer is formed such that the impurity concentration at the junction with the collector layer is higher than the impurity concentration at the junction with the emitter region. 2. The bipolar transistor according to claim 1, wherein said base layer is formed by a laminated structure including at least an epitaxially grown layer having a high impurity concentration and an epitaxially grown layer having a low impurity concentration. 3. The bipolar transistor according to claim 2, wherein the operation region of the base layer is partitioned by mesa etching. 4. A high conductivity second conductivity type semiconductor layer is epitaxially grown on a low impurity concentration semiconductor layer of a semiconductor wafer having a low impurity concentration first conductivity type semiconductor layer as a collector layer on a surface thereof. A low impurity concentration second conductivity type semiconductor layer is epitaxially grown on the second conductivity type semiconductor layer, and a high impurity concentration is formed as an emitter region by diffusion so as to have a pn junction with the low impurity concentration second conductivity type semiconductor layer. Forming a first conductivity type semiconductor region, and forming a mesa groove in the second conductivity type semiconductor layer on the outer peripheral side of the emitter region so as to reach the collector layer.
A method for manufacturing a bipolar transistor, comprising dividing a conductive semiconductor layer into a region that operates as a base layer. 5. A high impurity concentration second conductivity type semiconductor layer is further epitaxially grown on said low impurity concentration second conductivity type semiconductor layer, and said emitter region is replaced with said high impurity concentration second conductivity type semiconductor layer. The method according to claim 4, wherein the pn junction is formed so as to have a pn junction with the second conductive semiconductor layer having a low impurity concentration.