JP2000333280A - Electronic exchange - Google Patents

Abstract

(57) [Problem] To provide an electronic exchange which can efficiently cope with communication at a plurality of transfer rates, such as packet data, based on a time-division switch which can be configured relatively inexpensively. SOLUTION: In addition to a basic transfer clock, a clock line having a different frequency corresponding to a required transfer rate is provided on an exchange bus, a data transfer clock is selected, and the data transfer clock is selected and inputted to the selected clock. A bus that communicates on the bus at the transfer rate of the selected clock line by providing an input / output port that can send and receive data in synchronization with the clock and selecting the same transfer clock between the input port and the output port for communication An electronic exchange using a time-division switch can provide communication paths of various communication speeds without using an external multiplexing device or the like, and can have a simple configuration at low cost.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a conventional circuit-switching type communication system having a fixed communication speed of 64 Kbps,
And packet-switching variable-speed communication such as
The present invention relates to a circuit-switched exchange such as a PBX that also supports exchange of high-speed communication of Kbps or more.

[0002]

2. Description of the Related Art FIG. 4 is a configuration diagram of a bus type time division switch in a conventional electronic exchange.

As shown in FIG. 4, a bus type time division switch used in a conventional electronic exchange comprises an input / output port module # 0201 and an input / output port selection switch 202.
, Control table 203, control system interface 2
04, a data highway 211, a data transfer clock line 212, a reference frame signal line 213, a control bus 214, a serial output port 215, a serial input port 216, a switch module 230, and a switch module 231. I have.

A plurality of switch modules 201, 230, and 231 having input / output ports connected in parallel to an exchange bus composed of a serial data line, a single data transfer clock line, and a frame reference signal line. , Synchronously with the clock of the bus, communication data is selected in units of 8 bits, and the receiving port takes in the data at the same timing as the transmitting port inserts, thereby performing the switching operation.

[0005] Further, the function and operation of each block will be described. As shown in FIG.
11, a data transfer clock line 212 and a data frame reference signal line 213. Then, it is connected to a shared bus, and at the timing of an arbitrary bus, information is usually taken in units of 8 bits, and an exchange operation is performed by inserting and inserting the information. I / O selection switch 20 on the I / O port side
2, a time slot on the exchange bus is selected according to the contents set in the control table 203, and input or output to the input / output ports 215 and 216. The setting in the control table 203 is performed by the control system interface 20.
4 is set by a CPU or the like connected to the control bus 214.

By these functional operations, burst data traffic such as packet communication can be taken into the time division switch.

[0007]

However, in recent network equipment development and construction of public networks and private networks,
2. Description of the Related Art Due to the trend of fusion between a voice (circuit-switched) network and a data-based (packet-switched) network, a demand has arisen for a circuit-switched exchange such as a PBX to incorporate a data-based network as a network device.

However, data on a data network represented by a LAN has characteristics such as a variable data flow rate and the occurrence of bursty data traffic. The time-division switch system based on fixed-rate traffic has a problem. However, there is a problem that a case in which it is not possible to cope efficiently occurs.

An ATM (Asynchronous Transfer Mode) system has been proposed as a system for integrating circuit switching and packet switching. The ATM system is a system for simply switching fixed-length packets called cells. Each packet has a destination address area, and on the basis of the address set therein, a type of fixed-length packet exchange called an ATM switch is required. However, in the case of ATM, an address search is required for every packet of several tens of bytes, so that a complicated mechanism such as a high-speed memory and a search means is required, and it is difficult to adapt to a small-capacity exchange or the like from the viewpoint of cost. Met.

In view of the above-mentioned problems, the present invention provides an electronic exchange using a bus-type time-division switch which can efficiently cope with communication at a plurality of transfer rates such as high-speed packet data and can be constructed relatively inexpensively. The purpose is to:

[0011]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention relates to an electronic exchange having a bus type time division switch, wherein a basic transfer clock is provided on an exchange bus of the bus type time division switch. In addition, provide input / output ports that can transmit and receive data in synchronization with the selected clock by providing clock lines with different frequencies corresponding to the required transfer rate, selecting the data transfer clock, and inputting it to the selected clock By selecting the same transfer clock between the input port and the output port which perform communication, communication on the bus can be performed at the transfer rate of the selected clock line.

According to the present invention, an electronic exchange accommodating communications at various communication speeds is constituted by a time division switch capable of providing communication paths at various communication speeds without using an external multiplexing device or the like. Therefore, it is possible to provide an inexpensive and simple configuration of an electronic exchange that can efficiently cope with communication at a plurality of transfer rates such as high-speed packet data.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention according to claim 1 of the present invention provides a speed conversion buffer memory having a function of determining a plurality of data transfer clock lines and a clock to be taken into an input / output communication port from the data transfer clock line. A bus-type time-division switch which is configured by adding an input / output port having a function of allocating a plurality of channels to the input / output port with a plurality of time slots and which can be exchanged for communication with different communication speeds or burst data communication. This is the electronic exchange used, and the conventional time-division switch has a structure of 64 per channel.
Channel bandwidth is divided into Kbps units, usually 2Mh
While transfer clocks such as z, 4 Mhz, and 8 Mhz are fixedly used as the data transfer rates of the input / output lines and the exchange bus, according to the present invention, the configuration is simpler than other switch elements. By expanding the bus-type time-division switch, the same time-division switch provides channels of different communication bands in addition to communication in units of 64 Kbps. This has the effect that the electronic exchange can be made possible.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a configuration diagram of a time division switch in an electronic exchange according to Embodiment 1 of the present invention.

As shown in FIG. 1, this time division switch is
An input / output port module # 0101, a data transfer clock selector 102, a clock selection register 103,
I / O port selection switch 104 and control table 10
5, a control system interface 106, a data highway 111, a data transfer clock line (1) 112,
A data transfer clock line (2) 113, a data transfer clock line (3) 114, a reference frame signal line 115,
A control bus 116, a data transfer clock selector control line 117, an input / output port operation clock 118, a clock selection register data setting line 119, an input / output port selection switch control line 120, a control table data setting line 121, Output port module # m130, input / output port module # n131, clock generator 13
2 is provided.

In the first embodiment, for simplicity of description, a case where one high-speed transfer clock is added to the conventional example shown in FIG. 4 and two low-speed and high-speed transfer rates are provided. An example is shown.

FIG. 2 shows the state of two types of data transfer clocks in the first embodiment. The capacity of the exchange,
Depending on the switching speed and the application, the additional transfer clock line may be provided with a plurality of clock lines so long as it is synchronized with the frame clock, so that it can support various transfer rates. No effect on effect.

Next, the basic operation of the time division switch according to the first embodiment will be described. Embodiment 1
In the same manner as in the conventional time-division switch shown in the conventional example, there is an input port and an output port, and the time-division multiplexed data coming from the input port is allocated to the input port of the time-division switching bus. At the same time slot timing, data is transferred at the same time slot selected at the input / output port. It can be carried out.

FIG. 3 shows an outline of clock selection and a data highway. As shown in the figure, in the time slot in which the clock 2 is selected, a different rate communication is performed from the time slot in which the clock 1 is selected.

Next, the function and operation of each block in the first embodiment will be described.

The exchange bus includes a data highway 111, a data transfer clock line (1) 112, a data transfer clock line (2) 113, a data transfer clock line (3) 114,
It is composed of each signal line of the data frame reference signal 115. In the first embodiment, all the reference clocks are supplied by the clock generator 132. The input / output port modules 101, 130, and 131 connected to the exchange bus perform an exchange operation by fetching and inserting information, usually in units of 8 bits, at an arbitrary bus timing. The data transfer clock used in each time slot is supplied to the data transfer clock line (1) by the clock selector 102.
To (3) 112, 113, 114. The selected content is determined by the clock selection register 103.

On the input / output port side, the control table 105
The time slot on the exchange bus is selected in accordance with the contents set in (1), and input or output to the input / output ports 122 and 123. The settings in the control table 105 are set by a CPU or the like connected to the control bus 116 via the control system interface 106.

By these functional operations, communication paths of different communication speeds can be provided by the bus type time division switch.

[0025]

As is apparent from the above description, the present invention is based on a time division switch which can be constructed relatively inexpensively and can efficiently integrate variable rate communication such as packet data. By providing a function of operating the division switch in units of time slots for communication data and sending out multiple slots to the same port and a function of dynamically controlling it, communication of fixed rate communication such as voice that is conventionally supported is provided. In addition, it is possible to cope with variable-rate communication such as packet communication, which has the effect that an electronic exchange that can cope with so-called multimedia traffic can be configured at low cost.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a time-division switch in an electronic exchange according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a high-speed clock and a low-speed clock in a simultaneous division switch.

FIG. 3 is an explanatory diagram of a data highway using simultaneous division switches.

FIG. 4 is a configuration diagram of a time-division switch in a conventional electronic exchange.

[Explanation of symbols]

 101 I / O port module # 0 102 Data transfer clock selector 103 Clock selection register 104 I / O port selection switch 105 Control table 106 Control interface 111 Data highway 112 Data transfer clock line (1) 113 Data transfer clock line (2) 114 Data Transfer clock line (3) 115 reference frame signal line 116 control bus 117 data transfer clock selector control line 118 input / output port operation clock 119 clock selection register data setting line 120 input / output port selection switch control line 121 control table data setting line 130 input Output port module #m 131 I / O port module #n 132 Clock generator

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04L 12/50

Claims (1)

[Claims] An input / output port having a function of determining a clock to be taken into an input / output communication port from the data transfer clock line; a speed conversion buffer memory; and a time slot in the input / output port. An electronic exchange characterized by using a bus-type time-division switch, which is configured by adding a function of allocating a plurality of channels to each other, and can also be used for communication with different communication speeds or burst data communication.