JP2000332145A - Circuit material for resin-sealed semiconductor device, the resin sealed semiconductor device using the same and manufacturing method for the circuit material - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance occupancy ratio of semiconductor elements to improve the packing density on a circuit board by placing an outer frame, an independently disposed package, terminals independently disposed inside the frame, and electrically insulative resin members interposed between them. SOLUTION: A circuit material 1 comprises an outer frame 2, a die pad 3 independently disposed inside the frame 2, a plurality of terminals 4 mutually independently disposed on approximately the same plane inside the frame 2, and electrically insulative resin members 5 interposed between the frame 2, the die pad 3 and each terminal 4. The die pad 3 is covered with the resin member 5 over half of the front surface 3A and with half of the back surface 3B exposed to the back surface of the circuit member 1. The terminals 4 have inner terminals 4A on the front surface and outer terminals 4B integrally on the back surface, and each inner terminal 4A is exposed so as to form a recess between the resin members 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device having a semiconductor element mounted thereon, a circuit member used therein, and a method of manufacturing the resin-sealed semiconductor device.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been typified by LSI ASICs due to advances in high integration and miniaturization technologies, and the trend toward higher performance and lighter, thinner and smaller electric appliances (current trend).
Higher integration and higher functionality are being increasingly achieved. In such a highly integrated and highly functional semiconductor device,
In order to perform high-speed signal processing, heat generation of the chip and
The inductance in the package cannot be ignored. For this reason, thermal vias are provided to allow the heat of the chip to escape to the outside of the package, and the number of power and ground connection terminals is increased to lower the substantial inductance.
This is addressed by reducing the inductance in the package. As described above, as the degree of integration and function of a semiconductor device increases, the total number of external terminals (pins) increases, and more terminals (pins) are required.

[0003] In response to the demand for the multi-terminal (pin) as described above, a multi-terminal (pin) IC, particularly an ASIC represented in a gate array or a standard cell, or a DSP (Digital Signal Proc).
In some cases, a lead frame is used in the manufacture of a semiconductor device such as an e.s. Specifically, QFP (Qua
d Flat Package) and the like, and the QFP has been put into practical use to a 300-pin class.

However, in recent years, higher speed and higher performance (function) of signal processing of a semiconductor element require more terminals. In the QFP, it is possible to cope with further increase in the number of terminals by reducing the pitch of the external terminals. However, when the pitch of the external terminals is reduced, it is necessary to reduce the width of the external terminals themselves. Become. as a result,
A problem occurs in the positional accuracy or flatness accuracy of the terminal formation (gull wing formation). Further, in the QFP, as the pitch of the external terminals is further narrowed to 0.3 to 0.4 mm, the mounting process becomes difficult, and obstacles (problems) such as necessity of realizing advanced board mounting technology occur. I have.

[0005] In addition, due to the demand for miniaturization and thinning of a sealed type semiconductor device using a lead frame, the trend of the development is QFP and SOJ (Small Outl).
TSOP (Thin) through a surface mount type package such as an ine J-Leaded Package).
The development of Small Outline Packages has led to the development of smaller packages with the main axis being thinner, and the LOC (Lead On Chip) structure for the purpose of improving chip storage efficiency by making the package three-dimensional.

[0006]

However, even in the above-mentioned conventional package, there is a limit to miniaturization of the package due to the routing of leads on the outer peripheral portion of the semiconductor element. Further, in a small package such as TSOP, there is a limit to the number of pins in terms of lead routing and pin pitch.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a high occupancy rate of a semiconductor element, can be reduced in size, and can improve a mounting density on a circuit board.
It is still another object of the present invention to provide a resin-encapsulated semiconductor device capable of coping with an increase in the number of pins and a reduction in thickness, a circuit member used therefor, and a method of manufacturing the same.

[0008]

In order to achieve the above object, a circuit member for a resin-encapsulated semiconductor device according to the present invention is provided with an outer frame member and independently disposed inside the outer frame member. Provided die pad, and a plurality of terminal portions independently disposed on substantially one plane inside the outer frame member, having an internal terminal on the front side and an external terminal on the back side integrally on the back side. And an electrically insulating resin member interposed between the outer frame member and the die pad and each terminal portion.

The circuit member according to the present invention may be configured such that an internal terminal surface of the terminal portion is exposed so as to form a concave portion between the resin members, or an external terminal surface of the terminal portion may be such that It was configured to be exposed so as to form a concave portion between the resin members.

Further, the circuit member of the present invention is configured such that the die pad is thinner than the outer frame member.

Further, in the circuit member according to the present invention, the external terminal surface of the terminal portion may be provided with an external electrode member made of solder, or the external terminal surface of the terminal portion may be provided with a noble metal plating layer. And

In the resin-encapsulated semiconductor device of the present invention, a semiconductor element is electrically insulated and mounted on the surface side of the die pad of the circuit member, and the terminals of the semiconductor element and the terminal of the circuit member are formed. A structure in which the outer frame member of the circuit member is removed in a state where the internal terminals are electrically connected by wires and at least a part of the external terminals of each terminal portion is resin-sealed so as to be exposed to the outside. And

The method of manufacturing a circuit member for a resin-encapsulated semiconductor device according to the present invention comprises the steps of: (A) etching the surface of a conductive substrate to integrally form internal terminals on the front side and external terminals on the back side; A first step of preparing an externally processed member including a plurality of terminal portions, a die pad, and an outer frame member located outside the terminal portion and the die pad in a state of being connected on the back surface side; A) a second step of providing an electrically insulating resin layer on the etched surface of the externally processed member; and (C) removing the resin layer so as to expose the internal terminal surfaces of the respective terminal portions; A third step of etching the back surface of the outer shape processing member to electrically insulate the outer frame member, each terminal portion, and the die pad from each other.

Further, the method of manufacturing a circuit member for a resin-encapsulated semiconductor device according to the present invention comprises the steps of: (A) etching the back surface of the conductive substrate to integrate the internal terminals on the front surface and the external terminals on the back surface; A plurality of terminal portions, a die pad, and an outer frame member positioned outside the terminal portion and the die pad, a first step of creating an outer shape processing member provided in a state of being connected on the surface side, (B) a second step of providing an electrically insulating resin layer on the etched back side of the externally processed member; and (C) removing the resin layer so as to expose the external terminal surfaces of the respective terminal portions. And a third step of etching the surface of the outer shape processing member to electrically separate the outer frame member, each terminal portion, and the die pad from each other.

Further, the method of manufacturing a circuit member for a resin-encapsulated semiconductor device according to the present invention has a structure including a step of forming a noble metal plating layer on an internal terminal surface, and an external electrode member made of solder on an external terminal surface. Was formed.

According to the present invention, the circuit member does not lead the lead, and the resin-encapsulated semiconductor device can be miniaturized. The semiconductor device of the BGA (Ball Grid Array) type can be realized by forming an external electrode on an external terminal together with an operation of imparting strength to a circuit member together with an operation of electrically holding the semiconductor device electrically independent of the outer frame member. It becomes possible to improve handling and short-circuit prevention.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

Circuit Member FIG. 1 is a plan view showing an embodiment of the circuit member of the present invention, and FIG. 2 is a longitudinal sectional view taken along line AA of the circuit member shown in FIG. In FIGS. 1 and 2, the number of terminals is reduced and simplified for ease of explanation.

Referring to FIGS. 1 and 2, a circuit member 1 of the present invention comprises an outer frame member 2, a die pad 3 independently disposed inside the outer frame member, and a substantially inner portion of the outer frame member 2. It comprises a plurality of terminal portions 4 arranged independently on one plane, and an electrically insulating resin member 5 interposed between the outer frame member 2, the die pad 3 and each terminal portion 4. is there.

Although the outer frame member 2 has a rectangular outer shape and an inner opening shape in the illustrated example, the outer frame member 2 is a continuous body having a band-like outer shape, and rectangular inner openings are provided at predetermined intervals. Is also good.

The die pad 3 is located substantially at the center of the inner opening of the outer frame member 2, and the half of the front surface 3 A is covered with the resin member 5, and the half of the back surface 3 B is exposed to the back surface of the circuit member 1. I have.

The terminal portion 4 has an internal terminal 4A on the front surface side and an external terminal 4B on the back surface integrally on the front and back sides. In the illustrated example, the terminal portions 4 are arranged so as to surround the die pad 3.
Also, the surface of each internal terminal 4A is exposed so as to form a concave portion between the resin members 5, and such an internal terminal 4A
The surface and the surface of each external terminal 4B are located on the same plane.

The material of the circuit member 1 can be 42 alloy (Fe alloy of 41% Ni), copper, copper alloy or the like.

The resin member 5 can be made of an electrically insulating resin such as a polyimide resin or an epoxy solder resist. The thickness of the resin member 5 is 20 to 10
About 0 μm is preferable.

The circuit member 1 of the present invention may be one in which an electrically insulating double-sided adhesive tape is provided on a resin member 5 covering the surface 3A of the die pad 3. As a double-sided adhesive tape to be used, an electrically insulating base film provided with an adhesive layer on both sides thereof, for example, RX on both sides of Upilex (an electrically insulating base film manufactured by Ube Industries, Ltd.)
UXIW with F (adhesive manufactured by Tomoegawa Paper Mill) layer
(Manufactured by Hamakawa Paper Mills).

Further, as shown in FIG. 3, the circuit member 1 of the present invention may include an external electrode member 7 made of solder on the surface of the external terminal 4B of the terminal portion 4.

Further, as shown in FIG. 4, the circuit member 1 of the present invention may have a thin shape in which the thickness of the die pad 3 is thinner than the thickness of the outer frame member 2. Only the 3B side is exposed on the back side of the circuit member 1. Further, the circuit member 1 of the present invention may include a noble metal plating layer 8 on the surface of the external terminal 4B of the terminal portion 4, as shown in FIG.

It should be noted that the number of terminals, terminal arrangement, and the like in the above-described circuit member 1 are merely examples, and it is a matter of course that the present invention is not limited to this.

Circuit Member FIG. 5 is a plan view showing another embodiment of the circuit member of the present invention, and FIG. 6 is a longitudinal sectional view of the circuit member shown in FIG. In FIGS. 5 and 6, the number of terminals is reduced and simplified for ease of explanation.

5 and 6, a circuit member 11 of the present invention includes an outer frame member 12, a die pad 13 independently disposed inside the outer frame member, and a substantially inner portion of the outer frame member 12. A plurality of terminal portions 14 arranged independently on one plane, an outer frame member 12, a die pad 13 and each terminal portion 14;
And an electrically insulating resin member 15 interposed therebetween.

The outer frame member 12 has a rectangular outer shape and an inner opening shape in the illustrated example. However, the outer frame member 12 is a continuous body having a belt-like outer shape, and rectangular inner openings are provided at predetermined intervals. Is also good.

The die pad 13 is located substantially at the center of the inner opening of the outer frame member 12, and the half on the back surface 13 B side is made of the resin member 1.
5 and the half of the surface 13 </ b> B is exposed on the surface side of the circuit member 11.

The terminal portion 14 has an internal terminal 14A on the front surface side and an external terminal 14B on the back surface integrally on the front and back sides. In the illustrated example, the terminal portions 14 are arranged so as to surround the die pad 13. The surface of each external terminal 14B is
5, the inner terminals 14A and the outer terminals 14B are located on the same plane.

The material of the circuit member 11 and the material of the resin member 15 can be the same as those of the circuit member 1 and the resin member 5 described above. Further, the thickness of the resin member 15 is preferably about 20 to 100 μm.

The circuit member 11 of the present invention may be one in which an electrically insulating double-sided adhesive tape is provided on the surface 13A of the die pad 13. The double-sided adhesive tape to be used is the same as in the case of the circuit member 1 described above.

Further, as shown in FIG. 7, the circuit member 11 of the present invention may include an external electrode member 17 made of solder on the surface of the external terminal 14B of the terminal portion 14.

Further, as shown in FIG. 8, the circuit member 11 of the present invention has a die pad 13 having a thickness equal to that of the outer frame member 12.
May be thinner than the thickness of the circuit member 11, and only the surface 13A side is exposed to the surface side of the circuit member 11 in the illustrated example. Further, the circuit member 11 of the present invention has
As shown in (1), a noble metal plating layer 18 may be provided on the surface of the external terminal 14B of the terminal portion 14. Note that the number of terminals, the terminal arrangement, and the like in the above-described circuit member 1 are merely examples, and it is a matter of course that the present invention is not limited to this.

Production of circuit members for resin-encapsulated semiconductor devices
Method Next, a method for manufacturing a circuit member according to the present invention will be described.

FIGS. 9 and 10 are process diagrams showing one embodiment of a method for manufacturing a circuit member of the present invention using the circuit member 1 shown in FIGS. 1 and 2 as an example. Each step is shown in a longitudinal sectional view of the resin-sealed semiconductor device corresponding to FIG. 2 described above.

First, as a first step, the conductive substrate 21
A photosensitive resist is applied on the front and back surfaces of the photosensitive resist layer and dried to form a photosensitive resist layer 31 (FIG. 9A), which is exposed through a desired photomask, and then developed to form resist patterns 31A and 31B. It is formed (FIG. 9B). As described above, the conductive substrate 21 is made of a 42 alloy (Ni 41% F
e alloy), copper, copper alloy or other metal substrate (thickness 100 to 25)
0 μm) can be used.
It is preferable to use a material which has been subjected to a cleaning treatment after degreasing both surfaces. Further, as the photosensitive resist, conventionally known ones, for example, OFPR manufactured by Tokyo Ohka Kogyo Co., Ltd.
1305 etc. can be used.

Next, the back surface of the conductive substrate 21 on which the resist pattern 31B is formed is covered with an etching-resistant film 32, and the resist pattern 31A is used as a corrosion-resistant film from the front side of the conductive substrate 21 with a corrosion liquid. Etching is performed (FIG. 9C). The etching solution is usually an aqueous solution of ferric chloride, and is spray-etched on the surface of the conductive substrate 21. The amount of etching in this etching step is adjusted so as not to penetrate the conductive substrate 21 in the thickness direction. Thereby, the die pad 23 and the internal terminal 2
An outer shape processing member 21 'having a plurality of terminal portions 24 having 4A on the front surface and outer frame members 22 located outside thereof in a state of being connected on the back surface side is obtained.

Next, as a second step, after removing and removing the resist pattern 31A, the outer shape processing member 21 'is formed.
Outer frame member 2 on the surface (the surface that has been subjected to the etching process)
An electrically insulating resin layer 25 is formed in a region excluding the region 2 (FIG. 9D). As the electrically insulating resin, a conventionally known resin can be used, and examples thereof include a thermosetting polyimide paste 330 (Upitite UPA series manufactured by Ube Industries, Ltd.). The resin layer 25 can be formed by, for example, applying a screen printing method and performing a curing process as needed, and has a thickness of 10 to 100.
It is preferable that the thickness be about μm.

Next, as a third step, each terminal 24
Of the resin layer 25 so as to expose the internal terminals 24A.
Is removed to form an opening 25a (FIG. 10A).
The removal of the resin layer 25 can be performed by, for example, laser irradiation. The size of the opening 25a to be formed is
It can be set appropriately according to the terminal portion 24 already formed. Next, the outer shape processing member 2 is covered so as to cover the resin layer 25.
1 'is covered with a film 33 having etching resistance, and the film 32 on the back is removed (FIG. 10).
(B)). Next, the resist pattern 31B is etched with a corrosion liquid from the back surface side of the conductive substrate 21 as a corrosion resistant film. The etching liquid is similar to the above-described etching, and is performed by spray etching on the back surface of the outer shape processing member 21 '. The amount of etching in this etching step depends on the resin layer 25 (the outer frame member 2) in the thickness direction of the conductive substrate 21.
2 is adjusted to such an extent that the resin layer interposed between the die pad 23 and each terminal portion 24 is exposed. Thereafter, the resist pattern 31B is peeled off and removed, and the above-mentioned film 33 is also removed, whereby the circuit member 1 of the present invention is obtained (FIG. 10C). The gold plating layer 6 can be formed on the internal terminals 4A and the external terminals 4B of the terminal portion 4 of the obtained circuit member 1 (FIG. 10D). In addition, external terminal 4B
By forming the external electrode member 7 made of solder on
The circuit member 1 shown in FIG. 3 is obtained.

The die pad 3 as shown in FIG.
The circuit member whose thickness is thinner than the thickness of the outer frame member 2 is also changed by changing the pattern shape of the resist pattern 31B formed on the back surface (no resist pattern is provided at the position corresponding to the formation position of the die pad). It can be manufactured in the same manner as described above.

Production of circuit members for resin-encapsulated semiconductor devices
Method FIGS. 11 and 12 are process diagrams showing another embodiment of the method for manufacturing a circuit member of the present invention using the circuit member 11 shown in FIGS. 5 and 6 as an example. Each step is shown in a vertical sectional view of the resin-sealed semiconductor device corresponding to FIG.

First, as a first step, the conductive substrate 41
The photosensitive resist layer 51 is formed by applying a photosensitive resist on the front and back surfaces of the resist pattern and drying it (FIG. 11A), exposing it through a desired photomask, and developing it to form the resist patterns 51A and 51B. It is formed (FIG. 11B). The conductive substrate 41 and the photosensitive resist used can be the same as those in the above-described manufacturing method.

Next, the surface of the conductive substrate 41 on which the resist pattern 51A is formed is covered with an etching-resistant film 52, and the resist pattern 51B is used as a corrosion-resistant film from the back side of the conductive substrate 41 with a corrosion liquid. Etching is performed (FIG. 11C). The etchant used and the etching method can be the same as those described above. The amount of etching in this etching step depends on the conductive substrate 4
1 is adjusted so as not to penetrate in the thickness direction. Thereby, the die pad 43, the plurality of terminal portions 44 having the external terminals 44B on the back surface, and the outer frame member 4 located outside these are provided.
2 with the outer shape processing member 2 connected to the front side
1 'is obtained.

Next, as a second step, after removing and removing the resist pattern 51B, the outer shape processing member 41 'is formed.
Outer frame member 4 on the back surface (the surface that has been etched) of
An electrically insulating resin layer 45 is formed in a region excluding the region 2 (FIG. 11D). The electrically insulating resin used, the method of forming the resin layer 25, the thickness, and the like can be the same as those in the above-described manufacturing method.

Next, as a third step, each terminal 44
Resin layer 45 so as to expose the external terminals 44B.
Is removed to form an opening 45a (FIG. 12A).
The removal of the resin layer 45 can be performed by, for example, laser irradiation, and the size of the opening 45a to be formed can be appropriately set according to the terminal 44 already formed. Next, the outer shape processing member 41 ′ is covered so as to cover the resin layer 45.
Is covered with a film 53 having etching resistance,
Further, the film 52 existing on the surface is removed (FIG. 12).
(B)). Next, etching is performed from the surface side of the conductive substrate 41 with a corrosion liquid using the resist pattern 51A as a corrosion resistant film. The etching liquid is similar to the above-described etching, and is performed by spray etching on the back surface of the outer shape processing member 41 '. The amount of etching in this etching step depends on the resin layer 45 (outer frame member 4) in the thickness direction of the conductive substrate 41.
2 is adjusted to such an extent that the resin layer interposed between the die pad 43 and each terminal portion 44 is exposed. Thereafter, the resist pattern 51A is peeled off and removed, and the film 53 is also removed, whereby the circuit member 11 of the present invention is obtained (FIG. 12C). The inner terminal 14A and the outer terminal 14B of the terminal portion 14 of the obtained circuit member 11 are provided with the gold plating layer 1.
6 can also be formed (FIG. 12D). Also, by forming the external electrode member 17 made of solder on the external terminal 14B, the circuit member 11 shown in FIG. 7 is obtained.

Further, as shown in FIG. 8, the thickness of the die pad 13 is thinner than that of the outer frame member 12, and the circuit member having a thin wall shape also changes the pattern shape of the resist pattern 51A formed on the surface (die pad). (A resist pattern is not provided at a position corresponding to the formation position of (1)), thereby making it possible to manufacture in the same manner as described above.

Next, a resin-sealed semiconductor device of the present invention will be described with reference to a method of manufacturing the same.

A resin-sealed semiconductor device using the circuit member 1 of the present invention shown in FIGS. 1 and 2 will be described with reference to FIG.

First, the die pad 3 of the circuit member 1 of the present invention
The semiconductor element 65 is mounted on the surface side of the substrate using an adhesive 66 (FIG. 13A). In this case, the semiconductor element 65 is mounted on the die pad 3 via the resin member 5.

Next, the terminal 6 of the mounted semiconductor element 65
5a and the internal terminals 4A of the terminal portions 4 of the circuit member 1 are electrically connected by wires 67 (FIG. 13B).

Next, the external terminal 4B and the back surface 3B of the die pad are exposed to the outside so that the die pad 3
Terminal part 4, resin member 5, semiconductor element 65 and wire 6
7 is sealed with a sealing member 68 (FIG. 13C).

Next, the outer frame member 2 of the circuit member 1 is removed to obtain a semiconductor device 61 of the present invention (FIG. 13D).
Further, external electrodes 69 made of solder can be formed on the external terminals 4B exposed to the outside (FIG. 13).
(E)). Thereby, BGA (Ball Grid)
(Array) type semiconductor device.

Even when the circuit members shown in FIGS. 3 and 4 are used, the resin-sealed semiconductor device of the present invention can be manufactured in the same manner as described above. Note that the number of terminals, terminal arrangement, and the like in the above-described resin-sealed semiconductor device 1 are merely examples, and the present invention is not limited thereto.

Resin-sealed semiconductor device Next, the circuit member 11 of the present invention shown in FIGS.
Will be described with reference to FIG.

First, a semiconductor element 75 is mounted on the die pad 13 of the circuit member 11 of the present invention using an electrically insulating double-sided adhesive tape 76 (FIG. 14A).

Next, the terminal 7 of the mounted semiconductor element 75 is
5a and the internal terminal 14A of the terminal portion 14 of the circuit member 11 are electrically connected by a wire 77 (FIG. 14B).

Next, the die pad 1 is exposed so that the external terminals 14B and the back surface 15B of the resin member 15 are exposed to the outside.
3. The terminal portion 14, the resin member 15, the semiconductor element 75, and the wire 77 are sealed with a sealing member 78 (FIG. 14).
(C)).

Next, the outer frame member 12 of the circuit member 11 is removed to obtain a semiconductor device 71 of the present invention (FIG. 14).
(D)). Further, an external electrode 79 made of solder can be formed on the external terminal 14B exposed to the outside (FIG. 14E). Thereby, BGA (Ball Gri)
d Array) type semiconductor device.

Even if the circuit members shown in FIGS. 7 and 8 are used, the resin-sealed semiconductor device of the present invention can be manufactured in the same manner as described above. Note that the number of terminals, terminal arrangement, and the like in the above-described resin-sealed semiconductor device 1 are merely examples, and the present invention is not limited thereto.

[0064]

Next, the present invention will be described in more detail with reference to specific examples.

Preparation of Circuit Member A copper alloy plate (EFTEC64T-1 / 2H manufactured by Furukawa Electric Co., Ltd.) having a thickness of 0.125 mm was prepared as a conductive substrate, degreased and cleaned, and then this copper alloy UV curable resist on both sides of the plate (OF of Tokyo Ohka Kogyo Co., Ltd.)
PR1305) was applied by a pouring method and dried.
Next, the resist layers on the front side and the back side were respectively exposed through a predetermined photomask, and then developed to form a resist pattern. Next, the back surface was covered with an etching-resistant film (Hitalex manufactured by Hitachi Chemical Co., Ltd.), and then spray etching was performed on both surfaces of the copper alloy plate using an aqueous ferric chloride solution. This etching was performed so as not to penetrate in the thickness direction of the copper alloy plate. Next, after washing, the resist pattern on the surface side was peeled off using an organic alkali solution. As a result, there was obtained an externally processed member provided with the die pad, the plurality of terminal portions having the internal terminals on the front surface, and the outer frame member located outside of the die pads connected on the back surface side.

Next, a thermosetting polyimide paste 33 was applied to the above-mentioned outer shape processing member except for the outer frame member on the surface side.
No. 0 (manufactured by Ube Industries, Ltd.) was applied by screen printing (thickness: 50 μm) and thermally cured to form a resin layer.

Next, a portion of the resin layer corresponding to the internal terminal of each terminal portion was irradiated with a laser to form an opening having a diameter of 0.25 mm, thereby exposing the internal terminal.

Next, the same etching resistant film as described above was overlaid on the surface of the externally processed member so as to cover the resin layer, and the etching resistant film covering the back side was peeled off. Thereafter, etching was performed from the back side of the copper alloy plate using the resist pattern on the back side as a corrosion resistant film. Next, after washing, the resist pattern on the back side was peeled off and removed using an organic alkali solution, and the etching resistant film on the front side was peeled off to obtain a circuit member of the present invention. Further, a gold plating layer (about 5 μm in thickness) was formed on the internal terminal surface and the external terminal surface of this circuit member.

Fabrication of Resin-Encapsulated Semiconductor Device On a resin member (polyimide resin) covering the die pad of the circuit member of the present invention produced as described above, a die attach agent (Able Bond 839 manufactured by Able Stick Co., Ltd.)
0), the other side of the circuit forming surface of the semiconductor element (about 0.25 mm thick) was mounted by crimping.

Next, the gold plating layer on the internal terminal of the circuit member and the terminal of the mounted semiconductor element were connected by a gold wire (FA-30 manufactured by Tanaka Electronics Industry Co., Ltd.). Thereafter, the terminal portion, the die pad, the semiconductor element, and the gold wire were sealed with a resin material (MP-7400 manufactured by Nitto Denko Corporation) so that the external terminal surface was exposed to the outside.

Next, the outer frame member of the circuit member was removed by pressing, and a ball (0.3 mm in diameter) made of solder was fixed to an external terminal exposed outside to form an external electrode.

The resin-encapsulated semiconductor device manufactured in this manner has 60 external electrodes and an external dimension of 5 pins.
A very small resin-encapsulated semiconductor device that is as small as mm square was realized.

[0073]

As described above in detail, according to the present invention, since the circuit member does not have lead routing, the occupancy of the semiconductor element is increased, the size is reduced, and the mounting density on the circuit board is improved. Since the circuit member is reinforced by the resin member provided on the circuit member,
Deformation of circuit members due to miniaturization is prevented, and furthermore, by forming external electrodes on external terminals, BGA (Bal
l Grid Array) type semiconductor device becomes possible.
The short-circuit prevention property is improved, and furthermore, it is possible to cope with the increase in the number of pins, and the circuit member of the present invention can be easily manufactured by the manufacturing method of the present invention.

[Brief description of the drawings]

FIG. 1 is a plan view showing one embodiment of a circuit member of the present invention.

FIG. 2 is a longitudinal sectional view of the circuit member shown in FIG. 1 taken along line AA.

FIG. 3 is a longitudinal sectional view showing another embodiment of the circuit member of the present invention.

FIG. 4 is a longitudinal sectional view showing another embodiment of the circuit member of the present invention.

FIG. 5 is a plan view showing another embodiment of the circuit member of the present invention.

6 is a vertical sectional view of the circuit member shown in FIG. 5, taken along line BB.

FIG. 7 is a longitudinal sectional view showing another embodiment of the circuit member of the present invention.

FIG. 8 is a longitudinal sectional view showing another embodiment of the circuit member of the present invention.

FIG. 9 is a process chart showing one embodiment of a method for manufacturing a circuit member of the present invention.

FIG. 10 is a process chart showing one embodiment of a method for manufacturing a circuit member of the present invention.

FIG. 11 is a process chart showing another embodiment of the method for manufacturing a circuit member of the present invention.

FIG. 12 is a process chart showing another embodiment of the method for producing a circuit member of the present invention.

FIG. 13 is a manufacturing process diagram for describing one embodiment of a resin-sealed semiconductor device of the present invention.

FIG. 14 is a manufacturing process diagram for explaining another embodiment of the resin-sealed semiconductor device of the present invention.

[Explanation of symbols]

 1,11 ... Circuit member 2,12 ... Outer frame member 3,13 ... Die pad 4,14 ... Terminal part 4A, 14A ... Internal terminal 4B, 14B ... External terminal 5,15 ... Resin member 24A ... Internal terminal 44B ... External terminal 21, 41 ... conductive substrate 21 ', 41' ... outer shape processing member 25, 45 ... resin layer 61, 71 ... resin-sealed semiconductor device 65, 75 ... semiconductor element 65a, 75a ... terminal 67, 77 ... wire 68, 78: sealing member 69, 79: external electrode

Claims (11)

[Claims] 1. A circuit member for a resin-encapsulated semiconductor device, comprising: an outer frame member, a die pad independently disposed inside the outer frame member, an internal terminal on a front side, and an external terminal on a back side. A plurality of terminal portions which are integrally provided on the front and back sides and are arranged independently on a substantially flat surface inside the outer frame member, and interposed between the outer frame member, the die pad, and each terminal portion. A circuit member comprising: an electrically insulating resin member; 2. The circuit member according to claim 1, wherein an internal terminal surface of the terminal portion is exposed so as to form a concave portion between the resin members. 3. The circuit member according to claim 1, wherein the external terminal surface of the terminal portion is exposed so as to form a concave portion between the resin members. 4. The circuit member according to claim 1, wherein the die pad is thinner than the outer frame member. 5. The circuit member according to claim 1, wherein the external terminal surface of the terminal portion includes an external electrode member made of solder. 6. The circuit member according to claim 1, wherein an external terminal surface of the terminal portion includes a noble metal plating layer. 7. A semiconductor element is electrically insulated and mounted on the surface side of the die pad of the circuit member according to claim 1, and a terminal of the semiconductor element and a terminal part of the circuit member are provided. The inner terminal is electrically connected to the internal terminal by a wire, and the outer frame member of the circuit member is removed in a state where the whole is resin-sealed so that at least a part of the external terminal of each terminal portion is exposed to the outside. Resin-encapsulated semiconductor device. 8. A method of manufacturing a circuit member for a resin-encapsulated semiconductor device, comprising: (A) etching the surface of a conductive substrate to integrally have internal terminals on the front side and external terminals on the back side; (B) a first step of preparing an externally processed member including a plurality of terminal portions, a die pad, and an outer frame member located outside the terminal portion and the die pad, connected on a back surface side; A second step of providing an electrically insulating resin layer on the etched surface of the outer shape processing member; and (C) removing the resin layer so as to expose the internal terminal surfaces of the respective terminal portions; A third step of etching the back surface of the outer shape processing member to electrically separate the outer frame member, each terminal portion, and the die pad from each other. 9. A method of manufacturing a circuit member for a resin-encapsulated semiconductor device, comprising: (A) etching a back surface of a conductive substrate to integrally have internal terminals on a front surface side and external terminals on a back surface side; (B) a first step of preparing an externally processed member including a plurality of terminal portions, a die pad, and an outer frame member located outside the terminal portion and the die pad, connected to each other on a front surface side; A second step of providing an electrically insulating resin layer on the etched back surface side of the outer shape processing member; and (C) removing the resin layer so as to expose an external terminal surface of each terminal portion; A third step of etching the surface of the outer shape processing member to electrically isolate the outer frame member, each terminal portion, and the die pad from each other. 10. The method according to claim 8, further comprising the step of forming a noble metal plating layer on the internal terminal surface. 11. The method according to claim 8, further comprising the step of forming an external electrode member made of solder on the external terminal surface.