JP2000332143A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2000332143A JP2000332143A JP14001799A JP14001799A JP2000332143A JP 2000332143 A JP2000332143 A JP 2000332143A JP 14001799 A JP14001799 A JP 14001799A JP 14001799 A JP14001799 A JP 14001799A JP 2000332143 A JP2000332143 A JP 2000332143A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- bump
- surface side
- stress concentration
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000011347 resin Substances 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 10
- 238000007789 sealing Methods 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 19
- 229910052802 copper Inorganic materials 0.000 description 18
- 239000010949 copper Substances 0.000 description 18
- 230000035882 stress Effects 0.000 description 14
- 238000000034 method Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 238000012790 confirmation Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に関
し、特に基板接続面に外部接続端子としてのバンプを備
えると共に、集積回路チップを樹脂で封止した半導体装
置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a substrate connection surface provided with bumps as external connection terminals and sealing an integrated circuit chip with a resin.
【０００２】[0002]
【従来の技術】近年、半導体装置及びそれを実装する多
層プリント基板配線板においては、小型薄型化、高性能
化、高速化、高信頼性化が求められている。例えば、半
導体装置は小型薄型化の要求から「ピン挿入型のパッケ
ージ」から「表面実装型のパッケージ」ヘと移行し、半
導体素子をプリント基板へ直接実装するような「ベアチ
ップ実装」と呼ばれる実装方法も研究されている。ま
た、前記実装密度向上のための手法としては、ＣＯＢ
（Chip On Board ）、ＦＣ（Flip Chip）、ＴＣＰ（Ta
pe Carrier Package）などが知られている。2. Description of the Related Art In recent years, a semiconductor device and a multilayer printed circuit board on which the semiconductor device is mounted have been required to be small, thin, high-performance, high-speed, and highly reliable. For example, semiconductor devices have shifted from “pin-insertion-type packages” to “surface-mount-type packages” due to the demand for smaller and thinner devices, and a mounting method called “bare chip mounting” that directly mounts semiconductor elements on a printed circuit board. Has also been studied. As a method for improving the mounting density, COB is used.
(Chip On Board), FC (Flip Chip), TCP (Ta
pe Carrier Package) is known.
【０００３】樹脂封止型半導体装置では薄型化が進ん
で、約１ｍｍの厚さを有するＴＳＯＰ（Thin Small Out
line Package）やＴＱＦＰ（Thin Small Quad Flat Pac
kage）等の薄型パッケージが開発されている。[0003] Thinning of resin-encapsulated semiconductor devices has progressed, and TSOP (Thin Small Out) having a thickness of about 1 mm has been developed.
line Package) and TQFP (Thin Small Quad Flat Pac)
kage) and other thin packages have been developed.
【０００４】更に近年、小型化、薄型化した半導体装置
として、例えば半田バンプを使用したＣＳＰ（チップ・
サイズ・パッケージ）型の半導体装置が登場してきた。[0004] In recent years, as a semiconductor device that has been reduced in size and thickness, for example, a CSP (chip / chip) using solder bumps has been used.
(Size / package) type semiconductor devices have appeared.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、ＣＳＰ
型の半導体装置では前述の薄型化により曲げに対しての
強度が弱くなるため、実装後の温度サイクル試験時に、
シリコンチップと封止樹脂との熱膨張係数の差によって
発生する熱応力により、反ってしまうという問題が発生
している。この「反り」は、特に半導体素子において、
搭載するプリント配線基板の接続部である半田バンプに
応力が集中する原因となり、半田バンプが破壊して導通
不良となるなどの問題を引き起こしている。However, the CSP
In the semiconductor device of the type, since the strength against bending is weakened by the above-mentioned thinning, during a temperature cycle test after mounting,
There is a problem that the silicon chip and the sealing resin are warped by a thermal stress generated due to a difference in thermal expansion coefficient between the silicon chip and the sealing resin. This “warpage” is particularly observed in semiconductor devices.
This causes stress to concentrate on the solder bumps, which are the connection portions of the printed wiring board to be mounted, and causes problems such as breakage of the solder bumps and poor conduction.
【０００６】現在、一般的な反り対策としてシリコンチ
ップと封止樹脂との熱膨張係数の差を小さくすることに
より、対処しようとしているが、シリコンチップも封止
樹脂も素材が異なるため、現実には完全に無くすことが
できなかった。そして、特にエポキシ系樹脂を内部絶縁
基板として使用する半導体装置では、その応力が大きく
薄型化が困難で、薄型化には高価ではあるがガラス転移
点がよりエポキシ系樹脂よりも高く、高温域でも線膨張
係数が変化せず、応力が比較的少ないポリイミドテープ
を使用しなければならなかった。At present, as a general countermeasure against warpage, it is attempted to reduce the difference in thermal expansion coefficient between the silicon chip and the sealing resin. However, since the silicon chip and the sealing resin are made of different materials, they are actually used. Could not be completely eliminated. In particular, in a semiconductor device using an epoxy resin as an internal insulating substrate, the stress is large and it is difficult to reduce the thickness, and the glass transition point is higher than that of the epoxy resin, although it is expensive to reduce the thickness. It was necessary to use a polyimide tape whose coefficient of linear expansion did not change and which had relatively low stress.
【０００７】そこで本発明の課題は、バンプによる応力
集中を、安価な手段を用いて無くすようにした基板接続
面にバンプを備えた半導体装置を提供することである。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having bumps on a substrate connecting surface, which is capable of eliminating stress concentration due to bumps by using inexpensive means.
【０００８】[0008]
【課題を解決するための手段】前記課題を解決するため
に本発明は、絶縁基板の一面側と他面側とをスルーホー
ルで導通接続し、一面側のスルーホール開口部にバンプ
を取付け、他面側に集積回路チップを接着してなる半導
体装置において、前記一面側のスルーホール開口部に、
前記バンプによる応力集中を緩和する応力集中緩和手段
を設けたことを特徴とする。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a method for electrically connecting one side of an insulating substrate to the other side through a through hole, and mounting a bump in a through hole opening on one side. In a semiconductor device in which an integrated circuit chip is adhered to the other surface, in the through hole opening on the one surface,
A stress concentration relieving means for relieving stress concentration due to the bump is provided.
【０００９】このようにすれば、応力集中緩和手段（例
えば、テーパー手段）によりバンプによる応力集中が緩
和されるので、高価なポリイミドテープを使用しないで
も、内部絶縁基板の反りに伴なっていたバンプ破壊を防
止した、半導体装置を実現することができる。In this case, since the stress concentration due to the bump is reduced by the stress concentration reducing means (for example, a taper means), the bump caused by the warpage of the internal insulating substrate can be used without using an expensive polyimide tape. A semiconductor device in which destruction is prevented can be realized.
【００１０】[0010]
【発明の実施の形態】以下、本発明を図示の実施の形態
に基づいて説明する。図１及び図２に、本実施の形態の
ＣＳＰ型パッケージの半導体装置１を示す。半導体装置
１は大型の絶縁基板５（以下、絶縁基板と記す）を有
し、１２ｍｍ角、厚さ０．０７５ｍｍのエポキシ製のフ
ィルム片である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the illustrated embodiments. 1 and 2 show a CSP type semiconductor device 1 of the present embodiment. The semiconductor device 1 has a large-sized insulating substrate 5 (hereinafter, referred to as an insulating substrate), and is a 12 mm square, 0.075 mm thick film piece made of epoxy.
【００１１】図１、図２に示すように、絶縁基板５の表
面には集積回路（半導体）チップ２と外部接続端子であ
る半田バンプ１２とを電気的に接続するための多数の銅
パターンからなるワイヤ接続ランド４、バンプ接続ラン
ド６、及び銅配線８が形成されている。銅パターンから
なるバンプ接続ランド６は、絶縁基板５に形成されたス
ルーホール１３上に位置し、該スルーホール１３を介し
て半田バンプ１２と接続されている。本実施の形態にお
ける各銅パターンからなるバンプ接続ランド６は、上記
スルーホール１３の位置に対応して、絶縁基板５の各辺
に沿って連続的に配置されると共に、その並びの方向と
直交方向３列に並んで配置されている。As shown in FIGS. 1 and 2, a large number of copper patterns for electrically connecting the integrated circuit (semiconductor) chip 2 and the solder bumps 12 as external connection terminals are formed on the surface of the insulating substrate 5. The wire connection land 4, the bump connection land 6, and the copper wiring 8 are formed. The bump connection land 6 made of a copper pattern is located on the through hole 13 formed in the insulating substrate 5 and is connected to the solder bump 12 via the through hole 13. The bump connection lands 6 made of each copper pattern in the present embodiment are continuously arranged along each side of the insulating substrate 5 corresponding to the positions of the through holes 13 and orthogonal to the direction of the arrangement. They are arranged in three rows in the direction.
【００１２】また、銅パターンからなるワイヤ接続ラン
ド４には、集積回路チップ２の回路形成面側に形成した
電極パッド３から伸びる導体ワイヤ７の一端が接続され
ている。そして、これらワイヤ接続ランド４とバンプ接
続ランド６とは、銅パターンからなる銅配線８によって
接続されている。なお、本実施の形態において、銅配線
８の線幅は約０．０４ｍｍとし、バンプ接続ランド６の
線幅は約０．３ｍｍとし、ワイヤ接続ランド４の幅は約
０．１ｍｍとした。また、隣り合うバンプ接続ランド６
間のピッチは、約０．５ｍｍとした。Further, one end of a conductor wire 7 extending from the electrode pad 3 formed on the circuit forming surface side of the integrated circuit chip 2 is connected to the wire connection land 4 made of a copper pattern. The wire connection lands 4 and the bump connection lands 6 are connected by a copper wiring 8 made of a copper pattern. In the present embodiment, the line width of the copper wiring 8 is about 0.04 mm, the line width of the bump connection land 6 is about 0.3 mm, and the width of the wire connection land 4 is about 0.1 mm. In addition, adjacent bump connection lands 6
The pitch between them was about 0.5 mm.
【００１３】図２及びそのＡ部分拡大図の図３に示すよ
うに、上記銅パターンからなるワイヤ接続ランド４、バ
ンプ接続ランド６、及び銅配線８を形成した絶縁基板５
の表面には、その全域に渡って、エポキシ系樹脂からな
る半田マスク１１の塗布を行なうが、導体ワイヤ７のボ
ンディングのために、銅パターンからなるワイヤ接続ラ
ンド４上には半田マスクは塗布しない。As shown in FIG. 2 and FIG. 3 which is an enlarged view of a portion A of FIG. 2, an insulating substrate 5 on which a wire connection land 4, a bump connection land 6, and a copper wiring 8 formed of the copper pattern are formed.
Is applied to the entire surface of the wire, but the solder mask is not applied to the wire connection lands 4 made of a copper pattern for bonding the conductor wires 7. .
【００１４】本実施の形態における銅パターンからなる
ワイヤ接続ランド４、バンプ接続ランド６、及び銅配線
８は銅箔をラミネートした後に、その一部を、フォトリ
ソグラフィー技術を用いてエッチングすることにより得
られ、半田マスク１１の塗布されていないワイヤ接続ラ
ンド４上にはＡｕメッキを施した。集積回路チップ２
は、半田マスク１１の上に滴下された液状のエポキシ系
樹脂からなるダイペースト１０によって、絶縁基板５上
に接着される。これにより、上記すべての銅パターンか
らなるバンプ接続ランド６は、集積回路チップ２の下に
位置する。The wire connection lands 4, the bump connection lands 6, and the copper wirings 8 made of a copper pattern according to the present embodiment are obtained by laminating a copper foil and etching a part thereof by using a photolithography technique. Then, Au plating was applied to the wire connection lands 4 on which the solder mask 11 was not applied. Integrated circuit chip 2
Is bonded onto the insulating substrate 5 by a die paste 10 made of a liquid epoxy resin dropped on the solder mask 11. Thus, the bump connection lands 6 made of all the copper patterns are located below the integrated circuit chip 2.
【００１５】スルーホール１３内部には半田バンプ１２
の接続を容易にする為に銅メッキ１５が施されており、
その中にバンプ接続ランド６と半田バンプ１２の電気的
な抵抗を減少させる為、及び、製造時に硬化前のモール
ド樹脂等のスルーホール１３からの流出を防ぐ為に、導
電性樹脂１４が封入されている。本実施の形態でのスル
ーホール１３は打ち抜き部材による打ち抜き加工、又は
フォトリソグラフィー技術を用いて、下穴を空けてお
き、切削加工により形成することができ、半田バンプ１
２の取り付け側の端部を面取りすることにより、本発明
にかかるテーパー部分１６を設けることができる。本実
施の形態では面取りをＣ０．０３５ｍｍで行ない、その
上に厚み１μｍ程度の銅メッキ１５を行なっている。A solder bump 12 is provided inside the through hole 13.
Copper plating 15 is applied to facilitate connection of
A conductive resin 14 is sealed therein to reduce the electrical resistance between the bump connection lands 6 and the solder bumps 12 and to prevent the mold resin or the like before curing from flowing out of the through holes 13 during manufacturing. ing. The through-hole 13 in the present embodiment can be formed by punching with a punching member or by cutting a hole by using a photolithography technique, and cutting the solder bump 1.
By chamfering the end on the mounting side of 2, the tapered portion 16 according to the present invention can be provided. In the present embodiment, chamfering is performed at C of 0.035 mm, and copper plating 15 having a thickness of about 1 μm is performed thereon.
【００１６】以上のような構成の半導体装置に対し、半
田バンプにおいて、もっとも条件が厳しいといわれる、
それぞれを全く一致する表裏に配置する両面実装を行な
い、確認の為に−３５℃から＋１０５℃までの温度サイ
クル試験を行った。For the semiconductor device having the above-described structure, solder bumps are said to have the strictest conditions.
Each of them was mounted on both sides so as to completely coincide with each other, and a temperature cycle test from −35 ° C. to + 105 ° C. was performed for confirmation.
【００１７】その結果、従来の製法によるもの（スルー
ホール部分の面取り無し）は４００サイクル弱で半田バ
ンプの破壊が見られたが、本実施の形態に示す製法で製
造した半導体装置１（スルーホール開口部の面取り有
り）では７００サイクル以上で半田バンプ１２が破壊ま
で至っていないとの結果がでた。As a result, in the case of the conventional manufacturing method (without chamfering of the through-hole portion), the solder bump was broken in less than 400 cycles, but the semiconductor device 1 (through-hole) manufactured by the manufacturing method shown in this embodiment was used. In the case of (chamfering of the opening), the result was that the solder bump 12 did not break down after 700 cycles or more.
【００１８】更に確認として、上記半導体装置１をそれ
ぞれ８接点立体要素まで簡略化したモデルにて１００℃
温度変化時のシミュレーションを行なってみると、従来
の製法によるものに比較し、応力が分散しており、１
１．６ｍｍｋｇｆ／ｍｍ2 であった相当応力が、およそ
９．８ｋｇｆ／ｍｍ2 まで軽減されていることが確認さ
れた。As a further confirmation, the semiconductor device 1 was heated to 100 ° C. by using a simplified model of each of the three contact elements.
The simulation at the time of temperature change shows that the stress is more dispersed than that of the conventional manufacturing method,
1.6mmkgf / mm 2 and was the equivalent stress is, it was confirmed to be reduced to approximately 9.8kgf / mm 2.
【００１９】なお、図４に示すように、スルーホールの
半田パンプ１２の取付け側に、段部分（段差部分）１７
を形成しても、前記テーパー部分１６と同様に、応力集
中を緩和することができる。As shown in FIG. 4, a step portion (step portion) 17 is formed on the through-hole on the side where the solder pump 12 is mounted.
Is formed, the stress concentration can be reduced as in the case of the tapered portion 16.
【００２０】また、前記実施の形態においては、スルー
ホール１３の開口部に取り付けるバンプが半田バンプ１
２の場合について説明したが、本発明は半田バンプ１２
の場合に限定されるものではなく、例えば金バンプの場
合についても本発明を適用することが可能であることは
勿論である。In the above-described embodiment, the bumps to be attached to the openings of the through holes 13 are solder bumps 1.
2, the present invention relates to the solder bump 12
However, it is needless to say that the present invention can be applied to, for example, a gold bump.
【００２１】[0021]
【発明の効果】以上説明したように本発明によれば、例
えばＣＳＰ型半導体装置内のエポキシ系絶縁基板におい
て、スルーホール開口部にバンプによる応力集中を緩和
する応力集中緩和手段を設けることにより、例えば半田
バンプ取り付け穴（スルーホール）の周囲を面取りする
ことにより、薄型化を行なった場合に問題となっていた
半田バンプ部分への応力の集中を軽減し半田寿命を実使
用に耐え得る程度まで延長することができる。As described above, according to the present invention, for example, in an epoxy-based insulating substrate in a CSP type semiconductor device, a stress concentration relieving means for relieving stress concentration due to a bump is provided in a through hole opening. For example, by chamfering the periphery of the solder bump mounting hole (through hole), the concentration of stress on the solder bump part, which was a problem when thinning, was reduced and the solder life was long enough to withstand actual use Can be extended.
【００２２】それにより絶縁基板でポリイミド系よりは
安価なエポキシ系を使用した、例えばＣＳＰ型半導体装
置の薄型化を実現することができる。また、絶縁基板を
成形で製造する場合に成形金型の小変更のみで信頼性を
向上することができる為、加工費も軽減することができ
る。This makes it possible, for example, to reduce the thickness of a CSP type semiconductor device using an epoxy-based insulating substrate at a lower price than a polyimide-based insulating substrate. In addition, when the insulating substrate is manufactured by molding, the reliability can be improved only by a small change of the molding die, so that the processing cost can be reduced.
【図１】本発明の第１、第２実施の形態に共通の図であ
って、ＣＳＰ型パッケージの半導体装置の一部を破断し
て示す斜視図である。FIG. 1 is a view common to the first and second embodiments of the present invention, and is a perspective view showing a part of a semiconductor device of a CSP type package in a cutaway manner.
【図２】同第１実施の形態の断面図である。FIG. 2 is a sectional view of the first embodiment.
【図３】図２に示すＡ部分（要部）の拡大図である。FIG. 3 is an enlarged view of a portion A (main part) shown in FIG. 2;
【図４】同第２実施の形態の要部拡大図である。FIG. 4 is an enlarged view of a main part of the second embodiment.
１…半導体装置、２…集積回路チップ、３…電極パッ
ド、４…ワイヤ接続ランド、５…絶縁基板、６…バンプ
接続ランド、７…導体ワイヤ、８…銅配線、９…モール
ド樹脂、１０…接着層、１１…半田マスク、１２…半田
バンプ、１３…スルーホール、１４…導電性樹脂、１５
…銅メッキ、１６…テーパー部分、１７…段部分DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Integrated circuit chip, 3 ... Electrode pad, 4 ... Wire connection land, 5 ... Insulating substrate, 6 ... Bump connection land, 7 ... Conductor wire, 8 ... Copper wiring, 9 ... Mold resin, 10 ... Adhesive layer, 11: solder mask, 12: solder bump, 13: through hole, 14: conductive resin, 15
... copper plating, 16 ... tapered part, 17 ... stepped part
Claims (5)
ールで導通接続し、一面側のスルーホール開口部にバン
プを取付け、他面側に集積回路チップを接着してなる半
導体装置において、 前記一面側のスルーホール開口部に、前記バンプによる
応力集中を緩和する応力集中緩和手段を設けたことを特
徴とする半導体装置。1. A semiconductor device in which one surface side and another surface side of an insulating substrate are conductively connected by through holes, a bump is attached to a through hole opening on one surface side, and an integrated circuit chip is bonded to the other surface side. A semiconductor device, wherein a stress concentration relieving means for relieving stress concentration due to the bump is provided in the through hole opening on the one surface side.
ール開口部に形成したテーパー手段であることを特徴と
する請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said stress concentration reducing means is a taper means formed in said through hole opening.
ール開口部に形成した段差手段であることを特徴とする
請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein said stress concentration reducing means is a step means formed in said through hole opening.
および他面側を封止樹脂で覆った樹脂封止型半導体装置
であることを特徴とする請求項１乃至請求項３のいずれ
かに記載の半導体装置。4. The semiconductor device according to claim 1, wherein the semiconductor device is a resin-sealed semiconductor device in which the integrated circuit chip and the other surface are covered with a sealing resin. Semiconductor device.
であることを特徴とする請求項１乃至請求項４のいずれ
かに記載の半導体装置。5. The semiconductor device according to claim 1, wherein said semiconductor device is a CSP type semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14001799A JP2000332143A (en) | 1999-05-20 | 1999-05-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14001799A JP2000332143A (en) | 1999-05-20 | 1999-05-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000332143A true JP2000332143A (en) | 2000-11-30 |
Family
ID=15259010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14001799A Pending JP2000332143A (en) | 1999-05-20 | 1999-05-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000332143A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7030938B2 (en) * | 2000-11-09 | 2006-04-18 | Sony Corporation | Tuner and receiver apparatus |
| US7122462B2 (en) | 2003-11-21 | 2006-10-17 | International Business Machines Corporation | Back end interconnect with a shaped interface |
-
1999
- 1999-05-20 JP JP14001799A patent/JP2000332143A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7030938B2 (en) * | 2000-11-09 | 2006-04-18 | Sony Corporation | Tuner and receiver apparatus |
| US7122462B2 (en) | 2003-11-21 | 2006-10-17 | International Business Machines Corporation | Back end interconnect with a shaped interface |
| US7494915B2 (en) | 2003-11-21 | 2009-02-24 | International Business Machines Corporation | Back end interconnect with a shaped interface |
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