JP2000330923A - Data transfer system, transfer method, and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the hardware quantity without lowering the throughput performance. SOLUTION: In DMA transfer from a main storage 1 to peripheral devices 9-1 and 9-2, a prefetch data buffer 3 is dynamically allocated to channels 7-1 to 7-n as logical management units of the DMA transfer when necessary. The prefetch data buffer 3 is divided by a number less than the number (n) of the channels. The divided parts are called partitions, which are physical management units of buffering of prefetched data. Consequently, the prefetch data buffer is dynamically allocated when necessary, so that its use efficiency can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system, a data transfer method, and a recording medium on which a data transfer program is recorded, and more particularly to transferring data stored in a main memory to one of a plurality of channels via a data buffer. The present invention relates to a data transfer system, a data transfer method, and a recording medium on which a data transfer program is recorded.

[0002]

2. Description of the Related Art Conventionally, a prefetch data buffer has been
(Direct Memory Access) Division is performed for each channel, which is a logical management unit of transfer, and data is prefetched to a prefetch data buffer before a DMA transfer request from the channel control unit. In general, the size of the prefetch data buffer per channel is set so that the buffer is not emptied between sending a prefetch request to the central processing unit and storing read data in the buffer. A prefetch data buffer corresponding to the product of the size and the number of channels is required.

Here, consider an input / output processing device having a configuration in which the number of data transfer paths between the prefetch data buffer and the channel control unit is small and long burst transfer is mainly performed. Then, even after a transfer request from the channel control unit arrives, a data read request to the central processing unit is started.
Since there is only a performance decrease due to the lack of the first prefetch data, there is almost no decrease in throughput. In addition, since it is rare that a transfer that fills the buffers of all the channels is performed at the same time, it is highly likely that many buffers are not effectively used.

[0004]

SUMMARY OF THE INVENTION Incidentally, Japanese Patent Application Laid-Open No.
Japanese Patent Publication No. 151138 and Japanese Patent No. 2752834 describe a technique in which a data buffer is divided into the same number as channels and data is transferred using the divided units. In the prior art described in these publications, the transfer that fills the buffers of all the channels is rarely performed at the same time, so that many buffers are not effectively used. For this reason, there is a disadvantage that the unused portion is in the buffer and the amount of hardware is correspondingly large.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and has as its object the data transfer system and the data transfer method capable of reducing the amount of hardware without lowering the throughput performance. Another object of the present invention is to provide a recording medium on which a data transfer program is recorded.

[0006]

A data transfer system according to the present invention transfers data stored in a main memory to one of n (n is a positive integer) channels via a data buffer. In the system, the data buffer is divided into m partitions (m is a positive integer and m <n), and is provided corresponding to each of the divided partitions and indicates a use state of the corresponding partition. It is characterized by including a used partition flag and transfer control means for transferring the data to the channel using a partition other than the partition when the flag indicates that the corresponding partition is in use. Then, the transfer control means transfers the data to the channel using a partition corresponding to a flag which does not indicate that the partition is in use among the flags.

A data transfer method according to the present invention is a data transfer method for transferring data stored in a main memory to one of n (n is a positive integer) channels via a data buffer. The data buffer is divided into m partitions (m is a positive integer and m <n), and the usage status of the partition is indicated by a used partition flag provided corresponding to each of the divided partitions. And a transfer control step of transferring the data to the channel using a partition other than the partition when the used partition flag indicates that the corresponding partition is in use.

In a recording medium on which a data transfer program according to the present invention is recorded, a computer transfers data stored in a main memory to one of n (n is a positive integer) channels via a data buffer. A recording medium recording a data transfer program, wherein the data buffer has m partitions (m is a positive integer and m <
n), use status display means for displaying the use status of the partition by use partition flags provided corresponding to each of the divided partitions, and the use partition flag indicating that the corresponding partition is in use. A program for causing a computer to function as means for transferring the data to the channel using a partition other than the partition when the program is operating.

In short, in the present data transfer system, in the DMA output transfer, which is a transfer from the main memory to the peripheral control device, a prefetch data buffer is provided for the channel which is a logical management unit of the DMA transfer in consideration of load distribution. In addition, by dynamically allocating as needed and improving the utilization efficiency of hardware resources, it is possible to reduce the hardware amount of the prefetch data buffer without lowering the throughput.

In this case, the prefetch data buffer is divided by a number smaller than the number of channels. This is called a partition, and is a physical management unit for buffering prefetched data. The buffer size per partition is set so that burst transfer is not interrupted.

According to the prefetch start instruction and the display contents of the available partition corresponding to the designated channel number, the corresponding partition of the prefetch data buffer is selected. D
The MA transfer partition selection control unit determines the used partition display contents and the available partition display contents corresponding to the channel requested by the channel control unit.
Instructs selection of a partition of the prefetch data buffer or exchange of channels when there is no available partition.

That is, prefetch data buffers are dynamically allocated to channels as needed. In this manner, the total size of the prefetch data buffer can be reduced by dividing the prefetch data buffer by the number of channels and dividing the prefetch data buffer by a smaller number of partitions than the number of channels. For this reason, the amount of hardware can be reduced. Also, by controlling partitions to which channels can be assigned and grouping channels in units of partitions, the load in units of partitions can be equalized.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same parts as those in the other drawings are denoted by the same reference numerals.

FIG. 1 is a block diagram showing an embodiment of a data transfer system according to the present invention. In the figure,
The data stored in the main memory 1 is read out by the central processing unit 2 and transferred to the peripheral control device 8, and the other storage devices 9-1 and 9-
2 or the like, the input / output device 40 performs data transfer using the internal prefetch data buffer 3 in response to transfer requests from the n channels 7-1 to 7-n. The prefetch data buffer 3 in the input / output device 40 has m
It is divided into a number of partitions, and data transfer is performed using these partitions. Note that the number m of partitions is the number n of channels as described later.
Shall be smaller than

From the prefetch data buffer 3 to each channel 7
-I (i = 1 to n, the same applies hereinafter) is performed by the data transfer path 5-0 and the channel control unit 6-0, or the data transfer path 5-1 and the channel control unit 6-1.
Done by

FIG. 2 is a block diagram showing a configuration example of the input / output device 40 in FIG. In the figure, the prefetch data buffer 3 is divided as shown by a broken line. In this case, the data is divided by a number “m” smaller than the number of channels, and is used as a physical management unit for buffering prefetched data.

The prefetch data buffer 3 has a partition valid flag 20 indicating that the prefetch data buffer is in use (if there is free space in the buffer, a prefetch request can be made to the central processing unit 2 (FIG. 1)). A partition flag 21 indicating that DMA transfer is being performed from the prefetch data buffer 3 to the channel controller 6 (FIG. 1) via the data transfer path 5 for each partition. I do.

The input / output device 40 has, for each channel, a used partition display section 22 indicating a partition of the corresponding prefetch data buffer 3 and an available partition display section 23 indicating an assignable partition. And The available partition display unit 23 has a format as shown in FIG. That is, corresponding to each partition,
It is a display section showing whether the corresponding partition is valid.

In this embodiment, the prefetch data buffer 3 shown in FIG. 2 is divided by a number "m" smaller than the number "n" of channels, and this is called a partition. Then, a partition that can be assigned to each channel is set in the available partition display unit 23 as a physical management unit of buffering of prefetched data. The buffer size per partition is set so that burst transfer is not interrupted.

The prefetch request control unit 30 responds to the prefetch start instruction and the contents of the available partition display unit 23 corresponding to the designated channel number by using the prefetch data buffer 3.
Select the corresponding partition. The DMA transfer partition selection controller 31 controls the channel controller 6-0 or 6-
1 (FIG. 1), the used partition display unit 22 and the available partition display unit 23 corresponding to the channel requested by the user select a partition of the prefetch data buffer 3 or switch channels when there is no available partition. An instruction is given to the prefetch data buffer cancel control unit 32. The prefetch data buffer cancel control unit 32 transmits the partition flag 21 during transfer.
, The DMA transfer is interrupted, and the prefetch data buffer of the corresponding partition is canceled (= data discarded).

As described above, in the present system, the partitions of the prefetch data buffer 3 are not statically allocated to the channels in a one-to-one correspondence, but are dynamically allocated to the channels as needed. This makes it possible to reduce the total size of the prefetch data buffer by dividing the prefetch data buffer by m partitions smaller than the number of channels, rather than dividing the prefetch data buffer by n channels and statically allocating them. For this reason, the amount of hardware can be reduced, and by controlling partitions to which channels can be allocated and grouping channels in partition units, it is possible to equalize the load in partition units.

The input / output device 40 has a prefetch request control unit 30 for instructing the central processing unit 2 to issue a prefetch request. When a preemption start request for a specified channel is generated by the preemption start instruction, the prefetch request control unit 30 sets the available partition display unit 23 corresponding to the channel, the partition valid flags 20 of all corresponding partitions, and Is determined according to the above. If the allocation is possible, the prefetch request control unit 30 sets the partition valid flag 20 so that the prefetch request is sent to the central processing unit 2.
Instruct to.

The prefetch data transfer unit (not shown)
A write pointer (not shown) indicating the write position of the read data of the main memory 1 (FIG. 1) returned from the central processing unit 2 into the prefetch data buffer 3, and the read indicating the read position of the data to be transferred to the channel control unit. By controlling the pointer (not shown), the DM from the main memory to the channel control unit is controlled.
A transfer is performed.

When a DMA output transfer request is issued from the peripheral control device 8 (FIG. 1), the channel control unit 6 (FIG. 1) sends the DMA transfer request source to the data transfer request channel display unit 24 via the data transfer path 5. The channel number is stored.
The used partition display unit 22, available partition display unit 23 of the channel corresponding to the data transfer request channel display unit 24, and the partition valid flag 20 and the transferring partition flag 21 of the corresponding partition indicate the partition from which prefetched data is to be extracted. The determination and the partition assignment when the partition assignment has not been performed, and the instruction to replace the channel to the prefetch data buffer cancel control unit 32 when the allocatable partitions are all occupied by other channels, are DMA transfer partitions. This is performed by the selection control unit 31. When the channels are exchanged, the prefetch data buffer cancel control unit 32 sets the DM
A transfer is interrupted if necessary, and after waiting for the read data of the requested prefetch request to be returned from the central processing unit 2, the read pointer of the prefetch data buffer of the prefetch data transfer unit (not shown). (Not shown), clears the write pointer (not shown), and updates the used partition display unit 22.

The data transfer operation of the data transfer system having such a configuration will be described with reference to the flowcharts of FIGS. The operation of this system is roughly classified into a prefetch start instruction operation and a DMA transfer request operation.

1. In FIG. 4, when the prefetch start instruction is given to the prefetch request control unit 30 together with the channel number by a microinstruction or the like (step S41), first, all the partitions that match the contents of the corresponding available partition display unit 23 are assigned. The partition valid flags 20 are compared with each other (step S42).

As a result of the comparison, the partition valid flag 2
If there is a partition where 0 is invalid (= "0"), that partition is assigned to the channel (steps S43 → S44). In this case, the partition validity flag 20 is set to valid (= "1") (step S45), and the partition number assigned to the used partition display unit 22 is stored (step S4).
6). When the partition valid flag 20 becomes valid,
The prefetch request is sent to the central processing unit 2, and the data from the main memory 1 is sequentially stored in the prefetch data buffer 3 of the corresponding partition (step S47).

As a result of the comparison of the partition valid flag 20, all partitions that can be allocated are all valid (=
In the case of "1"), partition allocation is not performed and prefetching is not performed (steps S43 to S48).

2. DMA Transfer Request Referring to FIG. 5, in the DMA transfer request, first,
When a DMA transfer request is generated from the peripheral control device 10 (step S51), the DM is displayed on the data transfer request channel display unit 24 via the data transfer path 5 from the channel control unit 6.
The channel number of the request source of the A transfer is stored (step S
52). It is determined whether the partition valid flag 20 of the partition indicated by the used partition display unit 22 of the channel corresponding to the data transfer request channel display unit 24 is valid (= 1) (step S53).

If this flag is valid (= 1), and if data is stored in the prefetch data buffer of the partition indicated by the used partition display unit 22, the contents are transferred to the channel control unit 6 via the data transfer path 5. -0 or 6-1 (step S54).

On the other hand, when the partition valid flag is invalid (= 0), all partitions for which the available partition display unit 23 of the channel corresponding to the data transfer request channel display unit 24 is valid (= 1) Are compared (step S55). As a result of this comparison, if there is an invalid (= 0) partition (step S56), FIG.
The partition is assigned to the channel (step S61). At the time of this allocation, the partition valid flag 20 is set to valid (= "1"), and the allocated partition number is stored in the used partition display section 22 (step S62).

When the partition valid flag 20 becomes valid, a prefetch request is sent to the central processing unit 2, and the data from the main memory 1 is sequentially stored in the prefetch data buffer 3 of the corresponding partition (step S63).
As soon as the data is stored in the buffer 3, the contents of the prefetch data buffer are sent to the channel control unit 8 via the data transfer path 5-0 or 5-1 (step S64).

If there is no invalid (= 0) partition in the comparison result of the partition valid flag 20 (step S56), the process proceeds to FIG. The request is sent together with the channel number (step S71).

Next, the prefetch data buffer cancel control unit 32 controls the DMA transfer partition selection control unit 31.
In addition to the available partition display unit 23 corresponding to the channel number sent from, the partition flags in transfer 21 of all assignable partitions are referred to (step S72). As a result of this reference, if there is an invalid (= 0) partition, after waiting for the return of the read data of the requested prefetch request from the central processing unit 2, a prefetch data transfer unit (not shown) The read pointer (not shown) of the prefetch data buffer, the clear of the write pointer (not shown), and the used partition display section 22 of the channel number.
Is updated (steps S73 → S75).

In addition, the above-mentioned transfer-in-progress partition flag 2
If there is no invalid (= 0) partition as a result of the reference of 1, the DMA transfer is interrupted (step S
73 → S74), after waiting for the read data of the requested prefetch request to be returned from the central processing unit 2,
The read pointer (not shown) and the write pointer (not shown) of the prefetch data buffer of the prefetch data transfer unit (not shown) are cleared, and the used partition display unit 22 of the channel number is updated (step S75). .
The case where the DMA transfer is interrupted occurs only when a plurality of channels 7-i connected to different transfer paths 5 specify the assignment to the same partition.

As described above, in the present system, the following data transfer method is realized. That is, in the present system, the number of data stored in the main memory is n (n is a positive integer) via the data buffer.
A data transfer method for transferring data to any one of the channels is realized. The data buffer is divided into m partitions (m is a positive integer and m <n),
The used status of the partition is displayed by the used partition flag provided corresponding to each of the divided partitions, and when the used partition flag indicates that the corresponding partition is in use, the partition other than the used partition is used. It is transferring data to the channel. Further, in the data transfer control, data is transferred to the channel by using a partition corresponding to a flag which does not indicate that the partition is in use among the used partition flags.

Further, the DMA during transfer is provided by a partition flag during transfer provided corresponding to the m partitions.
This indicates that the transfer is being performed, and the data transfer is interrupted according to the contents of the partition flag during transfer.

Here, by preparing a recording medium on which a program for realizing the processes of FIGS. 4 to 7 described above is recorded and controlling each part of FIG. 1 using this, a data transfer similar to that described above can be achieved. It is clear that actions can be taken. As this recording medium, various recording media other than the semiconductor memory and the magnetic disk device not shown in FIG. 1 can be used.

If the computer is controlled by the program recorded on the recording medium, it is clear that the data transfer operation can be performed in the same manner as described above.
As this recording medium, various recording media other than the semiconductor memory and the magnetic disk device can be used.

In the above case, even if the size of the prefetch data buffer 3 is reduced to the number of partitions smaller than the number of channels, no partition is allocated to the channel when a DMA transfer request is issued from the channel control unit 6. Only in this case, the performance may be reduced as compared with the conventional case. However, this decrease in performance is negligible when the burst transfer is long.

As described above, by dynamically allocating the partitions of the prefetch data buffer to the channels as needed, the hardware amount of the prefetch data buffer can be reduced without lowering the throughput. In addition, it is possible to control the partitions that can be assigned to each channel, so that the load can be balanced between partitions,
This allows priority assignment of channels and the like. Also,
Since the prefetch data buffer is generally constituted by a RAM and has a higher failure rate than other parts, there is also obtained a secondary effect that a reduction in the hardware amount of the buffer can reduce the hardware failure rate.

The available partition display unit 23
It is apparent that the priority of each channel can be dynamically controlled by dynamically controlling the priority of each channel by a microinstruction or the like.

[0043]

As described above, the present invention dynamically allocates each partition of a prefetch data buffer to a channel as needed, thereby reducing the hardware amount of the prefetch data buffer without lowering the throughput. There is an effect that it can be reduced. In addition, since the partitions that can be assigned to each channel can be controlled, there is an effect that the load among the partitions can be equalized, the channel can be preferentially assigned, and the like. Furthermore, since the prefetch data buffer is generally composed of a RAM and has a higher failure rate than other parts, a secondary effect that a reduction in the hardware failure rate can be expected by reducing the amount of hardware of the buffer is also obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a data transfer system according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of an input / output device in the data transfer system of FIG.

FIG. 3 is a diagram showing a detailed format of an available partition.

FIG. 4 is a flowchart showing a data transfer operation of the present system in response to a prefetch start instruction.

FIG. 5 is a flowchart showing a data transfer operation of the present system in response to a DMA transfer request.

FIG. 6 is a flowchart showing a data transfer operation of the present system in response to a DMA transfer request.

FIG. 7 is a flowchart showing a data transfer operation of the present system in response to a DMA transfer request.

Claims (9)

[Claims] 1. A data transfer system for transferring data stored in a main memory to one of n (n is a positive integer) channels via a data buffer, wherein the data buffer comprises m data buffers. The partition is divided into partitions (m is a positive integer and m <n). A used partition flag provided corresponding to each of the divided partitions and indicating a use state of the corresponding partition; Transfer control means for transferring the data to the channel by using a partition other than the partition when busy is displayed. 2. The transfer control unit according to claim 1, wherein the transfer control unit transfers the data to the channel using a partition corresponding to a flag that does not indicate that the partition is in use among the flags. Data transfer system 3. The system further comprises a transfer-in-progress flag provided corresponding to the m partitions and indicating that DMA transfer is being performed using the corresponding partition, and wherein the data transfer is performed in accordance with the contents of the flag. 3. The data transfer system according to claim 1, wherein the data transfer is interrupted. 4. A data transfer method for transferring data stored in a main memory to one of n (n is a positive integer) channels via a data buffer, wherein the data buffer comprises m data buffers. Partition (m is a positive integer and m
<N), a use state display step of displaying the use state of the partition by use partition flags provided corresponding to each of the divided partitions, and a use state of the partition corresponding to the use partition flag A transfer control step of transferring the data to the channel using a partition other than the partition when is displayed. 5. The transfer control step, wherein the data is transferred to the channel using a partition corresponding to a flag that does not indicate that the partition is in use among the flags.
Data transfer method described. 6. A step of indicating that DMA transfer is being performed by a transferring partition flag provided corresponding to the m partitions, and a step of displaying the data transfer according to the contents of the transferring partition flag. 6. The data transfer method according to claim 4, further comprising the step of interrupting. 7. A recording medium which records a data transfer program for transferring data stored in a main memory to any one of n (n is a positive integer) channels via a data buffer by a computer. , The data buffer has m partitions (m is a positive integer and m <
n), use status display means for displaying the use status of the partition by use partition flags provided corresponding to each of the divided partitions, and the use partition flag indicating that the corresponding partition is in use. A program for causing a computer to function as means for transferring the data to the channel using a partition other than the partition when the data is stored. 8. The transfer control unit transfers the data to the channel by using a partition corresponding to a flag that does not indicate that the partition is in use among the flags. The recording medium according to the above. 9. The program according to claim 9, wherein said program is means for displaying that a DMA transfer is being performed by a transferring partition flag provided corresponding to said m partitions. 9. The recording medium according to claim 7, wherein the recording medium functions as means for interrupting the data transfer in response.