JP2000323527A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JP2000323527A JP2000323527A JP11134306A JP13430699A JP2000323527A JP 2000323527 A JP2000323527 A JP 2000323527A JP 11134306 A JP11134306 A JP 11134306A JP 13430699 A JP13430699 A JP 13430699A JP 2000323527 A JP2000323527 A JP 2000323527A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- semiconductor substrate
- bonding member
- wettability
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title description 6
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 239000000463 material Substances 0.000 claims abstract description 43
- 239000011248 coating agent Substances 0.000 claims description 20
- 238000000576 coating method Methods 0.000 claims description 20
- 230000005496 eutectics Effects 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- 229910017750 AgSn Inorganic materials 0.000 claims description 3
- 229910020658 PbSn Inorganic materials 0.000 claims description 3
- 101150071746 Pbsn gene Proteins 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 239000013039 cover film Substances 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 19
- 230000004888 barrier function Effects 0.000 description 10
- 238000000034 method Methods 0.000 description 8
- 238000005304 joining Methods 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に関し、特にバンプを有する半導体装置及び
その製造方法に関する。The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having bumps and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】半導体基板の表面上に形成されたバンプ
を、実装基板の表面上に形成された導電性の接合部材に
接触させ、両者の界面を共晶化させることにより、半導
体基板を実装基板に実装する技術が知られている。バン
プ材料として、例えばＡｕが用いられ、接合部材の材料
として、例えばＳｎやＡｕＳｎ合金が用いられる。2. Description of the Related Art A semiconductor substrate is mounted by bringing a bump formed on the surface of a semiconductor substrate into contact with a conductive bonding member formed on the surface of a mounting substrate and eutecticizing the interface between them. Techniques for mounting on a substrate are known. For example, Au is used as the bump material, and Sn or AuSn alloy is used as the material of the bonding member.
【０００３】[0003]
【発明が解決しようとする課題】バンプと接合部材とを
共晶化させる時に、接合部材の材料がバンプの側壁を伝
わり、バンプの下のパッドや配線まで達する場合があ
る。また、バンプの側面を伝わる接合部材の材料とバン
プの側面とでも共晶化が起こる。このため、加圧接合時
にバンプの形状が大きく変化する。バンプの下には、通
常バリアメタル層が配置されているが、バンプの径が大
きくなると、バンプがバリアメタル層からはみ出してし
まう場合がある。上述の現象は、半導体基板の表面に形
成されている各素子の信頼性を低下させる。When the bump and the joining member are eutecticized, the material of the joining member may propagate along the side wall of the bump to reach the pad and the wiring under the bump. Also, eutectic occurs between the material of the joining member that travels on the side surface of the bump and the side surface of the bump. For this reason, the shape of the bump changes significantly during pressure bonding. A barrier metal layer is usually arranged below the bump, but if the diameter of the bump is increased, the bump may protrude from the barrier metal layer. The above phenomenon reduces the reliability of each element formed on the surface of the semiconductor substrate.
【０００４】本発明の目的は、バンプを有する半導体装
置の、バンプに起因する信頼性の低下を防止することで
ある。It is an object of the present invention to prevent a semiconductor device having a bump from having a reduced reliability due to the bump.
【０００５】[0005]
【課題を解決するための手段】本発明の一観点による
と、半導体基板の表面上に形成されたバンプと、前記バ
ンプの側面を覆う導電性の被覆膜と、前記半導体基板の
前記表面に対向するように配置された実装基板と、前記
実装基板の対向面上に形成された導電性の接合部材であ
って、該接合部材が前記バンプの上面に密着し、該接合
部材の材料の、前記被覆膜の材料に対する濡れ性が、前
記バンプの材料に対する濡れ性よりも悪い前記接合部材
とを有する半導体装置が提供される。According to one aspect of the present invention, a bump formed on a surface of a semiconductor substrate, a conductive coating film covering a side surface of the bump, and a bump formed on the surface of the semiconductor substrate. A mounting board disposed so as to face, and a conductive bonding member formed on a facing surface of the mounting board, wherein the bonding member is in close contact with the upper surface of the bump, and a material of the bonding member is There is provided a semiconductor device having the bonding member, wherein wettability to the material of the coating film is lower than wettability to the material of the bump.
【０００６】本発明の他の観点によると、表面上に、外
部と電気的接続をとるためのパッドが形成された半導体
基板を準備する工程と、前記半導体基板の表面上に、前
記パッドと電気的に接続されたバンプを形成する工程
と、前記バンプの表面を覆うように、前記半導体基板上
に導電膜を堆積する工程と、前記導電膜を異方性エッチ
ングし、前記バンプの上面を露出させるとともに、該バ
ンプの側面に、前記導電膜からなる被覆膜を残す工程
と、表面上に接合部材が形成された実装基板であって、
該接合部材の材料の、前記被覆膜の材料に対する濡れ性
が、前記バンプの材料に対する濡れ性よりも悪い前記実
装基板を準備する工程と、前記接合部材に前記バンプの
上面が接触するように、前記実装基板と半導体基板とを
対向配置させ、前記バンプと接合部材との接触部に、前
記接合部材の材料とバンプの材料との共晶を形成する工
程とを有する半導体装置の製造方法が提供される。According to another aspect of the present invention, there is provided a step of preparing a semiconductor substrate on which a pad for making an electrical connection with the outside is formed on a surface, and the step of preparing the pad on the surface of the semiconductor substrate. Forming electrically connected bumps, depositing a conductive film on the semiconductor substrate so as to cover the surface of the bumps, anisotropically etching the conductive film to expose the upper surface of the bumps And a step of leaving a coating film made of the conductive film on the side surfaces of the bumps, and a mounting substrate having a bonding member formed on the surface thereof,
A step of preparing the mounting substrate, wherein the wettability of the material of the bonding member with respect to the material of the coating film is lower than the wettability of the material of the bump, and the upper surface of the bump is brought into contact with the bonding member. Forming the eutectic of the material of the bonding member and the material of the bump at the contact portion between the bump and the bonding member, with the mounting substrate and the semiconductor substrate facing each other. Provided.
【０００７】バンプの側面が、被覆膜で覆われており、
接合材料の、被覆膜に対する濡れ性が悪い。このため、
共晶化の際に、接合材料がバンプの側面を伝って半導体
基板側まで到達することを防止できる。これにより、半
導体装置の信頼性を高めることができる。[0007] The side surfaces of the bumps are covered with a coating film,
Poor wettability of the bonding material to the coating film. For this reason,
At the time of eutectic, it is possible to prevent the bonding material from reaching the semiconductor substrate side along the side surface of the bump. Thus, the reliability of the semiconductor device can be improved.
【０００８】ここで、濡れ性がよいか悪いかは、液体が
固体表面に接する場所において、液体の自由表面と固体
面とのなす接触角（液の内部にある角）の大小によって
決定することができる。接触角が大きいほど、濡れ性が
悪いということができる。Here, whether the wettability is good or bad is determined by the magnitude of the contact angle (the angle inside the liquid) between the free surface of the liquid and the solid surface at the place where the liquid contacts the solid surface. Can be. It can be said that the larger the contact angle, the poorer the wettability.
【０００９】[0009]
【発明の実施の形態】図１及び図２を参照して、本発明
の第１の実施例による半導体装置及びその製造方法につ
いて説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to a first embodiment of the present invention and a method for fabricating the same will be described with reference to FIGS.
【００１０】図１（Ａ）に示すように、半導体基板１の
表面上に層間絶縁膜２が形成され、その上に、配線３が
形成されている。配線３は、例えばＡｌで形成され、そ
の先端部にパッド３ａが配置されている。なお、配線３
は、半導体基板１の表面内に形成された半導体素子（図
示せず）に接続されている。保護膜４が配線３を覆う。
保護膜４は、例えばＳｉＯ2で形成される。保護膜４
に、パッド３ａの表面を露出させる開口５が形成されて
いる。As shown in FIG. 1A, an interlayer insulating film 2 is formed on a surface of a semiconductor substrate 1, and a wiring 3 is formed thereon. The wiring 3 is formed of, for example, Al, and a pad 3a is disposed at a tip portion thereof. Note that the wiring 3
Are connected to a semiconductor element (not shown) formed in the surface of the semiconductor substrate 1. The protection film 4 covers the wiring 3.
The protective film 4 is formed of, for example, SiO 2 . Protective film 4
Further, an opening 5 for exposing the surface of the pad 3a is formed.
【００１１】このように準備された基板の表面上に、Ｔ
ｉＷＮからなるバリア層１０とＡｕからなるシード層１
１とを、スパッタリングにより堆積する。バリア層１０
の厚さは例えば２００ｎｍであり、シード層１１の厚さ
は例えば１００ｎｍである。On the surface of the substrate thus prepared, T
iWN barrier layer 10 and Au seed layer 1
1 is deposited by sputtering. Barrier layer 10
Is 200 nm, for example, and the thickness of the seed layer 11 is 100 nm, for example.
【００１２】シード層１１の上に、厚さ２５〜３０μｍ
のレジスト膜１２を形成する。レジスト膜１２を露光、
現像し、パッド３ａに対応する位置に開口１３を形成す
る。メッキ法を用いて、開口１３内をＡｕからなるバン
プ１４で埋め込む。バンプ１４の高さは、約２０μｍで
ある。バンプ１４を形成した後、レジスト膜１２を除去
する。On the seed layer 11, a thickness of 25 to 30 μm
Is formed. Expose the resist film 12,
After the development, an opening 13 is formed at a position corresponding to the pad 3a. The inside of the opening 13 is filled with a bump 14 made of Au by using a plating method. The height of the bump 14 is about 20 μm. After forming the bumps 14, the resist film 12 is removed.
【００１３】図１（Ｂ）に示すように、バンプ１４の表
面を覆うように、基板の表面上にＰｔからなる導電膜２
０を形成する。導電膜２０は、スパッタリングにより形
成され、その厚さは約１００ｎｍである。As shown in FIG. 1B, a conductive film 2 made of Pt is formed on the surface of the substrate so as to cover the surface of the bump 14.
0 is formed. The conductive film 20 is formed by sputtering, and has a thickness of about 100 nm.
【００１４】図２（Ａ）の状態に至るまでの工程を説明
する。まず、Ａｒを用いたイオンミリングにより、導電
膜２０を異方性エッチングする。バンプ１４の上面が露
出し、その側面上にＰｔからなる被覆膜２０ａが残る。
バンプ１４の周囲にシード層１１が露出する。さらに、
イオンミリングを続け、露出したシード層１１を除去す
る。バンプ１４の周囲にバリア層１０が露出する。ＳＦ
6を用いたドライエッチングにより、露出したバリア層
１０をエッチングする。The steps up to the state shown in FIG. 2A will be described. First, the conductive film 20 is anisotropically etched by ion milling using Ar. The upper surface of the bump 14 is exposed, and the coating film 20a made of Pt remains on the side surface.
The seed layer 11 is exposed around the bump 14. further,
The ion milling is continued, and the exposed seed layer 11 is removed. The barrier layer 10 is exposed around the bump 14. SF
The exposed barrier layer 10 is etched by dry etching using 6 .
【００１５】図２（Ａ）に示すように、バリア層１０、
シード層１１、バンプ１４、及び被覆膜２０ａを含む突
起が残る。As shown in FIG. 2A, the barrier layer 10
A protrusion including the seed layer 11, the bump 14, and the coating film 20a remains.
【００１６】図２（Ｂ）に示すように、実装基板３０
を、半導体基板１に対向配置する。実装基板３０の対向
面上に、ＡｕＳｎからなる接合部材３１が形成されてい
る。接合部材３１は、バンプ１４の上面に接触する。Ａ
ｕとＳｎの共晶点以上まで加熱し、バンプ１４と接合部
材３１との接触部において、両者を共晶化させる。As shown in FIG. 2B, the mounting substrate 30
Are arranged to face the semiconductor substrate 1. A bonding member 31 made of AuSn is formed on the facing surface of the mounting substrate 30. The joining member 31 contacts the upper surface of the bump 14. A
Heating is performed to a temperature equal to or higher than the eutectic point of u and Sn, and eutectic is formed at the contact portion between the bump 14 and the bonding member 31.
【００１７】ＡｕＳｎの、Ｐｔに対する濡れ性は、Ａｕ
に対する濡れ性よりも悪い。このため、共晶化時に、接
合部材３１を形成する材料が被覆膜２０ａの表面を伝っ
て半導体１側に到達することを防止できる。また、バン
プ１４の側面では共晶化が起きないため、バンプ１４の
変形が抑制される。このため、バンプを用いた接続部の
信頼性を高めることができる。The wettability of AuSn to Pt is Au
Worse than wettability to For this reason, at the time of eutectic formation, the material forming the bonding member 31 can be prevented from traveling along the surface of the coating film 20a and reaching the semiconductor 1 side. Further, since no eutectic occurs on the side surfaces of the bumps 14, deformation of the bumps 14 is suppressed. Therefore, the reliability of the connection portion using the bump can be improved.
【００１８】次に、図３を参照して、本発明の第２の実
施例による半導体装置及びその製造方法について説明す
る。Next, a semiconductor device according to a second embodiment of the present invention and a method for fabricating the same will be described with reference to FIG.
【００１９】図３（Ａ）に示すように、半導体基板１の
表面上に、層間絶縁膜２、配線３、パッド３ａ、及び保
護膜４が形成されている。この基板上に、バリア層１
０、シード層１１、レジスト膜１２を形成し、開口１３
を設ける。ここまでの工程は、第１の実施例の図１
（Ａ）で説明した工程と同様である。メッキ法を用い
て、開口１３内にＡｕを埋め込みバンプ下部１４ａを形
成する。バンプ下部１４ａの高さは、例えば１０μｍで
ある。As shown in FIG. 3A, an interlayer insulating film 2, wirings 3, pads 3a, and a protective film 4 are formed on the surface of a semiconductor substrate 1. On this substrate, a barrier layer 1
0, a seed layer 11 and a resist film 12 are formed.
Is provided. The steps up to this point are the same as those in the first embodiment shown in FIG.
This is the same as the process described in (A). Au is buried in the opening 13 using a plating method to form a lower portion 14a of the bump. The height of the bump lower part 14a is, for example, 10 μm.
【００２０】図３（Ｂ）に示すように、レジスト膜１２
を等方的にエッチングする。例えば、酸素プラズマを用
いたアッシング時の圧力を調節することにより、ほぼ等
方的にエッチングを行うことができる。等方的なエッチ
ングにより、開口１３の開口部近傍にテーパ面１３ａが
形成される。As shown in FIG. 3B, the resist film 12
Is isotropically etched. For example, by adjusting the pressure at the time of ashing using oxygen plasma, etching can be performed almost isotropically. By the isotropic etching, a tapered surface 13a is formed near the opening of the opening 13.
【００２１】メッキ法を用い、テーパ面１３ａ及びバン
プ下部１４ａの上面により画定される凹部を、Ａｕで埋
め込む。バンプ下部１４ａの上に、バンプ上部１４ｂが
形成される。バンプ上部１４ｂは、半導体基板１の表面
から高くなるに従って徐々に広がった形状を有する。バ
ンプ上部１４ｂを形成した後、レジスト膜１２を除去す
る。The recess defined by the tapered surface 13a and the upper surface of the lower portion 14a of the bump is filled with Au by plating. The bump upper part 14b is formed on the bump lower part 14a. The bump upper portion 14b has a shape that gradually widens as the height from the surface of the semiconductor substrate 1 increases. After forming the bump upper part 14b, the resist film 12 is removed.
【００２２】第１の実施例の図１（Ｂ）及び図２（Ａ）
と同様の工程を経て、図３（Ｃ）に示す状態に至る。バ
ンプ下部１４ａ及びバンプ上部１４ｂの側面上に、Ｐｔ
からなる被覆膜２０ａが形成される。バンプ上部１４ｂ
が庇状に突き出た部分の下方に、シード層１１及びバリ
ア層１０が残る。これは、イオンミリング時に、この部
分が庇状の突出部の陰になるためである。FIGS. 1B and 2A of the first embodiment.
Through the same steps as described above, the state shown in FIG. Pt is formed on the side surfaces of the bump lower part 14a and the bump upper part 14b.
Is formed. Upper bump 14b
The seed layer 11 and the barrier layer 10 remain below the portion where the has protruded like an eave. This is because at the time of ion milling, this portion becomes a shadow of the eave-shaped projection.
【００２３】第２の実施例によるバンプは、第１の実施
例の場合に比べて広い上面を有する。このため、実装基
板に実装したときの機械的強度を高めることができる。
また、バンプ下部１４ａとバンプ上部１４ｂの側面がＰ
ｔからなる被覆膜２０ａで覆われているため、第１の実
施例の場合と同様に、実装基板側の接合材料がパッド３
ａ内まで侵入することを防止できる。The bump according to the second embodiment has a wider upper surface than that of the first embodiment. For this reason, the mechanical strength when mounted on the mounting board can be increased.
Also, the side surfaces of the bump lower part 14a and the bump upper part 14b are P
t, the bonding material on the mounting substrate side is the pad 3 as in the case of the first embodiment.
a can be prevented from entering.
【００２４】上記実施例では、バンプ材料としてＡｕを
用い、被覆膜の材料としてＰｔを用い、接合部材の材料
としてＡｕＳｎを用いた。より一般的に、これらの材料
として、接合部材の材料の、被覆膜の材料に対する濡れ
性が、バンプ材料に対する濡れ性よりも悪くなるような
組み合わせのものを用いてもよい。例えば、接合部をＳ
ｎまたはＡｕＳｎで形成し、バンプをＡｕで形成する場
合、被覆膜の材料として、Ｐｔ、ＴｉＷＮ等を用いるこ
とができる。また、接合部材をＰｂＳｎまたはＡｇＳｎ
で形成し、バンプをＡｕで形成する場合、被覆膜の材料
として、ＴｉＮ、ＴｉＷ、ＴｉＷＮ、ＷＳｉ、ＷＳｉ
Ｎ、Ｃｒ、Ａｌ等を用いることができる。In the above embodiment, Au was used as a bump material, Pt was used as a material for a coating film, and AuSn was used as a material for a bonding member. More generally, a combination of these materials may be used such that the wettability of the bonding member material with respect to the coating film material is lower than the wettability with respect to the bump material. For example, if the joint is S
In the case where the bumps are formed of Au or AuSn and the bumps are formed of Au, Pt, TiWN, or the like can be used as the material of the coating film. Further, the joining member is made of PbSn or AgSn.
When the bump is formed of Au, TiN, TiW, TiWN, WSi, WSi
N, Cr, Al or the like can be used.
【００２５】以上実施例に沿って本発明を説明したが、
本発明はこれらに制限されるものではない。例えば、種
々の変更、改良、組み合わせ等が可能なことは当業者に
自明であろう。The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
【００２６】[0026]
【発明の効果】以上説明したように、本発明によると、
バンプの側面を、実装基板側の接合材料の濡れ性が悪い
材料からなる膜で覆うことにより、接合材料がバンプの
下のパッドや配線等まで侵入することを防止できる。こ
れにより、半導体装置の信頼性向上を図ることが可能に
なる。As described above, according to the present invention,
By covering the side surfaces of the bumps with a film made of a material having poor wettability of the bonding material on the mounting substrate side, it is possible to prevent the bonding material from penetrating to pads, wiring, and the like below the bumps. This makes it possible to improve the reliability of the semiconductor device.
【図１】本発明の第１の実施例による半導体装置の製造
方法を説明するためのバンプ部分の断面図（その１）で
ある。FIG. 1 is a sectional view (part 1) of a bump portion for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第１の実施例による半導体装置の製造
方法を説明するためのバンプ部分の断面図（その２）で
ある。FIG. 2 is a sectional view (part 2) of a bump portion for describing a method of manufacturing a semiconductor device according to a first embodiment of the present invention.
【図３】本発明の第２の実施例による半導体装置の製造
方法を説明するためのバンプ部分の断面図である。FIG. 3 is a sectional view of a bump portion for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention.
１ 半導体基板 ２ 層間絶縁膜 ３ 配線 ３ａ パッド ４ 保護膜 １０ バリア層 １１ シード層 １２ レジスト膜 １３ 開口 １４ バンプ ２０ 導電膜 ２０ａ 被覆膜 ３０ 実装基板 ３１ 接合部材 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Interlayer insulating film 3 Wiring 3a pad 4 Protective film 10 Barrier layer 11 Seed layer 12 Resist film 13 Opening 14 Bump 20 Conductive film 20a Coating film 30 Mounting substrate 31 Joining member
Claims (6)
と、 前記バンプの側面を覆う導電性の被覆膜と、 前記半導体基板の前記表面に対向するように配置された
実装基板と、 前記実装基板の対向面上に形成された導電性の接合部材
であって、該接合部材が前記バンプの上面に密着し、該
接合部材の材料の、前記被覆膜の材料に対する濡れ性
が、前記バンプの材料に対する濡れ性よりも悪い前記接
合部材とを有する半導体装置。A bump formed on a surface of the semiconductor substrate; a conductive coating film covering a side surface of the bump; a mounting substrate arranged to face the surface of the semiconductor substrate; A conductive bonding member formed on the opposing surface of the mounting substrate, wherein the bonding member is in close contact with the upper surface of the bump, and the wettability of the material of the bonding member to the material of the coating film is A semiconductor device comprising: the bonding member having poorer wettability with respect to a bump material;
が、前記半導体基板の表面から高くなるに従って徐々に
広がった形状を有する請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein at least a part of the upper surface side of the bump has a shape that gradually widens as the height increases from the surface of the semiconductor substrate.
と、 前記バンプの側面を覆う導電性の被覆膜とを有し、Ｓ
ｎ、ＡｕＳｎ、ＡｇＳｎ、ＰｂＳｎからなる群より選択
されたひとつの接合材料の、前記バンプの材料に対する
濡れ性よりも、前記被覆膜の材料に対する濡れ性の方が
悪い半導体装置。3. A semiconductor device comprising: a bump formed on a surface of a semiconductor substrate; and a conductive coating film for covering a side surface of the bump.
A semiconductor device in which one bonding material selected from the group consisting of n, AuSn, AgSn, and PbSn has lower wettability with respect to the material of the coating film than wettability with respect to the material of the bump.
が、前記半導体基板の表面から高くなるに従って徐々に
広がった形状を有する請求項３に記載の半導体装置。4. The semiconductor device according to claim 3, wherein at least a part of the upper surface side of the bump has a shape that gradually widens as the height increases from the surface of the semiconductor substrate.
のパッドが形成された半導体基板を準備する工程と、 前記半導体基板の表面上に、前記パッドと電気的に接続
されたバンプを形成する工程と、 前記バンプの表面を覆うように、前記半導体基板上に導
電膜を堆積する工程と、 前記導電膜を異方性エッチングし、前記バンプの上面を
露出させるとともに、該バンプの側面に、前記導電膜か
らなる被覆膜を残す工程と、 表面上に接合部材が形成された実装基板であって、該接
合部材の材料の、前記被覆膜の材料に対する濡れ性が、
前記バンプの材料に対する濡れ性よりも悪い前記実装基
板を準備する工程と、 前記接合部材に前記バンプの上面が接触するように、前
記実装基板と半導体基板とを対向配置させ、前記バンプ
と接合部材との接触部に、前記接合部材の材料とバンプ
の材料との共晶を形成する工程とを有する半導体装置の
製造方法。5. A step of preparing a semiconductor substrate on a surface of which a pad for making an electrical connection with the outside is formed; and forming a bump electrically connected to the pad on the surface of the semiconductor substrate. Forming a conductive film on the semiconductor substrate so as to cover the surface of the bump; anisotropically etching the conductive film to expose an upper surface of the bump; A step of leaving a coating film made of the conductive film, and a mounting substrate having a bonding member formed on a surface thereof, wherein the material of the bonding member has a wettability to the material of the coating film,
A step of preparing the mounting substrate that is worse than the wettability with respect to the material of the bump; and disposing the mounting substrate and the semiconductor substrate to face each other so that an upper surface of the bump contacts the bonding member; Forming a eutectic of the material of the bonding member and the material of the bump at a contact portion with the semiconductor device.
のパッドが形成された半導体基板を準備する工程と、 前記半導体基板の表面上に、前記パッドと電気的に接続
されたバンプを形成する工程と、 前記バンプの表面及び前記半導体基板表面を覆う導電膜
であって、Ｓｎ、ＡｕＳｎ、ＡｇＳｎ、ＰｂＳｎからな
る群より選択されたひとつの接合材料の、前記バンプの
材料に対する濡れ性よりも、前記導電膜の材料に対する
濡れ性の方が悪い前記導電膜を形成する工程と、 前記導電膜を異方性エッチングし、前記バンプの上面を
露出させるとともに、該バンプの側面に、前記導電膜か
らなる被覆膜を残す工程とを有する半導体装置の製造方
法。6. A step of preparing a semiconductor substrate on a surface of which a pad for making an electrical connection with the outside is formed; and forming a bump electrically connected to the pad on the surface of the semiconductor substrate. Forming a conductive film covering the surface of the bump and the surface of the semiconductor substrate, wherein the bonding material is selected from the group consisting of Sn, AuSn, AgSn, and PbSn. A step of forming the conductive film having a poorer wettability with respect to the material of the conductive film; anisotropically etching the conductive film to expose an upper surface of the bump; Leaving a coating film made of a film.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13430699A JP3515013B2 (en) | 1999-05-14 | 1999-05-14 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13430699A JP3515013B2 (en) | 1999-05-14 | 1999-05-14 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000323527A true JP2000323527A (en) | 2000-11-24 |
| JP3515013B2 JP3515013B2 (en) | 2004-04-05 |
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ID=15125218
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|---|---|---|---|
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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