JP2000298638A - DMA transfer device - Google Patents

Abstract

(57) [Problem] To reduce the bus occupancy by DMA and reduce the time in the case where there are a plurality of external request devices or when there are external request devices with a short DREQ signal generation cycle on the same bus. And a DMA transfer device capable of effectively using a bus. SOLUTION: The DMA transfer device includes a CPU 100, a DM
An AC 110, an external request device 111, an external request device 112, and an external memory 113 are provided.
DREQ signal mask circuit 121,1 for masking Q signal
The DREQ signal mask circuits 121 and 122 mask the DREQ0 / DREQ1 signals to control the bus occupation state by the DMA transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA (Direct M
More specifically, the present invention relates to a DMA transfer device having a DMA control unit for performing a DMA transfer control for directly transferring data between a memory and an external request device independently of the operation of a CPU.

[0002]

2. Description of the Related Art In a DMA transfer, data is transferred directly between a main memory and a peripheral device such as an I / O device (for example, an external request device) without using a CPU. This enables high-speed and large-capacity data transfer without the overhead of the CPU. In DMA transfer, a DMAC (Direct Memory Access Controller) generally manages the bus to control the transfer.

Conventionally, in a system for performing a DMA transfer between a DMAC and an external request device, a DMAC
Receives a DMA request (DREQ) signal output from an external request device and controls another device so that data can be transferred between the memory device and the external request device.

FIG. 32 is a block diagram showing the configuration of a conventional DMA transfer device, which exemplifies data transfer between a DMAC and an external request device.

In FIG. 32, 1 is a CPU and 2 is a DMA.
C, 3 and 4 are a plurality of (two) external request devices (external request devices 1 and 2) and 5 is an external memory.

[0006] Request signals DREQ1 / DREQ2 are output from the external request devices 3 and 4 to the DMAC2. DMAC2 receives respective DMA request signals DREQ1 / DREQ2,
2 outputs a bus request (BREQ) signal to the CPU 1 in response to the input of the DREQ signal, and requests the CPU 1 to release the bus.

[0007] Upon receiving the BREQ, the CPU 1 outputs a bus release permission (BACK) signal to release the bus to the DMAC 2. Here, when there are a plurality of external request devices, the number of occurrences of DREQ from each device increases. Therefore, the order in which BREQ signals are generated inside the DMAC is adjusted (arbitrated), and the DM of each external request device is adjusted.
A transfer is realized.

[0008]

However, such a conventional DMA transfer device requires arbitration of a DREQ signal when mounted on a plurality of external request device systems as described above. The number of external request devices and the DRE of the external request device
There is a problem in that the bus occupation ratio by the DMA increases due to the generation cycle of the Q signal, and there is a possibility that a normal series of processing by the CPU is extremely extended.

Hereinafter, this problem will be described.

FIG. 33 is a timing chart conceptually showing DMAC arbitration timing.

In a DMAC having three channels, the time required for one DMA transfer of each CH is T. In the case of FIG. 33, the DMAC is the DMA of each channel.
And the channels are used in a round-robin system such as CH1 → CH2 → CH3 → CH1. However, when this method is used, the bus is occupied only for the DMA transfer, and the time during which the processor performs processing using the bus may be extremely extended in time.

According to the present invention, when a plurality of external request devices exist, or when an external request device having a short DREQ signal generation cycle exists on the same bus,
It is an object of the present invention to provide a DMA transfer device capable of reducing the bus occupation ratio by DMA and effectively using the bus in time.

[0013]

SUMMARY OF THE INVENTION A DMA transfer device according to the present invention includes a DMA controller for performing a DMA transfer control for directly transferring data between a memory and an external request device, independently of an operation of a CPU. When a DREQ signal is generated from an external request device, the
A DMA transfer device that outputs a BREQN signal to request a bus release, sends a DACK signal to an external request device when a BACKN signal is returned from the CPU, and controls data transfer between the memory and the external request device. In the external request device, the DREQ
A mask means for masking a signal is provided, and the DREQ signal is masked by the mask means to control a bus occupation state by DMA transfer.

A DMA transfer device according to the present invention includes a DMA control unit for performing a DMA transfer control for directly transferring data between a memory and an external request device, independently of the operation of the CPU. When the DREQ signal is generated from the
N signal is output to request bus release, and BA
When the CKN signal is returned, D is sent to the external request device.
In a DMA transfer device that sends an ACK signal and controls data transfer between a memory and an external request device,
The MA control unit includes masking means for masking the DREQ signal.
The bus occupation state by the A transfer is controlled.

A DMA transfer device according to the present invention includes a DMA control unit for performing a DMA transfer control for directly transferring data between a memory and an external request device, independently of the operation of the CPU. When the DREQ signal is generated from the
N signal is output to request bus release, and BA
When the CKN signal is returned, D is sent to the external request device.
In a DMA transfer device that sends an ACK signal and controls data transfer between a memory and an external request device,
The MA control unit includes mask means for masking the BREQN signal, and controls the bus occupation state by DMA transfer by masking the BREQN signal by the mask means.

The DMA transfer apparatus according to the present invention may further include means for controlling a mask time according to the number of external request devices that can operate simultaneously.

The DMA transfer device according to the present invention may include a management unit for managing the processing load of the CPU and a unit for controlling the mask time according to the processing load of the CPU.

The DMA transfer device according to the present invention has a DREQ
DREQ signal cycle detection means for detecting a signal generation cycle may be provided, and the mask means may mask the DREQ signal based on the DREQ signal generation cycle.

The DMA transfer apparatus according to the present invention includes a BR for detecting a generation cycle of a BREQN signal generated in response to a DREQ signal of a plurality of external request devices permitted to operate.
EQN signal period detecting means, and the masking means comprises a BRE
The BREQN signal may be masked based on the QN signal generation cycle.

[0020] The DMA transfer device according to the present invention comprises a managing means for managing the processing load of the CPU, a setting means for determining a bus occupancy rate associated with the CPU processing and setting a limit value thereof,
Means for controlling the mask time in accordance with the processing load and the limit value of U.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram showing a configuration of a DMA transfer device according to a first embodiment of the present invention. The present embodiment is applied to a system that performs a DMA transfer between an external memory and an external request device.

In FIG. 1, a DMA transfer device includes a CPU
100, DMAC 110 (DMA control unit), external request device 111, external request device 112,
And an external memory 113.

The DMAC 110 has two DMA channels, which are called CH0 and CH1. CH0 and CH1 are connected to the external request device 111 and the external request device 112, respectively.

Inside the external request device 111, a DREQ signal masking circuit 121 (masking means) is provided.
Also, the DRE is provided inside the external request device 112.
A Q signal masking circuit 122 (masking means) is provided.
The REQ signal mask circuits 121 and 122
Mask signals mask_en0 and mask_en1 from
Is controlled by

The mask signals mask_en0, mask_
The signal en1 is a signal for controlling enable / disable of the DREQ signal mask circuits 121 and 122, and both signals are active “H” (a signal active at “H” level).

A BREQ (bus release request) signal is output from the DMAC 110 to the CPU 100,
From 0, a BACK (bus release permission) signal is output to the DMAC 110.

The external memory 113 serves as a destination (transfer destination) or a source (transfer source) of the DMA transfer.

FIGS. 2 and 3 are circuit diagrams showing the structure of the DREQ signal mask circuits 121 and 122. FIG.
FIG. 3 shows a circuit configuration when the REQ signal is active "H", and FIG. 3 shows a circuit configuration when the DREQ signal is active "L" (active signal at "L" level).

In FIG. 2, the DREQ signal mask circuits 121 and 122 when the DREQ signal is active "H"
Is constituted by an AND gate 131. DREQ signal inside the external request device is DREQ_P_in
(In the case of active “H”), and a mask signal for controlling the mask is mask_en.

The AND gate 131 outputs the mask signal mas.
AND of inverted signal of k_en and DREQ_P_in signal
Takes logic and outputs DREQ_P. In this case, mas
When k_en = “H”, the DREQ_P_in signal is masked, and DREQ_P is output as an output.

Similarly, in FIG. 3, when the DREQ signal is active "L", the DREQ signal mask circuit 12
Reference numerals 1 and 122 each include an OR gate 132.

The OR gate 132 outputs the mask signal mask
OR logic of _en and DREQ_N_in signals and DR
Outputs EQ_N. In this case, mask_en =
When “H”, the DREQ_N_in signal is masked, and DREQ_N is output as an output.

Hereinafter, the operation of the DMA transfer device configured as described above will be described.

Here, CH0 is set by mask_en0.
DREQ signal mask circuit 121 is enabled,
A case where the DREQ signal mask circuit 122 of CH1 is enabled by mask_en1 will be described.

FIG. 4 is a timing chart showing the DMA transfer operation of the DMA transfer device.
500 ns), one DMA transfer is performed. In the figure, C
H0 and CH1 indicate two DMA channels of the DMAC 110.

As shown in FIG. 4, CH0 /
It is assumed that each DREG of CH1 has occurred simultaneously.

In the section of T2, DREQ of CH0
Since the 0 signal is masked by the mask_en0 signal, the DMA transfer of CH1 is being performed. At this time, the mask_en1 signal is in a disabled state (“L”).

Next, in the section of T3, both DMs
Since the A channel is masked, no DMA transfer is performed. In this section, the CPU 100 occupies the bus,
Performs processing according to the program.

Next, in the section of T4, mask_
Since en1 is in an enabled state (“H”), the DREQ1 signal of CH1 is masked, and DREQ1
Is not output, so that the DMA sequence is not performed.
In this section, the DMA transfer of CH0 is performed.

Next, in the section of T5, the processing of the CPU 100 is performed as in the section of T3. Therefore, the processing of the CPU 100 does not stop here.

As described above, mask_en0, mask
_En1 to mask the DREQ signal and
The generation cycle of the Q0 / DREQ1 signal is changed.

Also, mask_en0 / mask_en
1 is controlled by the CPU 100, but such a periodic enable signal can be realized by using a timer built in the CPU 100. For example, 500n
s interrupt processing, mask_en0 / mask_e
By setting n1 to be alternately enabled, each C
In the H DMA, DREQ occurs once every 2 μs. Furthermore, the setting interval can be shortened by setting a timer for periodically controlling the enable in the external request device, instead of setting from the CPU 100.

As described above, the DMA transfer device according to the first embodiment includes the CPU 100, the DMAC 110,
It comprises an external request device 111, an external request device 112, and an external memory 113. The external request devices 111 and 112 include DREQ signal mask circuits 121 and 122 for masking a DREQ signal.
The DREQ signal mask circuits 121 and 122 output DREQ0 /
Since the DREQ1 signal is masked to control the bus occupation state by the DMA transfer, the DREQ signal masking circuits 121 and 1 are controlled by the mask_en0 / mask_en1 signal (active “H”) from the CPU 100.
22 generates the DREQ signal periodically by masking the DREQ0 / DREQ1 signal,
It is possible to control the occupancy of the system bus by the MA.
As a result, it is possible to avoid that the bus is occupied by the DMA and the processing of the CPU cannot be performed.
This has the effect of preventing breakdown due to the intervention of C.

Further, since there is no change in the configuration of the DMAC, the throughput and reliability of the entire system can be improved without changing the existing CPU system. In addition, since it can be realized by adding a simple component called a gate circuit, it can be implemented at low cost.

In this embodiment, DREQ0 / DREQ is stored inside the external request devices 111 and 112.
DREQ signal mask circuit 121,1 for masking one signal
22 are provided, but these mask circuits 12
The components 1 and 122 need only be installed on the external request device side, and need not necessarily be configured to be installed inside the external request device. Second Embodiment FIG. 5 is a block diagram showing a configuration of a DMA transfer device according to a second embodiment of the present invention. In this embodiment, the DMAC
This is an example applied to a system that performs DMA transfer between an external memory device and an external request device by using. In the description of the DMA transfer device according to the present embodiment, the same components as those in FIG. 1 are denoted by the same reference numerals.

In FIG. 5, the DMA transfer device has a CPU
100, DMAC 200, external request device 24
0, external request device 241, and external memory 1
13.

The DMAC 200 has two DMA channels, which are called CH0 and CH1. CH0 and CH1 are connected to the external request device 240 and the external request device 241, respectively.

The DMAC 200 is provided for each channel, and a mask signal mask_en from the CPU 100 is provided.
DREQ signal masking circuits 210 and 220 controlled by 0, mask_en1, and DREQ signal masking circuit 2
An arbitration circuit 230 that arbitrates the BREQ0 signal and the BREQ1 signal of 10, 220.

The mask signals mask_en0, mask_
en1 is a DREQ signal mask circuit 2 for CH0 and CH1
These signals are for switching enable / disable of the signals 10, 220, and both signals are active "H".

The mask_e of the first embodiment is used.
The n signal means the mask signal itself, but the mask_e described in each embodiment described later including this embodiment.
The n signal means a signal for controlling whether to operate the mask circuit. Therefore, when the mask circuit is always operated, the mask_en signal can be omitted.

The CPU 100 outputs the mask signal mask
_En0 and mask_en1 are output to the DREQ signal mask circuits 210 and 220 to output the DREQ signal mask circuit 21.
0,220. In addition, the CPU 100
A timer count value can be set for the Q signal mask circuits 210 and 220, and the length of the generated mask signal changes according to the timer count value set by the CPU 100.

When external request device 240 is DMAC
DREQ0 to be output to the DMAC 200, and DR which the external request device 241 outputs to the DMAC 200.
The EQ signal is set to DREQ1, and DREQ0 and DREQ returned from the DMAC 200 to the external request devices 240 and 241.
DACK signals for REQ1 are respectively DACK0,
DACK1.

The DMAC 200 outputs a BREQN signal (bus release request signal: a signal for requesting the CPU to release the bus right / active “L”) to the CPU 100.
BACKN signal (bus acknowledge signal: signal indicating that release of bus right is permitted to external DMAC / active "L") is output.

Here, there are two DMA transfer directions, that is, an external request device → external memory direction and an external memory → external request device direction.
It is assumed that the CPU 100 can set the DMAC 200.

FIG. 6 shows the DREQ signal mask circuit 21.
It is a block diagram which shows the structure of 0,220. Since the DREQ signal mask circuits 210 and 220 of each channel have the same configuration, the DREQ signal mask circuit 210 will be described as a representative.

In FIG. 6, the DREQ signal mask circuit 2
Reference numeral 10 denotes a counter circuit 211 that counts (decrements) at the rising edge of the sampling clock, compares the count data with a predetermined value “0”, and when “0” matches the count data, a pulse for the period of the sampling clock, ie, a counter. It is composed of a comparator 212 that outputs a TC (Terminal Count) signal, and a mask circuit 213.

The counter circuit 211 receives an initial value for counting from the data bus and a sampling clock for counting. Further, a current count value which is data counted by the counter circuit 211 is input to the comparator 212, and a counter TC signal is output from the comparator 212.

The counter TC signal is a signal which becomes a pulse of "H" with a width of one sampling clock in a section where the input count data value becomes "0".
Indicates that the count has ended.

The mask circuit 213 includes the comparator 21
2 is input, the DREQ signal and the DACK signal are input while the counter TC signal output from
A Q signal is output.

FIG. 7 is a diagram showing a detailed configuration inside mask circuit 213 of FIG.

In FIG. 7, a mask circuit 213 includes a mask signal generation circuit 214 for outputting a mask signal that enables a mask signal generated internally when a DACK signal is input based on a counter TC signal, and a generation circuit. And an OR gate 215 that takes the OR logic of the mask signal and the DREQ signal.

Hereinafter, the operation of the DMA transfer device configured as described above will be described.

FIG. 8 is a timing chart for explaining the operation of the DMA transfer device. In the figure, the number (1)
Symbols (5) to (5) are used to describe operation timings or sections of operation.

First, the DREQ0 signal mask circuit 210 for CH0 of the two channels CH0 and CH1 will be described as an example.

In the timing chart of FIG.
It is assumed that the EQ0 signal is enabled (“H”) after a lapse of a predetermined time after the DACK0 signal is disabled (“L”).

At the timing (1) in FIG. 8, the CPU 100 writes the timer count value to the DREQ0 signal mask circuit 210. In the case of this operation, “5” is written.

Next, at the timing of (1) -1 in FIG.
U100 sets mask_en0 to “H”. With the operation of the CPU 100 so far, the DREQ0 signal mask circuit 210 is in an operable state.

Next, the DREQ0 signal output from the external request device 240 is input to the timer. At this time, the DMAC 200 outputs the DREQ0 input timing TEQN signal to the CPU 100 without operating the DREQ0 signal mask circuit 210.

CPU 100 that has received the BREQN signal
Outputs a BACKN signal at a certain timing (depending on the specifications of the CPU) ((2) -1 in FIG. 8).
Section). This section is a section in which the DMAC 200 occupies the bus, and in this section, the CPU 100 releases the bus right.

In the section (2) -1 of FIG. 8, the DMAC 200
A DACK0 signal is generated from the BACKN signal and output to the external request device 240. At this time, DACK0
Timing of signal falling (see (3) -1 in Fig. 8)
Then, the mask signal is set to "H". Then, (5)-of FIG.
At the timing of 1, the DREQ0 signal is masked by the mask signal.

Here, referring to FIG. 6 and FIG.
The mask operation of the signal mask circuits 210 and 220 will be described.

In FIG. 6, the CPU 100 sends an initial count value to the counter circuit 211 (in this embodiment,
"5h") is set. At this time, counting is performed only after the DACK signal is input.

The count (decrement) is performed at the rising edge of the sampling clock, and the comparator 212 compares the count data with a predetermined value “0”.
If the count data matches "0", the counter TC signal is output for the period of the sampling clock.

On the other hand, in the mask circuit 213, when the DACK signal is input, the internal mask signal generation circuit 21
4 (FIG. 7) is enabled (active "H"), and the OR signal of the mask signal and the DREQ signal is taken by the OR gate 215 and output as a BREQ signal. In order to disable the mask signal, the counter TC signal is used to disable the mask signal. This mask signal is supplied to the mask signal generation circuit 2
The signal generated in step 14 is "H" by the DACK signal and "L" by the counter TC signal.

Returning to the description of the timing chart of FIG.

The BREQN signal is created by using the DREQ0 signal as an input and the output generated from the mask signal.

The counter of the counter circuit 211 of the DREQ signal mask circuit 210 is decremented in synchronization with the sample clock from the point (3) -1 in FIG. When the counter value becomes "0", a counter TC signal is generated (active "H").

Using the falling edge of the counter TC signal, the mask signal becomes "L" and the mask is disabled (see (4) -1 in FIG. 8). Since the mask signal of the mask circuit 213 becomes "L" when the mask signal becomes "L", the DREQ0 signal passes through the gate as it is and is output. The BREQN signal is output using this output signal (for the timing, see (4) -1 in FIG. 8).

Here, the BAC of (5) -1 to (2) -2 in FIG.
In the section up to the falling edge of the KN signal, B
Since REQN is not output, the CPU 100 has the bus right.

The operation sequence after (4) -1 in FIG. 8 is the same as described above.

As shown in FIG. 8, sections (2) -1, (2)-
2, (2) -3 are sections in which the DMAC 200 owns the bus right, and the other sections are sections in which the CPU 100 owns the bus right.

In the above description, the external request device 240
Has been described, but the same applies to the external request device 241.

Next, DREQ0 / DR of CH0 and CH1
The arbitration of the EQ1 signal will be described.

FIG. 9 is a timing chart for explaining the arbitration operation of the DMAC 200 of the DMA transfer device.
In the figure, the mark を indicates the start of the DMA sequence of CH0, and the mark ● indicates the start of the DMA sequence of CH0.
(2) is a code for explaining the operation timing. The DREQ signal monitoring CH is inside the arbitration circuit 230.

DREQ0 / DR inside DMAC 200
The arbitration of the EQ1 signal is performed by the arbitration circuit 230 on CH0.
DR in the order of → CH1 → CH0 → ... (round robin)
It monitors whether EQ has been input.

Here, DREQ0,
The case where DREQ1 is input will be described as an example.

First, at the point (1) in FIG. 9, when DREQ monitoring is monitoring CH0, DREQ0 / DR
Since EQ1 is input, DREQ0 has priority. The BREQN signal that has received DREQ0 becomes "L" (see the circled portion in FIG. 9).

Next, in the section T3 (see the section (2)), C
At the end of the H0 DMA sequence, the DREQ signal monitor CH indicates CH1, and the DREQ1
Since the signal is enabled, DREQ
The BREQN signal which has received 1 becomes "L" (see the portion ● in FIG. 9). The DMA sequence of CH1 ends in the T5 section.

In the section from T6 to T8, the DREQ signal monitoring C
H is DREQ0 / DRE of CH0 / CH1 every cycle.
It is in a state of monitoring Q1 and waiting for a DREQ signal to be input. At this time, since the mask signal CH0 and the mask signal CH1 are operating, DREQ0 is set at T6.
DREQ1 is masked at T8.

At T9, the mask signal CH1 becomes "L".
, The BREQN signal is enabled (“L”) in the section T10, the DMA sequence of CH1 is performed, and the sequence ends in the section T11.

Further, in the section T12, the mask signal CH
Since 0 becomes “L” and the DREQ monitoring CH indicates “0”, the BREQN signal which has received DREQ0 in the section T13 becomes “L”, and the DMA sequence of CH0 is performed.

As described above, DREQ is monitored by the DREQ monitor CH.
The REQ signal is monitored, and when the validated DREQ signal is the same as the monitored CH, the BREQN signal is set to "L" to start the DMA sequence.

As described above, in the DMA transfer device according to the second embodiment, the DMAC 200 is provided for each channel, and the mask signal mask from the CPU 100 is provided.
_En0, DREQ controlled by mask_en1
Signal masking circuits 210 and 220; and an arbitration circuit 230 for arbitrating the BREQ0 signal and the BREQ1 signal of the DREQ signal masking circuits 210 and 220. Since the bus occupation state is controlled, by masking the DREQ signal of the external request device on the DMAC side (internal),
By periodically generating the DREQ signal, the DMA
Can control the bus occupancy of the system by
It is possible to avoid that the bus is occupied by the MA and the processing of the CPU becomes impossible, thereby preventing the failure of the system.

Further, in the present embodiment, the DREQ signal mask circuits 210 and 220 are mounted inside the DMAC 200. Therefore, when an external request device is newly added, the mask circuit is mounted every time a new device is mounted. This has the effect of preventing an increase in hardware due to the addition of.

The arbitration circuit 23 is provided on the DMAC side (inside).
By mounting the DREQ monitoring CH by 0, there is an effect that it is possible to assign priorities to the DMA transfer channels and evenly distribute the DMA channels.

In this embodiment, the DREQ signal masking circuits 210 and 220 for masking the DREQ signal are provided inside the DMAC 200. However, if these masking circuits 210 and 220 are provided on the DMAC side, The configuration may not always be installed inside the DMAC. Third Embodiment FIG. 10 is a block diagram showing a configuration of a DMA transfer device according to a third embodiment of the present invention. DM according to the present embodiment
In the description of the A transfer device, the same components as those in FIG. 5 are denoted by the same reference numerals.

In FIG. 10, the DMA transfer device has a CP
U100, DMAC300, external request device 3
50, an external request device 351, an external request device 352, and an external memory 113.
The MAC 300 includes a mask circuit 310 with a counter that masks the BREQN signal.

The DMAC 300 has three DMA channels, which are called CH0, CH1, and CH3. Also, CH0, CH1, and CH2 are the external request device 351 and the external request device 3 respectively.
52, connected to the external request device 353.

The DMA channel of the external request device 351 is CH1 and the DMA channel of the external request device 352 is D.
CH2 MA channel, external request device 35
The DMA channel of No. 3 is CH3.

As shown by the broken lines in FIG.
The external request device 351, the external request device 352, the external request device 3
53 to the DMAC 300 from the DMA request signal DREQ1,
DREQ2 and DREQ3 are output, and DMAC3
00 to the external request device 351, the external request device 352, and the external request device 353
MA permission signals DACK1, DACK2, and DACK3 are output.

DMAC 300 outputs a bus release request signal BREQN to CPU 100,
00 indicates a bus release permission signal BA to the DMAC 300.
CKN is output.

The mask_en signal output from the CPU 100 to the DMAC 300 is a signal output from the port of the CPU 100, and is a signal (active “H”) for enabling the counter circuit of the mask circuit with counter 310.

FIG. 11 shows the mask circuit 31 with the counter.
FIG. 3 is a block diagram showing a configuration of a 0.

In FIG. 11, a counter circuit 311 that counts (decrements) at the rising edge of the sampling clock, compares the count data with a predetermined value “0”, and when “0” and the count data match, the number of cycles of the sampling clock is exceeded. Pulse, that is, the counter TC
It comprises a comparator 312 that outputs a signal, and a mask circuit 313 that creates an OR (logical sum) of the BREQ signal and the mask_en mask signal created inside the DMAC 300 to create a BREQN signal.

The counter circuit 311 receives a data bus, a sample clock, and a BACKN signal, and outputs a current count value.

The comparator 312 receives the data of the current count value output from the counter circuit 311 and outputs a counter TC signal.

The mask circuit 313 includes the BREQ signal generated from the DREQ signal inside the DMAC 300 and the CPU 1
00, a counter TC signal from the comparator 312, and a BREQN signal
Output a signal.

FIG. 12 is a diagram showing a detailed configuration inside mask circuit 313 of FIG.

In FIG. 12, a masking circuit 313 includes a masking signal generating circuit 314 for outputting a masking signal that enables a masking signal generated internally when a BACKN signal is input based on a counter TC signal, and a generating circuit. And an OR gate 315 that performs OR logic of the mask signal and the BREQ signal.

FIG. 13 shows the DMA request signals DREQ1 and DREQ1.
FIG. 9 is a diagram showing a configuration from DREQ2, DREQ3 to BREQN signal generation.

In FIG. 13, reference numerals 316 denote DREQ1 and DRE from the external request device 351, the external request device 352, and the external request device 353.
A DREQ signal arbitration circuit that arbitrates the Q2 and DREQ3 signals and outputs the BREQ signal created inside the DMAC 300.

The BREQ signal generated by the DREQ signal arbitration circuit 316 is supplied to the mask circuit 313 (FIG. 11 and FIG. 1).
2), and the mask circuit 313 outputs a BREQN signal.

Here, the mask circuit with mask counter 310 of the present embodiment determines the mask time by providing a hardware counter (timer), similarly to the DREQ signal mask circuits 210 and 220 of the second embodiment. Take the way.
However, a method of determining a mask time by providing a hardware counter (timer) as in the second embodiment is also possible, and a mask time is determined by using a CPU port using a timer interrupt of the CPU itself. Can also be controlled.

In the present embodiment, the value of the counter of the counter circuit 311 in the mask circuit 310 with a mask counter is set so that the mask time is selected (selected according to the number of external request devices). Data is set in this counter so that a predetermined mask time is reached. This can also be realized by using a timer interrupt of the CPU itself.

The operation of the above-configured DMA transfer device will be described below.

First, the operation of the mask circuit with counter 310 will be described.

As shown in FIG. 11, the CPU 100 sets an initial value to be counted in the counter circuit 311 ("5h" is set in this embodiment). Next, BAC
When the KN signal is input, counting (decrement) is performed at the rising edge of the sample clock. Next, the comparator 312 compares the current count value with “0”, and outputs a pulse for one cycle of the sample clock when they match.

On the other hand, in the mask circuit 313, FIG.
As shown in FIG. 2, the internal mask signal is enabled (active “H”) by the BACKN signal, and the DMAC 3
00, the output of the OR gate 315 of the BREQ signal generated from DREQ and the internal mask signal is output as BREQN. Here, the internal mask signal is BACK
Enable (active "H") by N signal, disable (active "L") by counter TC signal
This is the signal.

Further, as shown in FIG.
The n signal is a signal input from the CPU 100 to the DMAC 300, and is controlled by a port of the CPU 100. The mask_en signal is a signal for controlling whether to enable or disable the entire mask circuit with a mask counter 310. When the BREQ is output without using the mask circuit with a mask counter 310, the mask_en signal is used.
U100 is controlled to be disabled ("L").

FIG. 14 is a timing chart for explaining the operation of the DMA transfer device. The numbers in the figure
Reference numerals (1) to (4) denote operation timings or operation sections.

In the timing chart of FIG.
The REQ1, DREQ2, and DREQ3 signals are (2) in FIG.
At the same time. The priority of the DMA request of each CH (CH1, CH2, CH3) is a round robin method such as CH1 → CH2 → CH3 → CH1.

A case where the counter value of the mask circuit with counter 310 is set to “5” will be described as an example.

The count value "5" is set at the timing (1) in FIG.

Next, at timing (2) in FIG. 14, three DREQs (DREQ1, DREQ2, DREQ3) are simultaneously enabled. Here, the section (2) -1 in FIG. 14 is a section in which DMA of CH1 is being executed.

Next, the timing (B) of (3) -1 in FIG.
The mask signal is enabled at the rising edge of the ACKN signal), and the BREQ signal is masked. The counting is also started at the point (3) -1, that is, at the timing when the BACKN signal becomes “H”. The mask circuit for the BREQ signal is the mask circuit 313 in FIG.
The BREQ signal in C300 is masked by the mask signal of mask circuit 313.

Next, at the timing of (4) -1 in FIG. 14, the counter value becomes "0", the mask signal becomes "L" (disable), the mask is released, and the BREQN signal is output to the outside of the DMAC 300. Is done. In the section (2) -2 in FIG. 14, the DMA transfer of CH2 is performed.

Next, the timing (B) of (3) -2 in FIG.
At the rising edge of the ACKN signal), the mask signal is enabled and the BREQN signal is masked. This mask operation is performed by the mask circuit 313 shown in FIG.

Next, at the timing of (4) -2 in FIG. 14, the counter becomes "0", the mask signal becomes "L" (disable), the mask is released, and the BREQN signal becomes D.
Output to the outside of the MAC 300.

In this way, the period in which BREQN is generated is adjusted by masking the BREQN signal.

As described above, in the DMA transfer device according to the third embodiment, the DMAC 300 includes the mask circuit 310 with a counter for masking the BREQN signal.
Since the mask circuit with counter 310 masks the BREQN signal and controls the bus occupation state by the DMA transfer, the same effect as in the first and second embodiments can be obtained.

In particular, according to this embodiment, the DR output from the external request device as in the second embodiment
Instead of masking the EQ signal, the DMAC 300 masks the BREQN signal. This makes it possible to reduce the number of mask circuits to one, rather than to add a mask circuit for each CH as in the second embodiment, and to reduce the hardware size compared to the second embodiment. There is an effect that can be done.

Since the BREQN signal is masked,
Even when DREQ signals from a plurality of external request devices are frequently overlapped, it is possible to control the BREQN signal to be output periodically, and the DMAC 3
00 has the effect of making the bus occupancy constant. Fourth Embodiment FIG. 15 is a block diagram illustrating a configuration of a DMA transfer device according to a fourth embodiment of the present invention. DM according to the present embodiment
In the description of the A transfer device, the same components as those in FIG. 5 are denoted by the same reference numerals.

In FIG. 15, the DMA transfer device has a CP
U100, DMAC400, a plurality of external request devices (451, 452, 453,..., N-1, N), and an external memory 113.

The DMAC 400 is equipped with a plurality of DMA channels, and these are assigned to CH1, CH2, CH3,
..., CHN-1, CHN. Also, CH1, CH
, CHN-1, and CHN are the corresponding external request devices (451, 452, and 45, respectively).
3,..., N-1, N).

The DMAC 400 has CH1, CH2, CH
, CHN-1, CHN-1, and a plurality of DREQ signal mask circuits 410,..., And an arbitration circuit 230 for arbitrating the BREQ signals of the DREQ signal mask circuits 410,.

External request device 451, external request device 452, external request device 453
Respectively output DREQ signals DREQ1 and DR
EQ2 and DREQ3, and DACK signals corresponding to the request signals are DACK1, DACK2 and DACK, respectively.
ACK3. At this time, the external request device (N-1) and the external request device (N) are DMAC in the sense that there are a plurality of external request devices.
400 indicates the number of external request devices that can be supported. The external memory 113 is a memory of the DMA system, and also serves as a source device and a destination device of the DMA system.

In the DMAC 400, a mask circuit with a mask counter (DREQ signal mask circuit) incorporating a mask counter and a mask circuit is mounted for each channel. This mask circuit has a circuit configuration similar to that of FIG. 2 and FIG. 3 described above.
U100 sets a counter value corresponding to the mask time.

The DRPQ signal arbitration circuit 230 inside the DMAC 400 outputs the DREQ signal output from each channel.
It arbitrates the signal and outputs a BREQN signal to CPU 100. The arbitration method is the same as in the second embodiment,
Which DMA sequence is to be performed is determined based on the input sequence of the DREQ signal and the DREQ signal monitoring CH (see the operation description in FIG. 9).

The DMAC 400 outputs a BREQN signal (bus release request signal: a signal requesting release of the bus right to the CPU / active "L") to the CPU 100.
To the BACKN signal (bus release permission signal: external DM
A signal indicating that the release of the bus right is permitted / active "L") is output to the AC.

Hereinafter, the operation of the DMA transfer device configured as described above will be described.

FIG. 16 is a timing chart for explaining the operation of the DMA transfer device. The numbers in the figure
Reference numerals (1) to (12) denote operation timings or operation sections.

External request device 451, external request device 452, external request device 453
, DREQ1, DREQ2, and DREQ3 signals are simultaneously transmitted at arbitrary timings (points (1) and (7) in FIG. 16).
Will be described.

[0143] The CPU 100
0 sets a mask time for a mask timer (Ch1 to ChN) inside. The set values are the values shown in FIG.
In the case of this embodiment, the number of external request devices is 3
Therefore, the mask time is set to 2 μs from the table shown in FIG.

The DMAC 400 enables DMA of only one channel at an arbitrary timing.
Ch1, Ch2,..., C
Valid in the order of hN.

In the timing chart of FIG.
BREQN is “L” upon receiving DREQ1 at points (1) and (7)
And the DMA sequence is started. After the end of this DMA sequence, the MASK1 signal is enabled at points (2) and (8). Since the setting of the mask time is 2 μs, the mask is masked for 2 μs.

Next, at timings (3) and (9) in FIG.
Upon receiving REQ2, BREQN becomes “L” and DMA
The sequence starts. The DMA sequence ends at the timings (4) and (10) in FIG. 16, but the masking starts at this timing. Again, the mask time is 2
Because of the μs setting, the mask is performed for 2 μs.

Similarly, the DREQ 3 is received at the timings of the points (5) and (11) in FIG. 16 to start the DMA sequence, and the DMA sequence ends at the points (6) and (12) and the mask starts. Is done. In this series of flows, a section where DMA is not performed exists between the point (6) and the point (13). In this section, the CPU 100 performs processing according to the program of the system. be able to. This section is a section that does not exist without the DREQ mask. This section is DREQ1, DREQ2, DREQ
3 and the number of mounted external request devices.

As described above, the DMA transfer device according to the fourth embodiment includes the C
A plurality of DREQ signal mask circuits 410 installed corresponding to H1, CH2, CH3,.
, And an arbitration circuit 230 for arbitrating the BREQ signal of the DREQ signal mask circuits 410,..., And a plurality of DREQ signal mask circuits 410,.
However, since the mask time is controlled by the CPU 100 in accordance with the number of request devices that operate simultaneously externally, the opportunity of DMA transfer of each DMA channel can be given evenly in time. Mediation is possible.

That is, when a plurality of operable external request devices are present on the same bus, the time for which the DMAC 400 occupies the bus naturally increases as a system. That is, the bus occupancy by the DMAC 400 increases. In the present embodiment, the average DMAC bus occupancy can be controlled by controlling the mask time of the DREQ signal by the number of external request devices that operate simultaneously. There is an effect that a remarkable increase in the bus occupancy of the DMAC 400 in the system can be prevented.

In the present embodiment, an example is shown in which the method of the second embodiment is used as the bus occupancy control method of the DMAC 400. However, the operation is possible as shown in the method of the first embodiment. The control on the external request device side can also be performed by the method of the third embodiment.
It can also be realized by controlling REQ. Fifth Embodiment FIG. 18 is a block diagram showing a configuration of a DMA transfer device according to a fifth embodiment of the present invention. DM according to the present embodiment
In the description of the A transfer device, the same components as those in FIG. 15 are denoted by the same reference numerals.

In FIG. 18, the DMA transfer device has a CP
U500, DMAC400, a plurality of external request devices (451, 452, 453,..., N-1, N), and an external memory 113.

The program of the CPU 500 includes a task management function 510 for managing a processing task of the program.
(Management means).

The DMAC 400 is equipped with a plurality of DMA channels, and these are used as CH1, CH2, CH3,
..., CHN-1, CHN. Also, CH1, CH
, CHN-1, and CHN are the corresponding external request devices (451, 452, and 45, respectively).
3,..., N-1, N).

The DMAC 400 has CH1, CH2, CH
, CHN-1, CHN-1, and a plurality of DREQ signal mask circuits 410,..., And an arbitration circuit 230 for arbitrating the BREQ signals of the DREQ signal mask circuits 410,.

External request device 451, external request device 452, external request device 453
Respectively output DREQ signals DREQ1 and DR
EQ2 and DREQ3, and DACK signals corresponding to the request signals are DACK1, DACK2 and DACK, respectively.
ACK3. At this time, the external request device (N-1) and the external request device (N) are DMAC in the sense that there are a plurality of external request devices.
400 indicates the number of external request devices that can be supported. The external memory 113 is a memory of the DMA system, and also serves as a source device and a destination device of the DMA system.

Also, mas output from CPU 500
k_en1, mask_en2, and mask_en3 are signals for enabling the masks of the DREQ signal mask circuits 410,... (DREQ signal mask circuits CH1, CH2, CH3), respectively. The control is performed by the CPU 500 itself through port control.

The DRPQ signal arbitration circuit 230 in the DMAC 400 arbitrates the DREQ signal of each channel (CH1 / 2/3...) And sends the BREQN signal to the CPU 500.
Output to The arbitration method is the same as in the second embodiment.

A BREQN signal (bus release request signal: active “L”) is output from the DMAC 400 to the CPU 500. In response to the BREQN signal, the CPU 500 sends a BA signal to the DMAC 400.
The CKN signal (bus release permission signal: active "L") is output.

The operation of the thus configured DMA transfer device will be described below.

[0160] The CPU 500 normally performs processing in accordance with a program.
Are different in processing load. The task management function 510 provided inside the CPU 500 has a function of constantly monitoring what task is currently being processed and retaining the information. This task management function 510 is realized by software.

First, task names T1 to T1 on the program
FIG. 19 shows the relationship between 0 and its processing load and the corresponding mask time.
Is shown in the table.

As shown in FIG. 19, the CPU 500 is a program for processing tasks in the order of T1, T2, T3,..., T10, T1,.

Hereinafter, a case where the enable interval of DREQ1 is 1 μs when DREQ1 is continuously generated will be described as an example.

FIG. 20 is a timing chart for explaining the operation of the DMA transfer device.

First, as shown in FIG. 20, while the task T1 is being processed, the mask time is set to 1 μs (see the table in FIG. 19). At this time, if the DREQ1 signal is enabled, the DREQ1 signal is always masked by the mask inside the DMAC 400 for 1 μs,
A transfer is performed. In this case, the mask setting time is 1 μs
However, since the enable interval of DREQ1 is 1 μs, there is no effect even if the mask timer is valid.

Next, a description will be given of a state where the task T2 is being processed. At this time, the mask time is set to 2 μs (see the table in FIG. 19). At this time, DRE
When the Q1 signal is enabled, the DRE must be 2 μs.
The Q1 signal is masked by the DREQ signal mask circuit 410 inside the DMAC 400, and DMA transfer is performed. In this case, since the enable interval of DREQ is 1 μs, whereas the mask setting time is 2 μs, the effect of the mask can be obtained 1 μs.

Similarly, in the case of the task T3, the mask effect appears for 2 μs, and in the case of the task T4, the mask effect appears for 3 μs.

The above operation is performed for each channel. Also,
The arbitration operation of each channel is the same as in the second embodiment.

As described above, in the DMA transfer device according to the fifth embodiment, the CPU 500 has the task management function 510 for managing the processing task of the program, and
Since the mask time is controlled in accordance with the processing load of U, the following effects can be obtained.

That is, if the CPU processing (task) is complicated and there are many tasks in the system which must be completed within a predetermined time, the DMAC
The BREQ signal output from the CPU may make the CPU processing inefficient in time. At this time, by performing the masking operation of the DREQ signal for each task as in the present embodiment, it is possible to complete the CPU processing within a predetermined time, and the temporal processing capability of the CPU on the system This has the effect of preventing a decrease in

In this embodiment, the operation of the DMAC is controlled by the method of the second embodiment. However, as shown in the first embodiment, the operation of the DMAC is controlled by the external request device, As shown in the embodiment, the DMAC
It can also be realized by a method of controlling the internal BREQ signal. Sixth Embodiment FIG. 21 is a block diagram illustrating a configuration of a DMA transfer device according to a sixth embodiment of the present invention. DM according to the present embodiment
In the description of the A transfer device, the same components as those in FIG. 5 are denoted by the same reference numerals.

In FIG. 21, the DMA transfer device has a CP
U100, DMAC600, external request device 6
50 and an external memory 113.
0 is a DREQ signal mask circuit 610 (mask means)
And a DREQ cycle detection circuit 620 (DREQ cycle detection means) for detecting a generation cycle of the DREQ signal.

[0173] DMA from external request device 650
The DREQ signal is output to C600, and the DACK signal is output from DMAC 600 to external request device 650.

BRE from DMAC 600 to CPU 100
The Q signal is output, and a BACK signal is output from the CPU 100 to the DMAC 600.

The external memory 113 is a source device (or a destination device) for DMA transfer.

Mask_e output from CPU 100
The n signal is a signal that enables the DREQ signal mask circuit 610.

The CPU 100 sets the mask signal mask
_En to the DREQ signal mask circuit 610 to output DR
The EQ signal mask circuit 610 is controlled.

FIG. 22 shows the DREQ cycle detection circuit 620.
FIG. 3 is a diagram showing a circuit configuration of FIG.

In FIG. 22, DREQ cycle detection circuit 6
Reference numeral 20 denotes an edge detection circuit 621 which receives a DREQ signal and logically detects an edge of the DREQ signal, a counter 622 which counts (decrements) at a rising edge of a sampling clock, and a data buffer 623 which stores count data. You.

The data buffer 623 has a counter 623
Is a buffer for storing data so that the CPU 100 (FIG. 21) can read the result of (1).

The operation of the above-configured DMA transfer device will be described below.

FIG. 23 is a timing chart showing the operation of DREQ cycle detection circuit 620.

First, the DREC signal is input from the external request device 650 to the DMAC 600, and the input signal is input to the internal DREQ cycle detection circuit 620.

In the internal circuit of DREQ cycle detection circuit 620, as shown in the timing chart of FIG.
The edge detector 621 detects the rising edge of the DREQ signal, and the detected pulse is used as a trigger to trigger the counter 6
22 starts counting. This count is the next DRE
Count up to the edge of the Q signal.

The count data counted by the counter 622 is transferred to the data buffer 623, and after the count is completed, the data buffer 623 holds the data.

FIG. 24 is a timing chart for explaining the operation of the DMA transfer device.

The CPU 100 reads out the count data of the data buffer 623 at an arbitrary timing, and performs an operation of enabling / disabling the mask_en signal by a port of the CPU according to the data. That is, if the read count data is small, the CPU 100 increases the time in which the mask_en signal is enabled.

As shown in FIG. 24, when the mask_en signal is enabled, the DREQ signal is kept for a certain period (section).
After being masked and unmasked, the mask_en signal is disabled and becomes a BREQ signal to be output to the CPU 100.

CPU 100 receiving BREQ signal
Outputs a BACK signal to notify that the bus right has been released.

As shown in FIG. 24, the interval in which the BREQ signal is generated is shorter in the period in which the mask_en signal is disabled, but the interval in which the mask_en signal is enabled is shorter than that in the period in which the BREQ signal is disabled. You can see that it is getting longer. This section (section in which the mask effect is generated) is a section in which the CPU 100 performs processing according to the program.

As described above, in the DMA transfer apparatus according to the sixth embodiment, the DMAC 600 includes the DREQ signal mask circuit 610 and the DREQ cycle detection circuit 620 for detecting the generation cycle of the DREQ signal. Since the detection circuit 620 detects the generation cycle of the input DREQ signal and masks the DREQ signal by using the counter data value, the DMA cycle (interval) can be extended, and the DMAC 600 Has the effect of reducing the bus occupancy in the system.

Further, if this method is used, the speed of the DMA transfer can be controlled by the CPU 100. Therefore, an I / O device (external request device) whose DREQ signal generation cycle varies exists on the bus. In this case, the BREQ signal is generated at the same cycle, and the bus occupancy is reduced.

In this embodiment, the operation of the DMAC is controlled by the method of the second embodiment. However, as shown in the method of the first embodiment, the operable external request device controls the DMAC. This can also be realized by a method of controlling the BREQ inside the DMAC as shown in the method of the third embodiment. Seventh Embodiment FIG. 25 is a block diagram showing a configuration of a DMA transfer device according to a seventh embodiment of the present invention. DM according to the present embodiment
In the description of the A transfer device, the same components as those in FIG. 21 are denoted by the same reference numerals.

Referring to FIG. 25, the DMA transfer device
U100, DMAC700, external request device 7
51, external request device 752 and external memory 1
The DMAC 700 comprises a BREQN signal masking circuit 720 (masking means) and a BREQN cycle detecting circuit 720 (BREQN) for detecting the generation cycle of the BREQN signal generated in response to the DREQ signals of a plurality of external request devices that permit the operation. Period detecting means).

The DMAC 700 has a plurality of (two) DMs.
A channel is installed, and those are CH1, CH2
And Further, CH1 and CH2 are connected to an external request device 751 and an external request device 752, respectively.

The DMA channel of the external request device 751 is set to CH1, and the DMA channel of the external request device 752 is set to D1.
Let the MA channel be CH2.

As shown by the broken lines in FIG.
The DMAC 700 outputs DMA request signals DREQ1 and DREQ2 (active “H”) to the DMAC 700 from the external request device 751 and the external request device 752 for each of the external request devices 751 and 752. DMA permission signals DACK1 and DACK2 are output.

The DMAC 700 outputs a bus release request signal BREQN (active "L") to the CPU 100, and the CPU 100 outputs a bus release permission signal BACKN (active "L") to the DMAC 700.

The mask_en signal output from the CPU 100 to the DMAC 700 is a signal output from the port of the CPU 100, and is output from the BREQN mask circuit 7
This is a signal (active “H”) for enabling the 20 counter circuits.

FIG. 26 is a diagram showing a circuit configuration of the BREQN signal cycle detection circuit 720.

Referring to FIG. 26, a BREQN signal cycle detecting circuit 720 receives an BREQN signal and logically detects an edge of the BREQN signal.
The counter 722 counts (decrements) at the rising edge of the sampling clock, and the data buffer 723 stores count data.

A count pulse is output from the edge detection circuit 721 to the counter, and the count data is transferred from the counter 722 to the data buffer 723.

The data buffer 723 includes a counter 723
Is a buffer for storing data so that the CPU 100 (FIG. 25) can read the result of (1).

Hereinafter, the operation of the DMA transfer device configured as described above will be described.

FIG. 27 shows a BREQN signal cycle detection circuit 72.
FIG. 28 is a timing chart showing the operation of D.
5 is a timing chart for explaining the operation of the MA transfer device.

First, in this embodiment, the priority of the DMA transfer of CH1 and CH2 is CH1 → CH2 → CH1 → C
A round robin type that performs a round like H2 is taken. At the same time, DREQ (request signal) is
, The priority is given to CH1. In other cases, the priority is given to the one in which the DREQ (request signal) comes earlier in time.

DREQ1 and DREQ2 are simultaneously set in FIG.
Let's take the case where it is active at point (1) as an example.
At this time, the DMA of CH1 is performed.

Next, at the point (2) in FIG.
MA is performed. At this time, the BRE of (1) and (2) of FIG.
At the falling edge of the QN signal, the BREQ signal shown in FIG.
The N signal period detection circuit 720 operates, and the counter 722 operates. Then, as shown in the timing chart of FIG. 27, the count data is transferred to the data buffer 723.

At the point (3) in FIG. 28, the DM of CH1 is
A is performed, but also at this time, the BREQN signal period detection circuit 720 counts between the edges of the BREQN in (2) and (3) of FIG. The count data at this time is also overwritten in the data buffer 723.

When the DMA transfer of (3) in FIG. 28 is completed, the CPU 100 reads the data in the data buffer 723. With this read value, the BRE of DMAC700
The CPU 100 can recognize the generation cycle of the QN signal.

Next, point (4) -1 in FIG.
When the ACKN signal becomes “H”, the CPU 100
Sets the mask_en1 signal to “H”. mask_
When en1 is set to "H", the BREQN signal is masked, and even if DREQ1 and DREQ2 are input, the BREQN signal is not output to the outside (see the section in FIG. 28 where the mask effect is obtained).

The same applies to points (4) -2 and (4) -3 in FIG.

[0213] The CPU 100 sets the mask_en1 to "H".
Is controlled based on the value of the generation cycle of the previously read BREQ signal. For example, the data buffer 723
If the value read from is extremely short, mas
The time during which k_en1 is kept at “H” is increased, and DMA
If the bus occupancy by C100 is reduced and, conversely, the value read from the data buffer 723 is extremely long, it is possible to control the time for which the mask_en1 signal is set to "H" to be shorter.

As described above, the generation cycle of BREQ is determined by the CPU.
The CPU 100 can control the bus occupancy of the device by the DMAC 700 by the recognition by the CPU 100.

As described above, in the DMA transfer device according to the seventh embodiment, in the DMAC 700, the DMAC 700 includes the BREQN signal mask circuit 720 and the BREQ signal generated in accordance with the DREQ signals of a plurality of external request devices permitted to operate.
BREQN cycle detection circuit 7 for detecting the generation cycle of N signal
20. The BREQN signal cycle detection circuit 720 includes:
An edge detection circuit 721 that inputs a BREQN signal and logically detects an edge of the BREQN signal, and counts (decrements) at a rising edge of a sampling clock.
And the data buffer 723 for storing count data, the generation cycle (generation interval) of the BREQN signal is counted using the edge of the BREQN signal, and the count data is held in the data buffer 723. In this case, the CPU 100
The generation cycle of the BREQ input from the AC 700 can be recognized.
It is possible to control the bus occupancy by the AC 700.

Further, as in the sixth embodiment, the DR for detecting the generation cycle of DREQ for each CH (channel) is used.
When the EQ cycle detection circuit 620 is mounted, when a large number of external request devices are mounted, it is necessary to newly add a counter and a data buffer constituting the DREQ cycle detection circuit for each CH. According to the present embodiment, the BRE
Since the BREQN cycle detection circuit 720 is provided for the QN signal, even if a large number of external request devices are mounted, only one counter or data buffer is required to configure the BREQN cycle detection circuit. This has the effect of reducing the size of the device.

In the present embodiment, the operation of the DMAC is controlled by the method of the third embodiment.
Even with the control by U, it is also possible to provide a hardware timer in the mask circuit and perform the masking with hardware. Also,
The control can be performed on the operable external request device side as shown in the method of the first embodiment, or the DMAC side can be controlled as shown in the method of the second embodiment. Eighth Embodiment FIG. 29 is a block diagram showing a configuration of a DMA transfer device according to an eighth embodiment of the present invention. DM according to the present embodiment
In the description of the A transfer device, the same components as those in FIGS. 18 and 21 are denoted by the same reference numerals.

In FIG. 29, the DMA transfer device
U800 (setting means), DMAC 600, external request device 650 and external memory 113,
The DMAC 600 includes a DREQ signal mask circuit 610,
And a DREQ cycle detection circuit 620.

The program of the CPU 800 includes a task management function 810 for managing a processing task of the program.
(Management means). This task management function 8
10 is realized by software.

The DMAC 600 receives the DREQ signal from the external request device 650, and masks the DREQ signal for the period of the mask_en signal to output the BREQN signal to the CPU 800 when masking is enabled. BA when CPU 800 releases the bus right
The CKN signal is output to DMAC 600.

Upon receiving the BACKN signal, DMAC 60
0 is the DAC to the external request device 650
Outputs K signal.

The DREQ cycle detection circuit 620 has the same circuit configuration as that of the sixth embodiment shown in FIG.

Hereinafter, the operation of the DMA transfer device configured as described above will be described.

First, the bus load factor of the entire system is defined. For simplicity, in the present embodiment, the bus load factor of the entire system is set to 12% or less. Further, the DREQ signal generation interval of the external request device 650 is set to 5 μs.
It is assumed that the bus occupancy of one DMA transfer is 10%. As a result, the time for occupying the bus in the DMA becomes 500 ns.

First, task names T1 to T1 on the program
FIG. 30 shows the relationship between 0, the processing load, the mask time corresponding to the processing load, and the load factor of the DMAC.

As shown in FIG. 30, the present embodiment is a system for processing using tasks T1 to T10, in which T1, T3, T5 and T7 are arranged in the order shown in the timing chart of FIG. Consider the case where task processing is performed.

FIG. 31 is a timing chart for explaining the operation of the DMA transfer device.

First, the DREQ signal is input in the section of task T1. In this case, when calculated from the table in FIG. 30, the total bus occupancy is 11%, and the occupancy 12
% Will not be exceeded. Therefore, since there is no need to operate the mask circuit, the mask_en signal remains disabled and there is no problem. Therefore, the BREQ signal is generated in the same cycle as the DREQ signal.

Next, when the DREQ signal is generated in the section of the task T3, it becomes 13% when calculated from the table in FIG. 30 and the bus occupancy of the DMA. Since the bus occupancy of this embodiment is 12% or less, a problem occurs. To prevent this from occurring, the CPU 800 controls the mask_en signal to be output at the timing shown in FIG. 31 when the process enters the task T3. At this time, the DREQ signal is masked by the mask_en signal and output to the CPU 800 as a BREQ signal. In response to the BREQ signal, the CPU 800 outputs a BACK signal to release the bus right. The DMA transfer sequence is executed by such exchange.

Next, the case where the DREQ signal is input in the section of task T5 will be described.

In this case, when the bus occupancy is calculated in the same manner as in the case of the task T3, it becomes 15%. Since this also does not satisfy the bus occupancy of 12% or less in the present embodiment, the mask time is set using the table of FIG. 30 to satisfy this condition.

According to this table, in the case of T5, mask_
The time during which en is enabled is 2.14 μs + 5 μs, and the bus occupancy is 12% or less. The CPU 800 controls the mask_en so as to satisfy the mask time at this time.

Similarly, in the case of the task T7, the mask time is set from the table of FIG. 30, the mask_en time is determined so that the bus occupancy set in this embodiment is 12% or less, and the mask time is satisfied. CPU 800 is ma
sk_en is controlled.

As described above, in the DMA transfer device according to the eighth embodiment, the CPU 800 is provided with the task management function 810 for managing the processing task of the program.
Since the mask time is controlled while maintaining the bus load of the predetermined system according to the processing load of U, the bus occupancy when each task is operating is calculated in advance, and the calculation is performed. By setting the limit value of the bus occupancy of the entire system from the value, it becomes possible to perform the CPU processing at a value that is effective and the DMA cycle does not exceed the upper limit of the bus occupancy, and it has been calculated in advance. This has the effect of reliably reducing the bus occupancy to the value of the bus occupancy.

In the present embodiment, the DMAC is controlled by the method of the second embodiment. However, as shown in the method of the first embodiment, the operable external request device controls the DMAC. This can also be realized by controlling the BREQ signal inside the DMAC by the method of the third embodiment.

The mask time can be controlled by the CPU, or the mask circuit can be provided with a hardware-based timer.
It is also possible to realize by setting the time of the timer from U.

Therefore, the DM having such features is
An A-transfer device is used in a PC (personal computer) peripheral device such as a printer, for example, when the data transfer speed from the PC and the data processing speed of the peripheral device themselves need to be high-speed processing. Moreover, in a system where it is essential to avoid a failure of the system, it is effective when it is desired to perform data transfer and CPU processing uniformly over time. In addition, DMA with a focus on the CPU
It can be used in all systems, including data transfer by.

In each of the above embodiments, the mask circuit and the like are provided in the external request device or DMAC. However, this is an example, and the mask circuit and the like may be provided externally. The DMAC has a dedicated D
An MA controller or a general-purpose DMA controller may be used. In particular, when high speed is required, the controller may be configured using individual components such as a counter and a buffer.

Further, it goes without saying that the types and numbers of the registers, counters, various control circuits, and the like constituting the DMA transfer device are not limited to those in the above-described embodiment.

[0240]

In the DMA transfer device according to the present invention, the external request device or the DMA control unit includes a masking means for masking the DREQ signal, and the masking means controls the DREQ signal.
Since the bus occupation state by DMA transfer is controlled by masking the REQ signal, when there are a plurality of external request devices, or when there is an external request device with a short DREQ signal generation cycle on the same bus , DMA occupancy can be reduced, and the bus can be used effectively over time.

[Brief description of the drawings]

FIG. 1 shows a DMA according to a first embodiment to which the present invention is applied.
FIG. 2 is a block diagram illustrating a configuration of a transfer device.

FIG. 2 is a circuit diagram showing a configuration of a DREQ signal mask circuit of the DMA transfer device.

FIG. 3 is a circuit diagram showing a configuration of a DREQ signal mask circuit of the DMA transfer device.

FIG. 4 is a timing chart showing a DMA transfer operation of the DMA transfer device.

FIG. 5 shows a DMA according to a second embodiment to which the present invention is applied.
FIG. 2 is a block diagram illustrating a configuration of a transfer device.

FIG. 6 is a block diagram showing a configuration of a DREQ signal mask circuit of the DMA transfer device.

FIG. 7 is a diagram showing a detailed configuration inside a mask circuit of the DMA transfer device.

FIG. 8 is a timing chart for explaining the operation of the DMA transfer device.

FIG. 9 is a timing chart for explaining the arbitration operation of the DMAC of the DMA transfer device.

FIG. 10 shows a DM according to a third embodiment to which the present invention is applied.
FIG. 2 is a block diagram illustrating a configuration of an A transfer device.

FIG. 11 is a block diagram showing a configuration of a mask circuit with a counter of the DMA transfer device.

FIG. 12 is a diagram showing a detailed configuration inside a mask circuit of the DMA transfer device.

FIG. 13 shows a DMA request signal DRE of the DMA transfer device.
FIG. 9 is a diagram showing a configuration from Q1, DREQ2, DREQ3 to generation of a BREQN signal.

FIG. 14 is a timing chart for explaining the operation of the DMA transfer device.

FIG. 15 shows a DM according to a fourth embodiment to which the present invention is applied.
FIG. 2 is a block diagram illustrating a configuration of an A transfer device.

FIG. 16 is a timing chart for explaining the operation of the DMA transfer device.

FIG. 17 is a diagram showing a table of setting a mask time of the DMA transfer device.

FIG. 18 shows a DM according to a fifth embodiment to which the present invention is applied.
FIG. 2 is a block diagram illustrating a configuration of an A transfer device.

FIG. 19 is a diagram showing a table of a relationship between a task name on a program of the DMA transfer device, its processing load, and a corresponding mask time.

FIG. 20 is a timing chart for explaining the operation of the DMA transfer device.

FIG. 21 shows a DM according to a sixth embodiment to which the present invention is applied.
FIG. 2 is a block diagram illustrating a configuration of an A transfer device.

FIG. 22 is a diagram showing a circuit configuration of a DREQ cycle detection circuit of the DMA transfer device.

FIG. 23 is a timing chart showing the operation of the DREQ cycle detection circuit of the DMA transfer device.

FIG. 24 is a timing chart for explaining the operation of the DMA transfer device.

FIG. 25 shows a DM according to a seventh embodiment to which the present invention is applied.
FIG. 2 is a block diagram illustrating a configuration of an A transfer device.

FIG. 26 is a diagram showing a circuit configuration of a BREQN signal cycle detection circuit of the DMA transfer device.

FIG. 27 is a timing chart showing the operation of the BREQN signal cycle detection circuit of the DMA transfer device.

FIG. 28 is a timing chart for explaining the operation of the DMA transfer device.

FIG. 29 shows a DM according to an eighth embodiment to which the present invention is applied.
FIG. 2 is a block diagram illustrating a configuration of an A transfer device.

FIG. 30 is a diagram showing a table of a relationship between a task name on a program of the DMA transfer device, its processing load, and a corresponding mask time.

FIG. 31 is a timing chart for explaining the operation of the DMA transfer device.

FIG. 32 is a block diagram illustrating a configuration of a conventional DMA transfer device.

FIG. 33 is a timing chart conceptually showing arbitration timing of a conventional DMAC.

[Explanation of symbols]

100, 500, 800 CPU, 110, 200, 3
00, 400, 600, 700 DMAC (DMA control unit), 111, 112, 240, 241, 351, 35
2,353,451,452,453,751,752
External request device, 113 External memory, 12
1,122,210,220,410,610 DRE
Q signal mask circuit (mask means), 131 AND gate, 132 OR gate, 230 arbitration circuit, 211,
311 counter circuit, 212, 312 comparator, 21
3,313 mask circuit, 214 mask signal generation circuit, 215, 315 OR gate, 310 mask circuit with counter (mask means), 316 DREQ signal arbitration circuit, 313 BREQ signal mask circuit, 314 mask signal generation circuit, 510, 810 tasks Management function (management means), 620 DREQ cycle detection circuit (DREQ cycle detection means), 621, 721 edge detection circuit, 62
2,722 counter, 623,723 data buffer, 710BREQN signal masking circuit (masking means),
720 BREQN cycle detection circuit (BREQN cycle detection means)

Claims (8)

[Claims] 1. A DMA control unit for performing a DMA transfer control for directly transferring data between a memory and an external request device independently of an operation of a CPU, wherein the DMA control unit receives a data transfer request (hereinafter, referred to as a “data transfer request”) from the external request device. When a DREQ signal is generated, a bus request (hereinafter, BREQ) is sent to the CPU.
N) to request the release of the bus,
Sends a data transfer request acknowledgment (DACK) signal to an external request device when a bus release permission (BACKN) signal is returned from the device, and a DMA transfer device for controlling data transfer between the memory and the external request device In the above, the external request device may include mask means for masking the DREQ signal, and mask the DREQ signal by the mask means.
A DMA transfer device for controlling a bus occupation state by MA transfer. 2. A DMA control unit for performing a DMA transfer control for directly transferring data between a memory and an external request device, independently of an operation of the CPU, wherein the DMA control unit receives a DREQ from the external request device.
When a signal is generated, a BREQN signal is output to the CPU to request the release of the bus. When the BACKN signal is returned from the CPU, a DACK signal is sent to the external request device, and data between the memory and the external request device is transmitted. In a DMA transfer device that performs transfer control, the DMA control unit includes a masking unit that masks the DREQ signal, and masks the DREQ signal with the masking unit.
A DMA transfer device for controlling a bus occupation state by MA transfer. 3. A DMA control unit for performing a DMA transfer control for directly transferring data between a memory and an external request device, independently of an operation of the CPU, wherein the DMA control unit receives a DREQ from the external request device.
When a signal is generated, a BREQN signal is output to the CPU to request the release of the bus. When the BACKN signal is returned from the CPU, a DACK signal is sent to the external request device, and data between the memory and the external request device is transmitted. In the DMA transfer device that performs transfer control, the DMA control unit includes a mask unit that masks the BREQN signal, and controls the bus occupation state by the DMA transfer by masking the BREQN signal by the mask unit. DMA transfer device. 4. The DMA transfer device according to claim 1, further comprising a unit that controls the mask time according to the number of external request devices that can operate simultaneously. 5. The DMA according to claim 1, further comprising management means for managing a processing load on the CPU, and means for controlling the mask time according to the processing load on the CPU. Transfer device. 6. A DR for detecting a generation cycle of a DREQ signal.
4. The DMA transfer device according to claim 1, further comprising an EQ signal cycle detecting unit, wherein the masking unit masks the DREQ signal based on the DREQ signal generation cycle. 7. A BREQN signal period detection unit for detecting a generation period of a BREQN signal generated in response to a DREQ signal of a plurality of external request devices that permit an operation, wherein the mask unit is configured to detect a generation period of the BREQN signal based on the BREQN signal generation period. 4. The DMA transfer device according to claim 1, wherein the BREQN signal is masked. 8. A management means for managing the processing load of the CPU, a setting means for obtaining a bus occupancy rate associated with the CPU processing and setting a limit value thereof, and a mask time according to the processing load of the CPU and the limit value. 5. The DMA transfer device according to claim 1, further comprising: means for controlling the DMA transfer.