JP2000294189A - Data acquisition system for time-of-flight mass spectrometer - Google Patents

Abstract

(57) [Summary] In a data acquisition system used for TOF-MS, an operation speed difference between an ADC 1 of ECL and a memory 5 or an adder 4 of TTL or CMOS can be absorbed, and within an allowed time. A predetermined number of data can be integrated. SOLUTION: A latch 3, an adder 4, and a memory 5 are provided in eight systems of the following. The timing control section 11 outputs a period signal after counting 256 start pulses.
The AD data digitized by the ADC 1 is sequentially latched from the system, is integrated by the adder 4 with the integrated data of the memory 5, and is written into the memory 5. Memory 5 is A,
B has two sets. When the AD data of 256 measurements is integrated, switching between the A set and the B set is performed, and the second memory control unit 6 reads the data integrated so far from the A set or the B set and stores the read data in the memory 7. Integrates with the stored data and returns to memory 7 again.
Write to. The above operation is repeated a predetermined number of times.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a system for collecting output data from a detector in a time-of-flight mass spectrometer (TOF-MS).

[0002]

2. Description of the Related Art TOF
-MS discharges an ionized sample by a start pulse, accelerates the sample, and performs mass spectrometry by utilizing the fact that the time until the ion reaches a detector differs depending on the difference in the mass of ions.

Therefore, it is necessary to measure the time from the start pulse to the arrival of the ion at the detector with high accuracy. For this purpose, a signal of the spectrum output from the detector is digitized at the subsequent stage of the detector. An A / D converter (hereinafter, referred to as an ADC) is provided. And TOF-M
In S, since a high time resolution is desired to obtain a good spectrum, a high-speed ADC is required. For this reason, an ADC having a high-speed logic element (hereinafter, simply referred to as ECL) called emitter-coupled logic is used as the ADC. When an ECL ADC is used, the clock can be set to about 500 MHz, so that the output of the detector can be A / D-converted at a cycle of about 2 nsec.

[0004] Data digitized by the ADC (hereinafter, referred to as ADC)
This is referred to as AD data) is stored in a memory, and a TTL or CMOS memory is used as the memory. However, the cycle time of a TTL or CMOS memory is usually about 12 nsec,
All AD data output from DC is converted to TTL or CMO
In order to store the data in the memory of S, the connection circuit needs to be devised.

Further, in TOF-MS, data obtained by one measurement often has insufficient S / N.
The data obtained by a plurality of measurements is integrated by an adder, and S
In this case, the ADC has a high-speed clock of about 500 MHz, whereas the adder for performing the integration uses a TTL or CMOS as in the case of the memory. Since the clock is low at about 70 MHz, the operation speed difference between these circuits must be absorbed by some means. It should be noted that one measurement refers to collecting data of the detector output of ions ejected by one start pulse.

Further, there are also the following requirements. TOF-M
In S, the discharge of ions by the start pulse is repeated many times in a cycle of about 100 μsec to 500 μsec. That is, the measurement is repeatedly performed many times, but the above-described integration of the data is not to integrate the data in all the measurements, but to integrate the data of a certain number of measurements, and to calculate the integrated data. Is analyzed as a group of This is because, if the measurement is repeated many times, the spectrum may change little by little. For example, if the measurement is performed 100,000 times now, the spectrum obtained in the first measurement and the spectrum obtained in the last 100,000 measurement may be significantly different, and in all these measurements, It is not advisable to integrate the data obtained.

Therefore, data of a certain number of measurements is integrated and treated as a set of data. For example, if data of 1000 measurements are integrated, the first first measurement is performed. The data from the measurement data to the data of the 1000th measurement are integrated and integrated into the next 1001
Repeating the process of integrating the data from the first measurement to the data of the 2000th measurement into a single set, analyzing each of the single set of data, and combining the results to produce an analysis result It is carried out. The number of measurements to be integrated for obtaining this set of data is required to be at least about 1,000, and if it is large, tens of thousands of data may need to be integrated.

The number of data bits increases as data is accumulated. For example, if the AD data is 8 bits, if the data of 1000 measurements are integrated, the number of bits of one data is 18 bits, and if the maximum integration number of data is 65,535, the data of one data is The number of bits is 24 bits. Such integration is performed by an adder, but it is very difficult to perform such data having a large number of bits within a limited short time.

Therefore, it is required that the required number of data can be integrated within an allowable time.

The present invention satisfies the above requirements, can absorb the difference in operating speed between the ECL ADC and the TTL or CMOS memory or adder, and integrates a predetermined number of data within the allowed time. It is an object of the present invention to provide a data collection system for a time-of-flight mass spectrometer capable of performing the above.

[0011]

In order to achieve the above object, a data collection system for a time-of-flight mass spectrometer according to the first aspect of the present invention includes an n-bit (n = 1 to 8) integration counter at a preceding stage. Place, the integration of up to 2 ⁿ times the N (N = 6~1
It performed in 16-bit adder and a 16-bit dual-port memory 6), after the integration ends, with continued same integrated switches the dual-port memory, 32-bit adder the integrated spectrum between 2 ⁿ times during and 32 It is characterized by multiplication by a bit memory. The data acquisition system for a time-of-flight mass spectrometer according to claim 2, wherein n
A multiplication counter of bits (n = 1 to 8) is placed at the preceding stage, and 2
The integration up to ⁿ times is performed by N (N = 6 to 16) 16-bit adders and 16-bit dual-port memories. After the integration is completed, the dual-port memory is switched to continue the same integration. A data transfer and bidirectional memory control unit for transferring and rearranging the divided spectrum data and clearing the preceding memory is provided. The data collection system for a time-of-flight mass spectrometer according to claim 3, wherein an 8-bit counter is provided at a preceding stage, and N (N = 6 to 16) 16-bit adders and 16-bit duals are integrated up to 2 ⁿ times. A time-of-flight mass spectrometer that performs the same accumulation in a port memory and, after completion of the accumulation, switches over the dual-port memory and continues the same accumulation, and in the meantime, integrates the 2 ⁿ integrated spectra with a 32-bit adder and a 32-bit memory. Data collection system, the ⁿ of the integrated value 2 ⁿ of the 8-bit counter is set to 5
8 is variable.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a view showing a first embodiment of a data acquisition system for a time-of-flight mass spectrometer according to the present invention, wherein 1 denotes an AD constituted by an ECL.
C, 2, 10, and 12 are level converters for converting the ECL level to the CMOS level, 3 is a latch, 4 is an adder, 5 is a dual port memory (DPM: hereinafter simply referred to as a memory), and 6 is a memory. 2 a memory control unit, 7 is a 32-bit memory, 8 is a reference oscillator for generating a 500 MHz clock, 9 is a pulse generation circuit, 11 is a timing control unit,
Reference numeral 3 denotes a first memory control unit. In the drawing, a thick line indicates a data flow, and a thin line indicates a control signal flow. Also,
Here, CMOS memories are used as the memories 5 and 7.

An output signal of a detector (not shown) is amplified by a preamplifier (not shown) and input to ADC1.
Here, it is assumed that the clock frequency of the ADC 1 is 500 MHz. Accordingly, ADC 1 outputs AD data every 2 nsec. The AD data from ADC 1 is supplied to level converter 2
From the ECL level to the CMOS level.

At the subsequent stage of the level converter 2, a series circuit comprising an 8-bit latch 3, a 16-bit adder 4 and a memory 5 is connected in parallel in eight systems. Hereinafter, for convenience, the system, the system,... Here, the memory 5 is a 16-bit, 32 kB memory, and has two sets of A and B. Also,
It is assumed that the latch 3 and the adder 4 are composed of CMOS elements.

The pulse generation circuit 9 has a TOF-
When a start pulse for ejecting ions from the MS is received, a 500 MHz clock from the reference oscillator 8 is applied to AD.
C1 and the rising edge is shifted by one clock of the clock based on the clock of the reference oscillator 8, the frequency is 62.5 (= 500/8) MHz, and the duty is
Generate eight 50% pulses. These eight pulses are converted from the ECL level to the CM by the level converter 10.
The signal is converted to the OS level and supplied to each clock input of the eight latches.

FIG. 2 shows the relationship among these start pulses, a 500 MHz clock, and eight pulses. FIG.
FIG. 2A shows a start pulse, and FIG.
2 (c) to 2 (j) respectively show the system
The pulse supplied to the system latch is shown. The latch 3 of each system latches the AD data at the rising edge of the pulse supplied from the level converter 10.

The timing control section 11 is composed of an 8-bit counter, and outputs a period signal every time 256 start pulses are counted. This period signal is converted from the ECL level to the CMOS level by the level converter 12 and supplied to the first memory control unit 13 and the second memory control unit 6.

The first memory control unit 13 receives a start pulse and eight pulses from the level converter 10 although not shown in FIG. The control of the latch 3, the adder 4, and the memory 5 is performed. Here, the clock for controlling the latch 3, the adder 4, and the memory 5 is 70 MHz.
And

The second memory control unit 6 adds the data read from the set A or the set B and the data read from the memory 7 for each of the systems, and integrates the data, and stores the sum in the memory 7 again. Is what you do.

The operation will be described below. Now, it is assumed that the memories 5 and 7 of the system to the system are all cleared. Then, the first start pulse causes 1
Assume that the second measurement has started. At this time, the first A
The D data is supplied to the system-to-system latch 3,
At this time, since the pulse supplied to the system latch 3 shown in FIG. 2C rises to a high level, it is latched by the system latch 3. Similarly, the second AD data is latched by the system latch 3,..., The eighth AD data is latched by the system latch 3.

When the first AD data is latched by the system latch 3, the first memory control unit 13
Data is read from the address A of the set A of the memory 5 of the system, the AD data latched by the latch 3 is integrated by the adder 4, and overwritten on the address 1 of the set A of the memory 5. The first memory control unit 13 determines the operation related to this system as 2
The processing is performed until the first to eighth AD data are latched by the system latches 3 to 3, respectively.

The same applies to the system. That is, the first
When the second AD data is latched by the system latch 3, the memory control unit 13 reads the data from the address A of the set A of the system memory 5 and compares the AD data latched by the latch 3 with the adder 4. Integrate and overwrite address 1 of set A in memory 5. The first memory control unit 13 performs the operation related to this system until the third to ninth AD data are latched by the system latches 3 to 3, respectively. The same applies to the operations of the system to the system.

In this manner, the first to eighth AD data are stored at the first address of the set A of the system-to-system memory 5, respectively. Then, the ninth AD data is latched by the system latch 3, and the.
The data is latched in the system latch 3, but when the ninth AD data is latched in the system latch 3, the first memory control unit 13 sets the second set A of the system memory 5.
The data is read from the address, and A latched by the latch 3
The D data and the adder 4 are integrated and overwritten on address 2 of the set A in the memory 5. The first memory control unit 13 performs the operation related to this system until the tenth AD data to the sixteenth AD data are latched by the system latches 3 to 3, respectively.

The first memory control unit 13 performs the above operation,
Repeat until the first measurement is completed. As is apparent from the above description, the clock for the first memory control unit 13 to control the latch 3, the adder 4, and the memory 5 is 70 MHz, but the AD is controlled by
The time allowed for latching the data, adding the latched AD data and the data read from the set A of the memory 5 by the adder 4 and overwriting the set A of the memory 5 again is 16 nsec. It is possible to perform the operation described above.

According to this configuration, it is possible to store a total of 256 × 10 ³ pieces of AD data for one measurement in the memory 5 of the system to the system. Is 512 μsec.

Next, by the second start pulse, 2
Assuming that the second measurement is started, the first AD data is supplied to the system-to-system latches 3 at this time. The third AD data is supplied to the latches 3 of the respective systems.

When the first AD data of the second measurement is latched by the system latch 3, the first memory control unit 13 reads the data from the address A in the set A of the system memory 5 and latches the data. The adder 4 accumulates the AD data latched in No. 3 and the AD data, and overwrites the address A set 1 in the memory 5. The first memory control unit 13 performs the operation related to this system until the second AD data to the eighth AD data are latched by the system latches 3 to 3, respectively. The same applies to systems to systems.

Then, the first memory control section 13 repeats the above operation for 256 times of measurement until the period signal is output from the level converter 12. As a result, the data obtained by integrating the AD data in the 256 measurements is stored in each address of the set A of the memory 5 of each system of the above. For example, in the first address of the A set in the memory 5 of the system, the first AD obtained by 256 measurements is stored.
A value obtained by integrating the data is stored, and a value obtained by integrating the second AD data obtained in 256 measurements is stored in the first address of the set A in the memory 5 of the system.

When the first memory control unit 13 receives the period signal, it switches the memories 5 of each system from A set to B set and repeats the above operation. Therefore, the AD data obtained in 256 measurements from the 257th measurement to the 512th measurement is integrated in the B set of the memory 5 of each of the following systems.

When the second memory control unit 6 receives the period signal, it reads out the data stored in the set A of the memory 5 of each system in a time-series order, and overwrites the memory 7 in the read-out order. Accordingly, the second memory control unit 6 first reads out data obtained by integrating the first AD data from the address A of the set A of the system memory 5 and overwrites the data at the address 1 of the memory 7, and then reads the data of the system memory 5. 5 A
The operation of reading data obtained by integrating the second AD data from the first address of the set and writing the data to the second address of the memory 7 is sequentially performed. As a result, the data obtained by integrating the first obtained AD data at each measurement, the data obtained by integrating the second obtained AD data,... become.

Then, the second memory control unit 6 reads out all data from the A set of the memory 5 of each system as described above and writes it in the memory 7,
A set of the memory 5 of each system is cleared and the operation is terminated. The second memory control unit 6 may perform the above operation while the AD data is accumulated in the B set of the memory 5. Therefore, even when the memory 7 is configured by a CMOS element, the second memory The target margin is enough.

As described above, from the 257th measurement, 5
When the 256 measurements up to the twelfth measurement are completed, a third start pulse is generated, and the third measurement is started. Assuming that the third measurement is started, when receiving the period signal, the first memory control unit 13 switches the memories 5 of the respective systems from B set to A set, and repeats the above-described operation. Therefore, the AD data obtained in 256 measurements from the 513th measurement to the 768th measurement is
Are integrated in the A set of the memory 5 of each system. Further, upon receiving this period signal, the second memory control unit 6 reads out the data stored in the B set of the memories 5 of the respective systems in time-series order,
The data at the corresponding address in the memory 7 is read out, integrated, and overwritten on the address in the memory 7 again. Therefore, the second memory control unit 6 first reads out the data obtained by integrating the first AD data from the first address of the B set of the system memory 5 and reads out the data at the first address of the memory 7 and integrates the data. 7, the data obtained by integrating the second AD data from the first address of the B set in the system memory 5 is read, and the data at the second address of the memory 7 is read and integrated. Are sequentially performed. As a result, the value obtained by integrating the data from the first measurement to the 512th measurement is stored in the memory 7.

The above operation is repeated a predetermined number of times.
The number of measurements to be accumulated in the memory 7 is determined by the second memory control unit 6. In this configuration, the memory 7 can accumulate data of up to 65535 measurements. It has been done.

When the data of the predetermined number of measurements are accumulated in the memory 7, the data stored in the memory 7 is taken into the subsequent analyzer as a set of data, and the above-mentioned operation is repeated again from the next start pulse. The operation is repeated a predetermined number of times.

As described above, according to the data collection system for a time-of-flight mass spectrometer, the integration of the AD data is performed by the latches 3 of eight systems from system to system with 256 measurements as one unit. The addition is performed by the adder 4 and the memory 5, and the data obtained by integrating the 256 times as one unit are performed by the second memory control unit 6 and the memory 7. Therefore, the ADC 1 is used as a high-speed ADC using ECL. Even if the memories 5 and 7 are low-speed memories using CMOS elements, it is possible to absorb these speed differences and obtain good integrated data within an allowable time.

Further, since the adder 4 and the memory 5 can use those having a small number of bits, the space can be reduced, and the space can be reduced. Therefore, the signal line can be shortened. This is advantageous for high-speed operation.

Further, the data integration by the second memory control unit 6 is performed in the next set of the memory 5 of the system.
It may be performed while the integration of the AD data of the 56 measurements is performed, so that a low-speed one may be used.

Next, a second embodiment of the data collection system for a time-of-flight mass spectrometer according to the present invention will be described. In the second embodiment, the second memory 6 of FIG.
~ From A set or B set of system memory 5
The operation is to efficiently read out the integrated data for 256 measurements, write it to the memory 7, and clear the set A or set B read out of the memory 5.

Now, assuming that the integrated data is read out from the A set of the memory 5 of the system and cleared, the operation at this time is, for example, first, as described above, the A set of the memory 5 of the system. 1 from address 1
The data obtained by integrating the second AD data is read out and overwritten on the address 1 of the memory 7, and then the data obtained by integrating the second AD data from the address 1 of the set A of the memory 5 of the system is read out and read out from the memory 7. By sequentially performing the operation of writing to the address, all the integrated data is read out from the A set of the memory 5 of the system and sequentially overwritten in the memory 7, and then 0 is written to the A set of the memory 5 of the system. Although clearing is conceivable, such an operation is inefficient.

That is, in this way, the address counter of the memory 5 of the second memory control unit 6 is used to read the integrated data from the set A of the memory 5 of the system and to clear the set A of these memories 5. And when
It must be operated twice for convenience.

Therefore, in the second embodiment,
In order to efficiently read the integrated data for 256 measurements from the set A or set B of the memory 5 of the system, write it to the memory 7, and clear the set A or set B read from the memory 5, FIG. The configuration shown in FIG. In FIG. 3, reference numeral 14 denotes a memory.
It is assumed that the memory is a 2 kB, 16-bit memory. Others are first
This is equivalent to the embodiment.

Now, suppose that the second memory control unit 6 reads out and clears the integrated data from a certain address of the A set in the memory 5 of a certain system.
The memory control unit 6 first accesses the address and reads out the integrated data as indicated by “R” in FIG.
Next, as shown by "W" in FIG. 4, the read data is written to the corresponding address of the memory 14, and then, as shown by "C" in FIG.
The operation of clearing the address by writing 0 is performed as one sequence. During this time, the second
The address counter of the memory control unit 6 does not move the address.

Then, the second memory control unit 6 performs the above operation for all addresses of the A set or the B set of the memories 5 of the system.

As described above, the system memory 5
After reading all the data from the set A, writing the data into the memory 14 and clearing the set A in the memories 5 of all the systems, the second memory control unit 6 then writes the data written into the memory 14 into the memory 7. And overwrite the data in the memory 7. That is, the second memory control unit 6
Reads data from address 1 of the memory 14 and
Data is read from address 1 of the memory 7 and integrated, the integrated value is overwritten on address 1 of the memory 7, and then
The operation of reading data from the address 2 of the memory 7 and integrating the data by reading the data from the address 2 of the memory 7 and overwriting the integrated value on the address 2 of the memory 7 is performed for all addresses. Other operations are the same as those in the above-described first embodiment.

As described above, according to the second embodiment, when the address counter of the second memory control unit 6 accesses each address of the A set or the B set of the memory 5 of the system, Since the operation only needs to be performed once, the operation can be performed efficiently.

Next, a third embodiment according to the present invention will be described. In the first and second embodiments described above,
Although the A set and the B set of the system memory 5 are assumed to accumulate the AD data of 256 measurements, depending on the sample, there is a case where the AD data of a smaller number of measurements may be accumulated. Therefore, in the third embodiment, the number of integrations in the A set and the B set of the memory 5 of the system can be designated so that AD data of a minimum of 32 times and a maximum of 256 times of measurement can be integrated. The number of times can be set flexibly.

The overall configuration of the data acquisition system for a time-of-flight mass spectrometer is the same as that shown in FIG. 1 or FIG. 3, but only the configuration of the timing control unit 11 is different. Therefore, only the configuration and operation of the timing control unit 11 will be described here. Others are the same as described above.

FIG. 5 shows an example of the configuration of the timing control section 11. In FIG. 5, 20 is an 8-bit counter, 21 is a selector, 22 to 25 are AND circuits, and 26 is an OR circuit.

The 8-bit counter 20 counts the number of start pulses, and when 32 (= ²⁵ ) start pulses are counted, the output of “05” in FIG.
When 64 (= 2 ⁶ ) counts, the output of “06” in the figure goes to a high level, and when 128 (= 2 ⁷ ) start pulses are counted, the output of “07” in the figure goes to a high level, and the start pulse is
When 256 (= 2 ⁸ ) are counted, the output of “08” in the figure becomes a high level.

The selector 21 is for setting which of the four outputs "05" to "08" of the 8-bit counter 20 is to be selected. The output of (a) is at a high level, setting of (6) sets the output of (b) to a high level, setting of (7) sets the output of (c) to a high level, setting of (8) sets the output of (d) to Becomes high level. That is, when the number of integration times is 2 ⁿ (n = 5, 6, 7, 8), the selector 2
In the case of 1, the value of n is set.

Now, it is assumed that the 8-bit counter 20 has been reset by a reset signal from a reset button or the like (not shown) and the selector 21 has set "5". The 8-bit counter 20 generates 32 start pulses.
When the number is counted, the output of “05” becomes a high level. In this case, since the output of the selector 21 is at the high level, only the output of the AND circuit 22 is at the high level. Is output as
Then, the 8-bit counter 20 repeats the operation of resetting itself with this period signal.

Therefore, in this case, in the A set and the B set of the memory 5 of the system, the AD data of 32 measurements are accumulated and stored. Selector 21
The same applies when other values are set in.

As described above, according to this embodiment, the 8-bit counter 2
Since the setting of 0 is made variable from n = 5 to 8, the number of integrations can be specified up to 32 times at the minimum and up to 256 times at the maximum, so that the number of integrations can be set flexibly.

Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment.
Various modifications are possible. For example, in the above-described embodiment, eight systems of the latch 3, the adder 4, and the memory 5 are provided. However, the present invention is not limited to this. The operating speed of the device 4 and the memory 5 and the operating speed of the ADC 1 may be determined in consideration of the operating speed. Usually, six to sixteen systems may be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of a data collection system for a time-of-flight mass spectrometer according to the present invention.

FIG. 2 is a diagram showing a relationship between a start pulse, a 500 MHz clock oscillated by a reference oscillator 8, and eight pulses generated by a pulse generation circuit 9 in the configuration of FIG.

FIG. 3 is a diagram showing a second embodiment of the data acquisition system for a time-of-flight mass spectrometer according to the present invention.

FIG. 4 shows a second memory control unit 6 according to the second embodiment.
Of data from the set A or the set B of the memory 5, writing into the memory 7,
FIG. 8 is a diagram for explaining a sequence of clearing data of a set or a B set.

FIG. 5 is a diagram illustrating a configuration example of a timing control unit 11 in a third embodiment of the data collection system for a time-of-flight mass spectrometer according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... ADC, 2 ... Level converter, 3 ... Latch, 4 ... Adder, 5 ... Dual port memory, 6 ... Second memory control part, 7 ... Memory, 8 ... Reference oscillator, 9 ... Pulse generation circuit, 10 ... Level converter, 11 timing control unit, 1
2 ... level converter, 13 ... first memory control unit.

Claims (3)

[Claims] 1. An n-bit (n = 1 to 8) integration counter is provided in the preceding stage, and N integrations (N = 6 to 16) are performed up to 2 ⁿ times.
After the integration is completed, the dual-port memory is switched and the same integration is continued. In the meantime, the spectra integrated 2 ⁿ times are combined with the 32-bit adder and the 32-bit memory. A data collection system for a time-of-flight mass spectrometer, wherein the data is integrated by: 2. An n-bit (n = 1 to 8) integration counter is provided at a preceding stage, and N integrations (N = 6 to 16) are performed up to 2 ⁿ times.
After completion of the integration, the dual-port memory is switched to continue the same integration, while the N-divided spectrum data is transferred, rearranged, and stored in the pre-stage memory. A data acquisition system for a time-of-flight mass spectrometer, comprising a data transfer and bidirectional memory control unit for clearing the data. 3. An 8-bit counter is provided in a preceding stage, and integration up to 2 ⁿ times is performed by N (N = 6 to 16) 16-bit adders and 16-bit dual-port memories. Is switched to continue the same integration, and in the meantime, in a data collection system for a time-of-flight mass spectrometer that integrates 2 ⁿ integrated spectra by a 32-bit adder and a 32-bit memory,
A data collection system for a time-of-flight mass spectrometer, wherein ⁿ of an integrated value 2 ⁿ of an 8-bit counter is varied between 5 and 8.