JP2000286428A - Field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a field-effect transistor, which can obtain a high output also in a microwave band and in which degradation of its distortion characteristics is not generated. SOLUTION: A field-effect transistor is provided with an n-type channel layer 5 formed on a semiconductor substrate, a p-type embedded layer 3 which is provided under the layer 5 and is neutralized, a source electrode 7 on the layer 5, a drain electrode 8 formed on the layer 5 leaving an interval between the electrode 8 and the electrode 7 and first and second gate electrodes 9 and 10 formed between the electrodes 7 and 8. An n-type external electrode 11, which is electrically insulated from the layer 5 and constitutes a diode with the layer 3, is formed on the layer 3 in the vicinity of the electrode 7, and the electrode 11 is connected with the electrode 10. Holes in the layer 3 are fed to the electrode 10 through the electrode 11, and reduction in the drain current is self-corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field-effect transistor, and more particularly to a field-effect transistor suitable for forming a high-output amplifier in a microwave band.

[0002]

2. Description of the Related Art A MESFET (Metal Semiconductor) using gallium arsenide (hereinafter referred to as GaAs).
or Field Effect Transisto
r) and HJFET (Heterojunction F)
ET) is widely used as a microwave band high-power amplifier for mobile communication base stations and mobile phone terminals. In recent years, a wide band semiconductor represented by gallium nitride (hereinafter, referred to as GaN) has a breakdown electric field which is nearly one digit higher than that of GaAs, and a high sheet carrier density can be obtained by using a piezo effect. It is attracting attention as a material for high-output FETs that surpasses system FETs, and is being actively researched and developed. In these high-output FETs used for wireless communication applications, higher output, higher efficiency, and lower distortion are required.

To increase the output of the FET, obtaining a high current density and a high breakdown voltage is one of the important technical elements. However, in GaAs or GaN, a large amount of deep levels (traps) exist on the bulk crystal or semiconductor surface.
During the operation of the FET, the trapping of carriers causes a current fluctuation (decrease) at a high frequency called a current lag or a current collapse, which causes a reduction in output power.

For example, in the 1994 Electronics
Letters Vol. 30 No. 25, pp. 2175-2176 (Elec
tronics Letters Vol. 30 N
o. GaN-based HJF
A remarkable current collapse phenomenon of ET has been reported. In this report example, the drain current is greatly reduced in a low drain voltage region in a dark place, and the characteristic of the GaN-based FET, such as a high current density, cannot be fully utilized. GaA
Although it is often reported that the drain current decreases in the AC operation as compared with the DC operation in the s-FET, this phenomenon is also caused by the trapping of carriers by the trap.

[0005] In order to solve these problems, besides improving the crystallinity and the quality of the semiconductor surface, attempts have been made to avoid the problems by the structure of the FET. For example, as shown in the sectional side view of FIG.
No. 0462 discloses a method in which a p-type layer 103 is provided below an n-type channel layer 105. In addition,
In FIG. 13, reference numeral 101 denotes a semiconductor substrate;
Is a source electrode and a drain electrode, 109 is a gate electrode, and 106 is n-type GaAs doped with silicon.
Layer.

[0006] Further, as shown in the cross-sectional side view of FIG.
Of Solid State Circuit 25 Vol.6 No.1
544 pages (IEEE Journal of Soli)
d-State Circuits, Vol. 25, N
o. 6 p 1544, 1990), reports an attempt to connect the p-type layer 103 to the external electrode 111 in contact with the source electrode 107 region and fix the potential.
At this time, if the p-type layer 103 is neutralized, the potential of the substrate is fixed in the horizontal direction (the direction parallel to the channel).
Fluctuations in the substrate potential due to trapping of carriers by the traps in the substrate crystal are suppressed, whereby fluctuations in the drain current and current collapse can be eliminated.

As shown in the sectional side view of FIG.
By providing the neutralized buried p-type layer 103, channel electrons between the gate electrode 109 and the drain electrode 108 can be depleted, so that another effect that the two-terminal breakdown voltage between the gate and the drain is improved. Is a technical digest of the 1998 IEEE International Electron Device Meeting, p. 71 (1998 IEEE Int.
electronic Electron Device
e Meeting Technical Digests
tp71), demonstrating significant effects.

[0008]

In the conventional examples shown in FIGS. 13, 14 and 15, at a frequency of several hundred MHz or less, the potential of the p-type layer is fixed to the source electrode (or the external electrode). Although effective in removing the drain current fluctuation due to the substrate trap, in the microwave band, the potential of the p-type layer fluctuates due to capacitive coupling with the drain, and the effect of fixing the substrate potential is lost.

That is, when an AC signal in the microwave band is input to the gate electrode or the drain electrode, even if an external electrode (for example, the external electrode 111 in FIG. 14) which makes ohmic contact with the buried p-type layer 103 is provided, n Since there is a rectifying property between the source electrode of the mold and the buried p-type layer 103, holes flow from the p-type layer 103 to the source electrode in one direction, and the potential of the p-type layer 103 gradually decreases. as a result,
A problem arises in that the channel is narrowed from the substrate side and the drain current decreases in the microwave band, resulting in a decrease in the maximum output power of the FET. Moreover, this phenomenon becomes more conspicuous as the input amplitude increases, which means that the power gain of the transistor rapidly decreases depending on the input amplitude, which causes deterioration of the distortion characteristics of the input / output power characteristics. I will.

A main object of the present invention is to provide a field effect transistor which can obtain high output even in a microwave band and does not cause deterioration of distortion characteristics.

[0011]

In order to achieve the above object, the present invention provides a first conductivity type channel layer formed on a semiconductor substrate and a neutralized channel layer provided below the channel layer. A buried layer of a second conductivity type, a source electrode formed on the channel layer, a drain electrode formed on the channel layer at an interval between the source electrode, the source electrode, A drain electrode and a gate electrode formed on the channel layer between the drain electrode and the channel layer, the field effect transistor is formed on the buried layer electrically insulated from the channel layer, together with the buried layer An external electrode constituting a diode is provided, and the external electrode is connected to the gate electrode.

In the field effect transistor of the present invention, the second
Is supplied from the external electrode to the gate electrode through the diode, and is accumulated in the gate capacitance to change the gate voltage. This change in the gate voltage acts to cancel the phenomenon that the drain current decreases due to carrier capture by the trap in the substrate. Therefore, in the field-effect transistor of the present invention, a high output can be obtained even in the microwave band, and even when the input amplitude is large, the power gain does not decrease, so that the distortion characteristics do not deteriorate.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional side view showing an example of the field effect transistor according to the present invention, and FIG. 2 is a plan view of the field effect transistor shown in FIG. FIG. 1 shows a cross section along the line AA ′ in FIG. The field effect transistor 4 (FET4) of the first embodiment shown in FIGS. 1 and 2 is an n-type dual gate GaAs.
・ MESFET, semi-insulating GaAs substrate 1
Undoped GaAs layer 2 (about 800 n thick)
m), a p-type GaAs layer doped with beryllium (Be) at a concentration of 5 × 10 ¹⁷ cm ^-3 , that is, a buried p-type layer 3
(25 nm), undoped GaAs layer 4 (200 n
m), an n-type GaAs layer doped with silicon (Si) at a concentration of 2 × 10 ¹⁷ cm ⁻³ , that is, a channel layer 5 (23
5 nm), and an n-type GaAs layer 6 (100 nm) doped with Si at a concentration of 5 × 10 ¹⁷ cm ⁻³ is formed by growing in this order by a molecular beam epitaxy (MBE) method.

Ohmic source electrode 7 and drain electrode 8
Is gold / germanium alloy / nickel / gold (AuGe / N
i / Au) is formed on each n-type GaAs layer 6 by annealing at 450 ° C. for 30 seconds.
In order to simultaneously achieve a low source resistance and a high withstand voltage, a distance of 150
A first gate electrode 9 having Schottky properties is formed by sputtering tungsten silicide (WSi) to a length of 0.9 μm on the surface of the channel layer 5 from which the epi crystal has been removed by nm.

The source electrode 7 is grounded, while the drain electrode 8 is connected via a load 13 to a power supply having a voltage VD. Then, an input RF signal is input to the first gate electrode 9. In the vicinity of the first gate electrode 9, a second gate electrode 10 is formed of WSi between the first gate electrode 9 and the drain electrode 8 with an interval between the first gate electrode 9 and the first gate electrode 9. . On the side of the source electrode 7 opposite to the drain electrode 8, a gold / germanium alloy / nickel / gold (A
Ohmic external n-type electrode 1 made of uGe / Ni / Au)
1 is provided, and between the external n-type electrode 11 and the source electrode 7, a crystal groove 12 which does not reach the buried p-type layer 3 by removing the n-type GaAs layer 5 and the n-type GaAs layer 6 is formed. Is formed.

When viewed from above, as shown in FIG. 2, the external n-type electrode 11 is electrically insulated from the channel layer 5 by the crystal groove 12 and partially surrounds the source electrode 7 so that the source n It is formed in a larger area than the electrode 7 and the drain electrode 8. The buried p-type layer 3 is formed so as to overlap below the channel layer 5 and the external n-type electrode 11. The external n-type electrode 11 is connected to the second gate 10.

Next, the operation of the field effect transistor 4 configured as described above will be described. FIG. 3 is a cross-sectional side view showing the operation of the field-effect transistor 4 of the first embodiment, and FIGS. 4A to 4D are the same waveform diagrams. 4, the horizontal axis represents time, the vertical axis of FIG. 4A represents the voltage of the first gate electrode 9, FIG. 4B represents the voltage of the drain electrode 8, and FIG. And (D) represents the voltage of the second gate electrode 10, respectively.

The field effect transistor 4 according to the present embodiment
Since the neutralized buried p-type layer 3 is provided, the channel layer 5 is electrically shielded, so that the charges 21 captured by the substrate trap do not adversely affect the operation of the FET 4. Now, as shown in FIG. 4A, assuming that an RF signal is input to the first gate electrode 9 of the FET 4, the voltage of the drain electrode 8 is also shown in FIG. It changes as By the way, since the drain region and the buried p-type layer 3 are equivalently connected by the capacitor 17, when the voltage of the drain electrode 8 changes at a high frequency, the voltage of the buried p-type layer 3 also changes correspondingly.

On the other hand, the embedded p-type layer 3 and the external n-type electrode 1
1 forms a pin diode structure 14 and has a rectifying property. Therefore, when the voltage of the buried p-type layer 3 is transferred to the positive side, the hole current flows out of the buried p-type layer 3 from the external n-electrode 11 in the forward direction. However, when the voltage of the p-type layer is transferred to the negative side, the current does not flow into the buried p-type layer 3 in the opposite direction. As a result, the average voltage of the buried p-type layer 3 gradually changes to the negative side as shown in FIG.

The conventional external electrode 111 shown in FIG.
Is connected to the source electrode 107 and another power source, so that the holes only flow freely from the buried layer through the external electrode. However, in this embodiment, since the external n-type electrode 11 is connected to the second gate electrode 10, the holes that flow out charge the gate capacitance of the second gate electrode 10 positively, and the second gate electrode 10 The voltage of 10 gradually changes to the positive side as shown in FIG.

As a result, in this embodiment, the phenomenon that the voltage of the buried p-type layer 3 gradually changes to the negative side is self-corrected, and the voltage of the buried p-type layer 3 is maintained at a constant value.
Therefore, the DC component of the drain current is kept constant. FIGS. 11A and 11B are diagrams showing that the drain current of the field effect transistor 4 is kept constant, as compared with a conventional field effect transistor. FIG. 11A is a circuit diagram, FIG. 11B is a graph showing a gate voltage, (C) is a graph showing the DC component of the drain current. FIG. 11A schematically shows the periphery of the field-effect transistor 4. An AC voltage is applied to the first gate electrode 9 together with a bias voltage, while a current (arrow I) flows through the load 13 to the drain. It indicates that it flows. The horizontal axes of (B) and (C) of FIG. 11 both represent time, the vertical axis of (B) is the voltage of the first gate electrode 9, and the vertical axis of (C) is the average value (DC component) of the drain current. Is represented.

When an AC voltage is applied to the first gate electrode 9 together with a DC bias voltage as shown in FIG. 11B, the average value of the drain current of the conventional field-effect transistor becomes as shown in FIG. Although it gradually decreases as time elapses as shown by the curve 12, in the field-effect transistor 4 of the present embodiment, as shown by the straight line 14, it is constant over time.

FIG. 12 is a graph showing the power gain and output power of the field effect transistor 4 in the microwave band in comparison with the conventional field effect transistor. In FIG. 12, the horizontal axis represents the magnitude of the input power. The right vertical axis represents the power gain, and the left vertical axis represents the output power.
Curves 22 and 24 show changes in the power gain of the field effect transistor 4 of the embodiment and the conventional field effect transistor, respectively, and curves 26 and 28 show the changes of the field effect transistor 4 of the embodiment and the conventional field effect transistor, respectively. The change of the output power of the effect transistor is shown.

In the conventional field effect transistor 4, FIG.
As shown by curve 12 in FIG. 1, the drain current decreases as time passes, but the degree of the decrease increases as the input power increases. Therefore, as shown in the graph of FIG. 12, in the conventional field effect transistor, as the input power increases, the power gain (curve 24) and the output power (curve 2)
8) Both are greatly reduced. On the other hand, in the field effect transistor 4 of the present embodiment, since the drain current does not change, the power gain (curve 22) is kept constant even when the input power is large, and the output power (curve 26).
Increases in proportion to the input power. As described above, in the field-effect transistor 4 of the present embodiment, high output is obtained even in the microwave band, and the power gain does not decrease even when the input amplitude is large, so that the distortion characteristics do not deteriorate. .

In the field effect transistor 4 of the present embodiment, a part of the holes of the buried p-type layer 3 also flows out to the source electrode 7, but the area of the external n-type electrode 11 is increased as described above. Therefore, most of the holes flow out to the external n-type electrode 11, and the effect of the present embodiment is maintained.

The voltage applied to the second gate electrode 10 preferably has the same phase as the input RF signal applied to the first gate electrode 7 or the input RF component is sufficiently attenuated. However, in a normal FET application, since the load 13 exists, in principle, the second gate electrode 1
The signal fed back to 0 is 180 degrees out of phase with the input signal (FIG. 4B). However, actually, the hole mobility is small and the resistance 18
Because of the large (FIG. 3) and the presence of the parasitic capacitance 16, the RF component of the signal applied to the second gate electrode 10 has the external n-type electrode as shown in FIG. 11
Already attenuated by the time it exits,
Degree phase shifts are usually not a problem.

Next, a second embodiment of the present invention will be described. FIG. 5 is a sectional side view showing a field effect transistor according to the second embodiment. In the drawing, the same elements as those in FIG. 1 and the like are denoted by the same reference numerals, and a description thereof will be omitted here. The field effect transistor 32 of the second embodiment is different from the field effect transistor 4 in that a low-pass filter 19 including a resistor and a capacitor is provided to remove an RF component from the voltage of the external n-type electrode 11. It is a point. Therefore, in the field-effect transistor 32, the RF component included in the voltage applied to the second gate electrode 10 is greatly attenuated as compared with the case of the field-effect transistor 4, and the drain current can be more reliably kept constant. As a result, a higher output is obtained even in the microwave band, and a better result is obtained in that the distortion characteristics are not deteriorated. Note that the low-pass filter 19 is not necessarily limited to a filter constituted by a resistor and a capacitor.

Next, a third embodiment of the present invention will be described. FIG. 6 is a sectional side view showing a field-effect transistor according to the third embodiment. In the drawing, the same elements as those in FIG. 1 and the like are denoted by the same reference numerals, and a description thereof will be omitted here. The field effect transistor 34 according to the third embodiment is different from the field effect transistor 4 in that an SiO 2 film 20 as an interlayer insulating film has a thickness of 10 mm.
The point is that the second gate electrode 10 is formed by vapor deposition of gold (Au) after a film is formed on the element surface by thermal CVD at 0 nm.

By adopting such a structure, the second
Since the gate electrode 10 has a MOS structure and has no leakage current, the effect of accumulating positive charges is further enhanced. As a result, the drain current can be more reliably kept constant,
Even better results are obtained in that high output is obtained even in the microwave band and distortion characteristics are not deteriorated.

Next, a fourth embodiment of the present invention will be described. FIG. 7 is a sectional side view showing a field-effect transistor according to the fourth embodiment. In the drawing, the same elements as those in FIG. 1 and the like are denoted by the same reference numerals, and a description thereof will be omitted here. The field effect transistor 36 of the fourth embodiment is different from the field effect transistor 4 in that the external n-type electrode 11 is
After partially removing the GaAs layer 5 and the undoped GaAs layer 4 to expose the buried p-type layer 3,
The point is that it is formed by depositing gold (Au) in contact with the mold layer 3.

Therefore, in the field effect transistor 36, the external n-type electrode 11 forms a p-type Schottky diode. By adopting such a configuration,
Although the manufacturing process becomes complicated, the external n-type electrode 11 having a rectifying property is directly connected to the buried p-type layer 3, and the flow of holes through the external n-type electrode 11 is improved. Therefore, the drain current can be more reliably maintained at a constant level, and a high output can be obtained even in the microwave band, and the effect that the distortion characteristic does not deteriorate becomes more remarkable.

Next, a fifth embodiment of the present invention will be described. FIG. 8 is a plan view showing a field-effect transistor according to a fifth embodiment, and FIG. 9 is a cross-sectional side view taken along the line BB 'in FIG. In the drawing, the same elements as those in FIG. 1 and the like are denoted by the same reference numerals, and a description thereof will be omitted here. The field-effect transistor 38 of the fifth embodiment is different from the field-effect transistor 4 in that the field-effect transistor 38 has only the first gate electrode 9 as a gate electrode and the output signal of the low-pass filter 19 is the first signal. The point is that it is supplied to the gate electrode 9.

Even with such a configuration, the voltage from the gate electrode can be increased by supplying holes from the buried p-type layer 3 to the gate electrode, and the drain current can be kept constant by self-correction. . Therefore, the same effect as in the case of the field-effect transistor 4 can be obtained in the field-effect transistor 38. Further, since the field-effect transistor 38 does not require the second gate electrode 10, the manufacturing process is simplified. The effect is obtained.

As shown in FIGS. 8 and 9, the input R
In order to prevent F signal leakage, choke inductor 3
It is also effective to insert 0 between the low-pass filter 19 and the first gate electrode 9 or between the low-pass filter 19 and the supply source of the bias voltage VG. In addition to attaching the low-pass filter 19 externally, it is of course possible to form the low-pass filter 19 monolithically on the same semiconductor substrate.

Next, a sixth embodiment of the present invention will be described. FIG. 10 is a sectional side view showing a field effect transistor according to the sixth embodiment. In the drawing, the same elements as those in FIG. 1 and the like are denoted by the same reference numerals, and a description thereof will be omitted here. The field-effect transistor 40 of the sixth embodiment is different from the field-effect transistor 3
The difference from 8 is that the external n-type electrode 11 is formed by depositing Au in contact with the buried p-type layer 3 as in the field effect transistor 36. Therefore, in the field-effect transistor 40, the effect of the fourth embodiment can be obtained in addition to the effect obtained in the fifth embodiment.

In the above embodiment, the field effect transistors are all n-type GaAs M fabricated by MBE.
Although an ESFET is used, the principle of the present invention is that a semiconductor material other than GaAs (for example, InP or Ga) is used when the buried layer is formed by ion implantation or when the conductivity type is reversed.
N), the FET structure other than the MEFET (for example, a high electron mobility field effect transistor: HE
Needless to say, the method is effective in any case where (MT) is adopted.

[0037]

As described above, the present invention relates to a first conductive type channel layer formed on a semiconductor substrate and a neutralized second conductive type channel layer provided below the channel layer. A buried layer, a source electrode formed on the channel layer, a drain electrode formed on the channel layer at an interval between the source electrode, and a drain electrode formed between the source electrode and the drain electrode. A field effect transistor comprising a gate electrode formed on the channel layer,
An external electrode which is electrically insulated from the channel layer and is formed on the buried layer and forms a diode together with the buried layer is provided, and the external electrode is connected to the gate electrode.

In the field effect transistor of the present invention having the above-described structure, the second conductivity type carrier is supplied from the external electrode to the gate electrode through the diode, and is accumulated in the gate capacitance to change the gate voltage. This change in the gate voltage acts to cancel the phenomenon that the drain current decreases due to carrier capture by the trap in the substrate. Therefore, in the field-effect transistor of the present invention, a high output can be obtained even in the microwave band, and even when the input amplitude is large, the power gain does not decrease, so that the distortion characteristics do not deteriorate.

[Brief description of the drawings]

FIG. 1 is a sectional side view showing an example of a field-effect transistor according to the present invention.

FIG. 2 is a plan view of the field-effect transistor shown in FIG.

FIG. 3 is a cross-sectional side view illustrating an operation of the field-effect transistor according to the first embodiment.

FIGS. 4A to 4D are waveform diagrams illustrating the operation of the field-effect transistor according to the first embodiment.

FIG. 5 is a cross-sectional side view showing a field-effect transistor according to a second embodiment.

FIG. 6 is a cross-sectional side view illustrating a field-effect transistor according to a third embodiment.

FIG. 7 is a cross-sectional side view illustrating a field-effect transistor according to a fourth embodiment.

FIG. 8 is a plan view showing a field-effect transistor according to a fifth embodiment.

9 is a cross-sectional side view taken along the line BB 'in FIG.

FIG. 10 is a sectional side view showing a field-effect transistor according to a sixth embodiment.

11A and 11B are diagrams showing that a drain current of a field-effect transistor is kept constant, as compared with a conventional field-effect transistor, (A) is a circuit diagram, (B) is a graph showing a gate voltage, C) is a graph showing the DC component of the drain current.

FIG. 12 is a graph showing a power gain and an output power of a field effect transistor in a microwave band in comparison with a conventional field effect transistor.

FIG. 13 is a sectional side view showing an example of a conventional field-effect transistor.

FIG. 14 is a sectional side view showing another example of a conventional field-effect transistor.

FIG. 15 is a sectional side view showing still another example of the conventional field effect transistor.

[Explanation of symbols]

1 ... Semi-insulating GaAs substrate, 2 ... Undoped GaAs
s layer, 3 buried p-type layer, 4 field-effect transistor (FET), 5 channel layer, 6 n-type GaAs
s layer, 7 ... source electrode, 8 ... drain electrode, 9 ...
1st gate electrode, 10 ... 2nd gate electrode, 11 ... external n-type electrode, 12 ... curve, 13 ... load, 14 ... straight line, 16 ... parasitic capacitance, 18 ... resistance, 19 ... Low-pass filter, 20: SiO2 film, 21: electric charge, 22:
... Curve, 24 ... Curve, 26 ... Curve, 28 ... Curve,
30 Choke inductor, 32 Field effect transistor, 34 Field effect transistor, 36 Field effect transistor, 38 Field effect transistor, 4
0: Field effect transistor.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroyuki Takahashi 5-7-1 Shiba, Minato-ku, Tokyo Inside the NEC Corporation (72) Inventor Tatsumine Nakayama 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (72) Kenshi Kasahara, Inventor 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation F-term (reference) 5F102 FA02 GA14 GB01 GC01 GC05 GD01 GD10 GJ05 GL05 GN05 GT03 GT05 GV07 HC01 HC11

Claims (12)

[Claims] A first conductive type channel layer formed on a semiconductor substrate; a neutralized second conductive type buried layer provided below the channel layer; A source electrode formed, a drain electrode formed on the channel layer at an interval between the source electrode, and a gate formed on the channel layer between the source electrode and the drain electrode A field effect transistor comprising: an electrode that is electrically insulated from the channel layer, is formed on the buried layer, and includes an external electrode that forms a diode together with the buried layer. A field-effect transistor, which is connected to an electrode. 2. The field effect transistor according to claim 1, wherein the external electrode is an ohmic first conductivity type electrode, and forms a pn junction with the buried layer. 3. The external electrode is provided on a first conductive type semiconductor layer formed on the semiconductor substrate and at the same layer level as the channel layer. 3. The field effect transistor according to claim 2, wherein a groove is formed between the grooves to electrically separate the two from each other. 4. The field effect transistor according to claim 3, wherein the external electrode is formed so as to partially surround the source electrode. 5. The field effect transistor according to claim 3, wherein said external electrode has a larger area than said source electrode and said drain electrode. 6. The field effect transistor according to claim 1, wherein the external electrode is a Schottky electrode formed in contact with the buried layer. 7. The gate electrode includes first and second gate electrodes spaced from each other, the external electrode is connected to the second gate electrode, and the first gate electrode is connected to the second gate electrode. 2. The field effect transistor according to claim 1, wherein the field effect transistor is a gate electrode for signal input. 8. The field effect transistor according to claim 7, wherein said second gate electrode is disposed between said first gate electrode and said drain electrode. 9. The field effect transistor according to claim 7, wherein said second gate electrode is formed on a surface protection film made of an insulator formed on said channel layer. 10. The field effect transistor according to claim 7, wherein said external electrode is connected to said second gate electrode via a low-pass filter. 11. The field effect transistor according to claim 1, wherein said external electrode is connected to said gate electrode via a low-pass filter. 12. The field effect transistor according to claim 11, wherein said gate electrode is a signal input gate electrode.