JP2000278117A - Count circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of a count circuit without impairing its substantial function. SOLUTION: This count circuit 111 is provided with a circuit 20 that detects whether or not initial data R3, R4 of prescribed high-order bits among initial data stored in a register 10 are all '1B' and with a clock supply control circuit 30 that inhibits supply of a clock signal CLK to flip-flop circuits 101-3, 101-4 that conduct count processing for the prescribed high-order bits when the initial data R3, R4 of prescribed high-order bits are all '1B'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counting circuit, and more particularly, to a synchronous counting circuit comprising a plurality of flip-flops, wherein a clock signal is supplied to each flip-flop to perform a counting operation.

[0002]

2. Description of the Related Art Devices such as microcomputers composed of semiconductor integrated circuits are used in various devices to perform various controls, such as system control. In order for the microcomputer to realize these controls, it is necessary to accurately adjust the timing of the output signal and the processing timing within the input signal. As described above, in order to make the output and operation timing accurate, a microcomputer or a semiconductor integrated circuit constituting the microcomputer has a built-in counting circuit.

[0003] As a counting circuit, there is a so-called synchronous counting circuit. The synchronous counting circuit includes, for example, a plurality of flip-flops, and a clock signal is supplied to each flip-flop. Each flip-flop operates according to the clock signal. That is, in the synchronous clock circuit, each flip-flop operates in synchronization with the clock signal.

[0004] The synchronous counting circuit has a higher operating speed than an asynchronous counting circuit in which each of a plurality of flip-flops except the first-stage flip-flop operates in response to a change in the output signal of the preceding flip-flop. is there. For this reason, a synchronous counting circuit is often used for a semiconductor integrated circuit or the like that requires a high-speed operation.

[0005]

As described above, since each flip-flop constituting the synchronous counting circuit operates in response to the supply of the clock signal, a current consumption occurs in each flip-flop. For this reason,
Conventional synchronous counting circuits do not always satisfy the high-speed operation and low power consumption required in recent semiconductor integrated circuits.

In particular, when an initial value at which counting is started can be set in the synchronous counting circuit, all flip-flops constituting the synchronous counting circuit receive a clock signal regardless of the initial value. It operates according to the supply of. For this reason, depending on the initial value, a flip-flop that does not need to operate may also operate unnecessarily.

For example, it is assumed that an initial value is 1110B in a 4-bit synchronous counting circuit. The letter B added to the end of the numerical sequence means that each numerical value in the numerical sequence is represented by a binary number. The leftmost end of the numerical sequence is the most significant bit, and the rightmost end of the numerical sequence is the least significant bit. .

Generally, a synchronous counting circuit outputs a carry signal when all the bits of the count value become 1B (when the count value becomes 1111B in the case of a 4-bit synchronous counting circuit). Is what you do.

In the case of the above initial value, a carry signal is output if the least significant bit is counted by one. In this case, only the flip-flop that counts the least significant bit needs to operate. However,
In the conventional synchronous counting circuit, all flip-flops operate regardless of the initial value. Therefore,
The power consumption of the synchronous clock circuit is unnecessarily increased.

An object of the present invention is to provide a counting circuit capable of reducing power consumption without impairing the original function in view of the above problems.

[0011]

In order to achieve the above object, the present invention comprises n (where n is a positive integer of 2 or more) flip-flops each capable of storing initial data. The flip-flop operates in response to the supply of a clock signal. In the n-bit count circuit, predetermined high-order k bits (however,
k is a positive integer of n> k) a detection circuit for detecting whether or not the initial data is 1 and supply of a clock signal to a flip-flop corresponding to a predetermined upper bit in accordance with a detection result of the detection circuit And a clock supply control circuit for controlling

Further, in order to achieve the above object, the present invention provides a method for storing n data (where n
Is a positive integer of 2 or more), and each flip-flop is an n-bit count circuit that operates when a clock signal is supplied. A detection circuit for detecting whether the initial data for the bit is 0 or not, and an m-th (where m is a positive integer of n ≧ m) flip-flop supplied to each flip-flop according to the detection result of the detection circuit. An initial data control circuit for controlling whether or not to supply the initial data as the initial data of the (m-1) -th flop, and a second circuit for generating a clock pulse in a first cycle according to a detection result of the detection circuit. 1 and a second signal that generates a clock pulse with a cycle twice as long as the first cycle. It shall have a clock selection circuit for outputting a signal.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The counting circuit of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram of the count circuit according to the first embodiment of the present invention. Note that the count circuit in FIG. 1 will be described by taking a 4-bit count circuit (corresponding to one that counts 16 in decimal notation) as an example.

In FIG. 1, the counting circuit 111 includes a counting section 100 for performing a counting operation, a detection circuit 20, a register 10 as a storage circuit, and a clock supply control circuit 30. Note that each of the register 10, the detection circuit 20, and the clock supply control circuit 30 may be a peripheral circuit provided around the count circuit 111. However, here, the register 10, the detection circuit 20, the clock supply control circuit 30, and the counter 100 And the counting circuit 1
11 will be described.

The register 10 is, for example, a shift register or a plurality of individual flip-flops. Therefore, it has four temporary storage circuits 10-1 to 10-4 as temporary storage means. Each of the temporary storage circuits 10-1 to 10-4 is formed of, for example, a flip-flop.

The register 10 stores and outputs an initial value at which the count circuit 111 starts a count operation. That is, the least significant bit of the initial value is stored in the temporary storage circuit 10-1 as the initial data. Temporary storage circuit 1
In 0-2, the second bit of the initial value is stored as initial data. The temporary storage circuit 10-3 stores the third bit of the initial value as initial data. The temporary storage circuit 10-4 stores the most significant bit of the initial value as initial data. The initial data stored in the temporary storage circuits 10-1 to 10-4 are output as signals R1 to R4, respectively.

The detection circuit 20 comprises, for example, a two-input one-output AND gate 21 as shown in FIG. The signals R3 and R4 are input to the AND gate 21. Therefore, the potential levels of signal R3 and signal R4 are both the power supply potential level (hereinafter, referred to as H level,
When expressed as data, it is called 1B).
AND gate 21 outputs H-level signal N1. When one or both of the signal R3 and the signal R4 are at the ground potential level (hereinafter referred to as the L level or referred to as 0B when expressed as data), the AND gate 21 is at the L level. Is output. As described above, the detection circuit 20 including the AND gate 21 outputs the initial value stored in the register 10
All of the initial data corresponding to the upper bits are all 1B
Is detected.

The clock supply control circuit 30 comprises an AND gate 31 having two inputs and one output and an inverter 32. Signal N1 is input to inverter 32. AN
A clock signal CLK and an inverter 32
Is output. Therefore, when the output signal of inverter 32 is at the H level, that is, when signal N1 output from the detection circuit is at the L level, AND gate 31 outputs a signal of a potential level in response to the potential level of clock signal CLK. When the output signal of the inverter 32 is at L level, that is, when the signal N1 output from the detection circuit is at H level, the AND gate 31 outputs a signal at L level.
Keep it. The signal output from the AND gate 31 is
It is supplied to some flip-flops used for executing the count corresponding to the higher-order bit among a plurality of flip-flops constituting the counting unit 100 described later.

As described above, the clock supply control circuit 30
Are clocks to some of the flip-flops included in the counting unit 100 that are used to execute the count corresponding to the upper bit, in accordance with the potential level of the signal N1 as the detection result of the detection circuit 20. Signal C
It controls the supply of LK.

The counting section 100 comprises four JK flip-flops (hereinafter simply referred to as flip-flops) 101-1 to 101-4 and nine 2-input / 1-output selection circuits 10
3-1 to 103-4, 104-1 to 104-4, 110
And four two-input one-output AND gates 105, 10
7, 109, and 113.

One input terminal (hereinafter, referred to as a 0-side input terminal) of the selection circuit 103-1 receives 1B as data, and the other input terminal (hereinafter, referred to as a 1-side input terminal) receives data. The signal R1 is input. Selection circuit 104
-1 is input to the 0-side input terminal as data and 1B is input to the 1-side input terminal as data. Each of the selection circuits 103-1 and 104-1 selects and outputs a signal (or data) input to one of the two input terminals according to the potential level of the set signal SET which is a control signal. .

In FIG. 1, selection circuits 103-1 to 103-1
03-4, 104-1 to 104-4, when the set signal SET is at the L level, the 0-side input terminal is selected, and when the set signal SET is at the H level,
It is assumed that the first input terminal is selected. For this reason,
When the set signal SET is at the L level, the selection circuit 103
-1 and the selection circuit 104-1 are both 1B as data.
Is output. When the set signal SET is at the H level, the selection circuit 103-1 outputs a signal of a potential level corresponding to the signal R1, and the selection circuit 104-1 outputs a signal corresponding to 0B as data.

The signal output from the selection circuit 103-1 is input to the J-side input terminal of the flip-flop 101-1 and the signal output from the selection circuit 104-1 is input to the K-side input terminal. The clock signal CLK is input to the clock terminal of the flip-flop 101-1. The flip-flop 101-1 receives the clock signal C
It operates according to either the rising edge or the falling edge of LK, but here,
Description will be made assuming that the operation is performed in response to the rising edge of the clock signal CLK. The other flip-flops 101-2 to 101-4, which will be described later, also receive the clock signal CLK.
Operates in response to either the rising edge or the falling edge of the clock signal CLK. However, here, the description will be made assuming that the operation is performed in response to the rising edge of the clock signal CLK.

Here, as is well known, the JK flip-flop is connected to the potential level (or data value) of the signal (or data) input to the J-side input terminal and to the K-side input terminal. If the potential level (or data value) of the signal (or data) is different,
In response to a rising edge of the clock signal CLK, a signal having a potential level (or data value) corresponding to a signal (or data) input to the J-side input terminal is output to the output terminal Q.
Output from. When an L-level signal (or 0B as data) is input to both the J-side input terminal and the K-side input terminal, the clock signal CL
In response to the rising edge of K, flip-flop 10
The signal OUT output from the output terminal Q of 1-1 itself.
The signal of the potential level maintaining the potential level of 1 is newly output from the output terminal Q as the signal OUT1.
When an H-level signal (or equivalent to 1B as data) is input to both the J-side input terminal and the K-side input terminal, the flip-flop 101-1 itself operates in response to the rising edge of the clock signal CLK. A signal having a potential level obtained by inverting the potential level of the signal OUT1 output from the output terminal Q is newly output from the output terminal Q as a signal OUT1.

For this reason, when the set signal SET is at the L level, 1B is input as data to both the J-side input terminal and the K-side input terminal.
A signal OUT1 is a signal OUT1 obtained by inverting the potential level of the signal output from the output terminal Q of the flip-flop 101-1 itself every time the clock signal CLK rises.
From the output terminal Q. When the set signal SET is at the H level, the signal R1 is substantially input to the J-side input terminal, and 0B is input to the K-side input terminal as data. In response to the rise of CLK, a signal corresponding to the potential level (or data value) of signal R1 is output from output terminal Q as signal OUT1.

The 0-side input terminal of the selection circuit 103-2 has
The signal OUT1 is input, and the signal R2 is input to the first input terminal.
Is entered. The signal OUT1 is input to the 0-side input terminal of the selection circuit 104-1, and 0B is input to the 1-side input terminal as data. Therefore, when the set signal SET is at the L level, both the selection circuit 103-2 and the selection circuit 104-2 output a signal corresponding to the signal OUT1. When the set signal SET is at the H level,
The selection circuit 103-2 outputs a signal of a potential level corresponding to the signal R2, and the selection circuit 104-2 outputs a signal corresponding to 0B as data.

The signal output from the selection circuit 102-2 is input to the J-side input terminal of the flip-flop 101-2, and the signal output from the selection circuit 104-2 is input to the K-side input terminal. The clock signal CLK is input to the clock terminal of the flip-flop 101-2.

Therefore, when the set signal SET is at the L level, a signal corresponding to the signal OUT1 is input to both the J-side input terminal and the K-side input terminal. That is, the signal O
When the UT1 is at the L level, the flip-flop 101-2 maintains the potential level of the signal OUT2 output from the output terminal Q of the flip-flop 101-2 itself at every rising of the clock signal CLK. Is newly output from the output terminal Q as a signal OUT2. When the signal OUT1 is at the H level, the flip-flop 101-2 renews a signal obtained by inverting the potential level of the signal OUT2 output from the output terminal Q of the flip-flop 101-2 itself at every rise of the clock signal CLK. At the output terminal Q as a signal OUT2. When the set signal SET is at the H level, the signal R2 is substantially input to the J-side input terminal and 0B is input to the K-side input terminal as data. CL
In response to the rise of K, a signal corresponding to the potential level (or data value) of signal R2 is output from output terminal Q as signal OUT2.

The AND gate 105 has a signal OUT 1,
OUT2 is input. Therefore, the signal O
When both UT1 and OUT2 are at H level, AND gate 105 outputs signal N2 at H level. When one or both of the signals OUT1 and OUT2 are at L level, the AND gate 105 outputs the signal N2 at L level.
Is output.

The 0-side input terminal of the selection circuit 103-3 includes:
The signal N2 is input, and the signal R3 is input to the first input terminal. The signal N2 is input to the 0-side input terminal of the selection circuit 104-3, and 0B is input to the 1-side input terminal as data. Therefore, the set signal SE
When T is at the L level, both the selection circuit 103-3 and the selection circuit 104-3 output a signal corresponding to the signal N2. When the set signal SET is at the H level, the selection circuit 1
03-3 outputs a signal of a potential level corresponding to the signal R3, and the selection circuit 104-3 outputs a signal corresponding to 0B as data.

The signal output from the selection circuit 103-3 is input to the J-side input terminal of the flip-flop 101-3, and the signal output from the selection circuit 104-3 is input to the K-side input terminal. The output signal of the AND gate 31, which is the output signal of the clock supply control circuit 30, is input to the clock terminal of the flip-flop 101-3.

The flip-flop 101-3 performs a normal operation if the output signal of the AND gate 31 is in response to the clock signal, and the flip-flop 101-3 maintains the L level of the output signal of the AND gate 31. In this case, the operation is prohibited. Here, the flip-flop 101-3
Performs a normal operation.

When the set signal SET is at L level, J
A signal corresponding to the signal N2 is input to both the side input terminal and the K side input terminal. That is, when the signal N2 is at the L level, the flip-flop 101-3 is turned on every time the clock signal CLK rises.
A signal having a potential level that maintains the potential level of the signal OUT3 output from its own output terminal Q is newly added to the signal OU.
The signal is output from the output terminal Q as T3. Signal N
2 is at H level, flip-flop 101-3
Means that a signal obtained by inverting the potential level of the signal OUT3 output from the output terminal Q of the flip-flop 101-3 itself is output as a new signal OUT3 from the output terminal Q every time the clock signal CLK rises. When the set signal SET is at the H level, the signal R3 is substantially input to the J-side input terminal, and 0B is input to the K-side input terminal as data. In response to the rise of CLK, a signal corresponding to the potential level (or data value) of the signal R3 is output from the output terminal Q as the signal OUT3.

The signal OUT3 and the signal N2 are input to the AND gate 113, respectively. Therefore, when both the signal OUT3 and the signal N2 are at H level, AND
Gate 113 outputs an H-level signal. In addition, one or both of the signal OUT3 and the signal N2 are at L
At the time of the level, the AND gate 113 outputs an L level signal.

The 0-side input terminal of the selection circuit 103-4 has
A signal output from the AND gate 113 is input, and 1
The signal R4 is input to the side input terminal. The signal output from the AND gate 113 is input to the 0-side input terminal of the selection circuit 104-4, and 0B is input to the 1-side input terminal as data. Therefore, when the set signal SET is at the L level, both the selection circuit 103-4 and the selection circuit 104-4 output a signal corresponding to the signal output from the AND gate 113. Set signal SE
When T is at the H level, the selection circuit 103-4 outputs the signal R4
, And the selection circuit 1044 outputs a signal corresponding to 0B as data.

The signal output from the selector 103-4 is input to the J-side input terminal of the flip-flop 101-4, and the signal output from the selector 104-4 is input to the K-side input terminal. The output signal of the AND gate 31, which is the output signal of the clock supply control circuit 30, is input to the clock terminal of the flip-flop 101-3.

The flip-flop 101-4 performs a normal operation if the output signal of the AND gate 31 is in accordance with the clock signal, and the flip-flop 101-4 maintains the L level of the output signal of the AND gate 31. In this case, the operation is prohibited. Here, the flip-flop 101-4
Performs a normal operation.

When the set signal SET is at L level, J
AND gate 1 is connected to both the input terminal on the K side and the input terminal on the K side.
A signal corresponding to the 13 output signals is input. That is,
When the output signal of the AND gate 113 is at the L level, the flip-flop 101-4 maintains the potential level of the signal OUT4 output from the output terminal Q of the flip-flop 101-4 at every rise of the clock signal CLK. The signal of the potential level is newly output from the output terminal Q as the signal OUT4. AND gate 11
3 is at the H level, the flip-flop 1
01-4 is to output a signal obtained by inverting the potential level of the signal OUT4 output from the output terminal Q of the flip-flop 101-4 itself as a new signal OUT4 from the output terminal Q every time the clock signal CLK rises. Becomes When the set signal SET is at the H level, J
Since the signal R4 is substantially input to the input terminal on the side and 0B is input as data to the input terminal on the K side, the flip-flop 101-4 sets the potential level of the signal R4 in response to the rise of the clock signal CLK. A signal corresponding to (or the value of the data) is output from the output terminal Q as the signal OUT4.

As described above, the selection circuits 103-1 to 103-1
-4, 104-1 to 104-4, flip-flop 10
Counting of 4 bits is performed by 1-1 to 101-4 and AND gates 105 and 113. More specifically, when the set signal SET is at the H level, the flip-flops 101-1 to 101-4 output the signals R1 to R4, respectively.
4 can be stored and output according to the potential level. As a result, the initial value is stored in the counting unit 100. After that, the set signal SET is set to the L level, and the flip-flops 101-1 to 101-4 operate according to the rising edge of the clock signal CLK to realize the count operation. When the signals R3 and R4 corresponding to the initial data of the upper bits both correspond to 1B as data, the clock signal C
Flip flops 101-3, 101 not supplied with LK
-4 Each operation is prohibited.

The AND gate 107 has a signal OUT3,
OUT4 is input. Therefore, the signal O
When both UT3 and OUT4 are at H level, AND gate 107 outputs a signal at H level. Also, the signal OU
When one or both of T3 and OUT4 are at L level, AND gate 107 outputs an L level signal.

The AND gate 109 has the signals N2 and A
The signal output from the ND gate 107 is input. Therefore, when both the signal N2 and the signal output from the AND gate 107 are at the H level, the AND gate 1
09 outputs an H level signal N3. Also, the signal N2
And either one or both of the signals output from the AND gate 107 are at the L level.
9 outputs an L level signal N3.

The selection circuit 110 has a signal N2 and a signal N3.
Are entered. Further, a signal N1 is input as a signal for controlling selection. Therefore, for example, in FIG. 1, when the signal N1 is at the L level, that is, when the initial data of one or both of the signals R3 and R4 is equivalent to 0B, the selection circuit 110 outputs the signal N3. The corresponding signal is output as carry signal CARRY. When the signal N1 is at the H level, that is, when the initial data of the signals R3 and R4 both correspond to 1B, the signal corresponding to the signal N2 is changed to the carry signal C.
Output as ARRY.

AND gates 107 and 109, selection circuit 1
In the overall configuration of No. 10, the case where the initial data for the upper bits are all equivalent to 1B (signal N1
Is H level), the flip-flop 10
When the data output by each of 1-1 and 101-2 is 1B, the carry signal CARRY of the H level is output. In addition, when there is data corresponding to 0B in the initial data corresponding to the upper bits (corresponding to the case where the signal N1 is at the L level), when the data output from each of the flip-flops 101-1 to 101-4 is 1B, H A level carry signal CARRY is output.

The counting circuit 11 configured as described above
Operation 1 will be described in detail below. FIG. 2 shows the first
9 is a timing chart illustrating an operation of the count circuit 111 according to the embodiment. FIG. 2 is an operation example when the initial value set in the count circuit 111 is 0000B. In FIG. 2, CLK is a clock signal C
LK, SET is a set signal SET, and R1 to R4 are signals R1 to R4 which are output signals of the register 10, respectively.
N1 is a signal N1 output from the detection circuit 20,
T1 to OUT4 are flip-flops 101-1 to 101
-4 are the outputs OUT1 to OUT4, and N2 is A
The signal N2 output from the ND gate 105 and the signal N3
The signal N3, which is the output of the D gate 109, and CARRY indicate the carry signal CARRY.

First, before time t0, the set signal SET
Becomes H level. Therefore, the selection circuits 103-1 to 103-1
Each of 03-4 and 104-1 to 104-4 selects a signal input from the 1-side input terminal as an output. Note that the output signals OUT1 to OUT4 of the flip-flops 101-1 to 101-4 before the time t0 are at the L level.

In response to the rising edge of clock signal CLK at time t0, flip-flop 101-1
Signals corresponding to the signals R1 to R4 are stored as initial data for setting initial values of the counts in the signals 101 to 104, respectively, and are output as the signals OUT1 to OUT4. Since the initial value is 0000B, the signals R1 to R4 are all at L level. Therefore, the flip-flop 101
The output signals OUT1 to OUT4 of -1 to 101-4 remain at the L level, respectively.

Before time t1, set signal SET goes low. Therefore, each of the selection circuits 103-1 to 103-4 and 104-1 to 104-4 selects a signal input from the 0-side input terminal as an output.

In response to the rising edge of the clock signal CLK at the time t1, the flip-flops 101-1 to 101-4 each have a potential level corresponding to the potential level of the signal input to the J-side input terminal and the K-side input terminal. Are output as signals OUT1 to OUT4.
As described above, since the initial value is 0000B, the signal N1 which is the output of the detection circuit 20 is at the L level, so that the output signal of the clock supply control circuit 30 corresponds to the clock signal CLK. For this reason, the flip-flops 101-3 and 101-4 both perform normal operations. The selection circuit 110 also selects the signal N3 input to the 0-side input terminal as an output.

At time t2, the count becomes 10B, and in response to the rising edge of clock signal CLK at time t3, output signal OUT1 from flip-flop 101-1 becomes H level, and the count becomes 11
B. Therefore, the output signal N of the AND gate 105
2 becomes H level. However, the output signals OUT3, OUT4 of the flip-flops 101-3, 101-4
Are both at L level, and the output signal of AND gate 107 is at L level. Therefore, the AND gate 109
Carry signal CARRY is maintained at the L level.

Thereafter, from time t4 to t6, the counts become 100B, 101B, and 110B, respectively. In response to the rising edge of clock signal CLK at time t7, output signal O from flip-flop 101-1 is output.
UT1 becomes H level, and the count number becomes 111B. Therefore, the output signal N2 of the AND gate 105 becomes H
Level. However, flip-flop 101
−4 output signal OUT4 is at L level,
The output signal of gate 107 is at L level. Therefore, A
Since output signal N3 of ND gate 109 remains at L level, carry signal CARRY is maintained at L level.

Thereafter, from time t8 to t10, the counts become 1000B, 1001B and 1010B, respectively. In response to the rising edge of the clock signal CLK at the time t11, the output signal OUT1 from the flip-flop 101-1 becomes H level, and the count number becomes 10
11B. Therefore, the output signal N2 of the AND gate 105 becomes H level. However, since the output signal OUT3 of the flip-flop 101-3 is at the L level, the output signal of the AND gate 107 is at the L level.
Therefore, output signal N3 of AND gate 109 remains at L level, and carry signal CARRY is maintained at L level.

Thereafter, from time t12 to t14, the counts become 1100B, 1101B, and 1110B, respectively. In response to the rising edge of the clock signal CLK at the time t15, the output signal OUT1 from the flip-flop 101-1 becomes H level, and the count number becomes 1
111B. Therefore, the output signal N2 of the AND gate 105 becomes H level. Also, flip-flop 1
Since the output signals OUT3 and OUT4 of 01-3 and 104-4 are both at H level, the output signal of the AND gate 107 is at H level. Therefore, output signal N3 of AND gate 109 attains H level, and carry signal CARRY
Becomes H level.

Next, the clock signal C at time t16
Output signals OUT1 to OUT4 of the flip-flops 101-1 to 101-4 according to the rising edge of LK.
Become L level, and the count number returns to 0000B. Therefore, carry signal CARRY is also L
Level. After time t17, the same operation as after time t1 is performed.

As described above, when the initial data for the predetermined upper bits in the initial value is not all 1B, such as when the initial value is 0000B, the operation can be performed in the same manner as a normal 4-bit counter.

Next, an example in which the initial data for the predetermined upper bits are all 1B will be described. FIG. 3 is a timing chart for explaining the operation of the count circuit 111 according to the first embodiment. FIG. 3 is an operation example when the initial value set in the count circuit 111 is 1100B.

First, before time t0, the set signal SET
Becomes H level. Therefore, the selection circuits 103-1 to 103-1
Each of 03-4 and 104-1 to 104-4 selects a signal input from the 1-side input terminal as an output. Note that the output signals OUT1 to OUT4 of the flip-flops 101-1 to 101-4 before the time t0 are at the L level.

In response to the rising edge of clock signal CLK at time t0, flip-flop 101-1
And 101-2 store signals corresponding to the signals R1 and R2 as initial data for setting the initial value of the count, respectively, and output them as signals OUT1 and OUT2.
Since the initial value is 1100B, the flip-flops 101-3 and 101-4 do not operate. Therefore, the output signal OUT of the flip-flops 101-3 and 101-4
3, OUT4 remains at the L level.

Before time t1, set signal SET goes low. Therefore, each of the selection circuits 103-1 to 103-4 and 104-1 to 104-4 selects a signal input from the 0-side input terminal as an output.

In response to the rising edge of the clock signal CLK at the time t1, the flip-flops 101-1 to 101-4 each have a potential level corresponding to the potential level of the signal input to the J-side input terminal and the K-side input terminal. Are output as signals OUT1 to OUT4.
As described above, since the initial value is 1100B, the signal N1 which is the output of the detection circuit 20 becomes H level, so that the output signal of the clock supply control circuit 30 is maintained at L level. Therefore, the flip-flop 101-3,
Since the clock 101 is not supplied with the clock signal CLK and the normal operation is prohibited, the output signal OU is not output.
T3 and OUT4 maintain the L level. That is, the time t
From 1, the counting operation from the initial value 1100 is started in the flip-flops 101-1 and 101-2. In other words, this is equivalent to starting the counting operation from the initial value 00B with two flip-flops. The selection circuit 110 selects the signal N2 input to the first input terminal as an output.

At time t2, the count number becomes 10B, and in response to the rising edge of clock signal CLK at time t3, output signal OUT1 from flip-flop 101-1 becomes H level, and the count number becomes 11
B. Therefore, the output signal N of the AND gate 105
2 becomes H level. Therefore, carry signal CARRY attains H level.

Thereafter, if the initial value stored in the register 10 remains at 1100B, the flip-flop 1
The operations of 01-3 and 101-4 remain prohibited.
Therefore, as shown from time t4 to time t7, the counting unit 100
Can operate in the same manner as the two-bit counter composed of the flip-flops 101-1 and 101-2, similarly to the time t0 to t3.

Thereafter, between time t8 and time t9, the initial value stored in register 10 is 1100B.
Is changed to 0000B. For this reason, the signal N1 output from the detection circuit 20 becomes L level, and the output signal of the clock supply control circuit 30 becomes the clock signal CL.
A signal corresponding to K is obtained. Therefore, the flip-flop 1
Both 01-3 and 101-4 can perform normal operations.

In FIG. 3, the initial value newly stored in the register 10 is 0000B, and the output signals OUT3 and OUT4 from the flip-flops 101-3 and 101-4 are both at the L level. It is assumed that there is no need to store a new initial value. When the initial value newly stored in the register 10 needs to be newly stored in each of the flip-flops 101-1 to 101-4 such as 0100B, the time t
Before the time t9, the set signal SET is set to the H level, and at time t9
The initial value newly stored in the register 10 may be stored in each of the flip-flops 101-1 to 101-4.

In FIG. 3, after time t9, the flip-flops 101-1 to 101-4 operate as 4-bit counters, so that the same operations as those after time t1 in FIG. 2 are executed.

As described above, when all of the predetermined upper bits in the initial value are 1B, the supply of the clock signal CLK to the flip-flop that counts the predetermined higher bits that do not need to operate does not operate. hand,
The count operation is performed only by flip-flops that need to operate. Even in this case, the counting unit 10
Carry signal CARRY can be set to H level at the same count number as when all flip-flops constituting 0 are operated.

As described above, the count circuit 111 of the first embodiment realizes a reduction in power consumption without impairing the functionality as a counter.

In the first embodiment, a 4-bit counter has been described as an example. However, the present invention is not limited to this, and is an n-bit counter (where n is a positive integer of 2 or more). Is also good. Further, in the first embodiment, the predetermined upper bits to be detected by the detection circuit 20 are set to the upper two bits from the most significant bit including the most significant bit.
However, the present invention is not limited to this, and the uppermost k bits including the most significant bit and the upper k bits (where k is n
> K positive integer). In consideration of efficient use of the functions of the present invention and reduction of power consumption, k ≦ n / 2 is preferable. Because k> n /
This is because, in the case of 2, there are few cases where an initial value for using the function of the present invention is given.

Next, a count circuit according to a second embodiment of the present invention will be described below with reference to the drawings.
FIG. 4 is a circuit diagram of the count circuit according to the first embodiment of the present invention. The count circuit shown in FIG. 4 will be described by taking a 4-bit count circuit (corresponding to one that counts 16 in decimal system) as an example, as in the first embodiment. In FIG. 4, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and the description thereof will be omitted, and the description will not be repeated.

In FIG. 4, a counting circuit 222 includes a counting section 200 for performing a counting operation, a detection circuit 230,
1 as a storage circuit, an initial data control circuit 250 for controlling an initial value supplied to the counting unit 200, and a selection circuit 271 as a clock selection circuit
It is composed of Note that each of the register 10, the detection circuit 230, the initial data control circuit 250, and the selection circuit 271 may be a peripheral circuit provided around the count circuit 222, but here, the register 10, the counting section 200, and the detection circuit 230 And the initial data control circuit 25
0 and the selection circuit 271 will be described as circuits constituting the count circuit 222.

The detection circuit 230 includes, for example, the inverter 2
31. Inverter 231 has signal R
1 has been entered. That is, the inverter 231 sets the least significant bit of the initial value stored in the register 10 to 0.
At the time of B, an H-level signal is output, and when the least significant bit of the initial value is 1B, an L-level signal is output.

The initial data control circuit 250 includes, for example, 4
It is composed of two selection circuits 251 to 254. The signal R1 is input to the 0-side input terminal of the selection circuit 251 and 1
The signal R2 is input to the side input terminal. Selection circuit 2
The signal R2 is input to the 0-side input terminal and the signal R3 is input to the 1-side input terminal. The signal R3 is input to the 0-side input terminal of the selection circuit 253, and the signal R4 is input to the 1-side input terminal. The signal R4 is input to the 0-side input terminal of the selection circuit 254, and the output signal from the register 273 is input to the 1-side input terminal. Note that a signal corresponding to 1B (H level signal) is stored as data from the register 273, and a signal corresponding to 1B is constantly output as data.

The output signal JV of the inverter 231 is input to each of the selection circuits 251 to 254 as a signal for selectively controlling the output signals of the selection circuits 251 to 254. Therefore, when the signal JV is at the L level, the selection circuits 251-2
Each outputs a signal input to the 0-side input terminal as an output signal. When the signal JV is at the H level, each of the selection circuits 251 to 254 outputs a signal input to the first input terminal as an output signal.

That is, when the least significant bit of the initial value stored in the register 10 is 0B, the initial data control circuit 250 sets the initial data for the most significant bit to 1B, and sets a flip-flop constituting the counting unit 200 described later. The initial data for the X-th flip-flop (where X is a positive integer of 4 ≧ X ≧ 2) is (X
-1) Output as initial data for the flip-flop. When the least significant bit of the initial value stored in the register 10 is 1B, the initial data control circuit 250 outputs the signals R1 to R4 as they are.

Selection circuit 27 constituting clock selection circuit
A first clock signal CLK that repeats an H level and an L level at a predetermined cycle is input to the 0-side input terminal of 1 and 1
The second input clock signal CLK / 2, which divides the first clock signal CLK and repeats the H level and the L level at twice the cycle of the first clock signal CLK, is input to the side input terminal.

The signal JV is input as a signal for selectively controlling the output signal of the selection circuit 271. Therefore, when the signal JV is at the L level, the selection circuit 271 outputs the signal input to the 0-side input terminal as the output signal SECLK. When the signal JV is at the H level, the selection circuit 271 outputs the signal input to the first input terminal as the output signal SECLK.

That is, when the least significant bit of the initial value stored in the register 10 is 0B, the signal SECLK is a signal corresponding to the second clock signal CLK / 2.
When the least significant bit of the initial value stored in the register 10 is 1B, the signal SECLK is a signal corresponding to the first clock signal CLK.

The counting section 200 includes four JK flip-flops 201-1 to 201-4, eight selection circuits 203-1 to 203-4, 204-1 to 204-4, and three ANs.
D gates 205, 207, and 209 are provided.

The 0-side input terminal of the selection circuit 203-1 has:
1B is input as data, and the output signal of the selection circuit 251 is input to the first input terminal. Selection circuit 20
In the 4-1 0-side input terminal, 1B is input as data, and in the 1-side input terminal, 0B is input as data. The selection circuits 203-1 and 204-1 both select and output a signal (or data) input to one of the two input terminals in accordance with the potential level of the set signal SET which is a control signal. .

In FIG. 4, similarly to FIG. 1, in any of the selection circuits 203-1 to 203-4 and 204-1 to 204-4, when the set signal SET is at the L level, the 0 side input terminal is When the set signal SET is at the H level, the 1-side input terminal is selected. Therefore, when the set signal SET is at the L level,
Both the selection circuit 203-1 and the selection circuit 204-1 output a signal corresponding to 1B as data. When the set signal SET is at the H level, the selection circuit 203-1 outputs a signal of a potential level corresponding to the output signal of the selection circuit 251, and the selection circuit 204-1 outputs a signal corresponding to 0B as data.

The signal output from the selection circuit 203-1 is input to the J-side input terminal of the flip-flop 201-1 and the signal output from the selection circuit 204-1 is input to the K-side input terminal. The signal SECLK is input to a clock terminal of the flip-flop 201-1. The flip-flop 201-1 operates in response to either the rising edge or the falling edge of the signal SECLK.
The description will be made assuming that the operation is performed according to the rising edge of ECLK. Note that another flip-flop 20 described later is used.
Although 1-2 to 201-4 also operate in response to either the rising edge or the falling edge of the signal SECLK, here, it is assumed that they operate in response to the rising edge of the signal SECLK.

When the set signal SET is at the L level, J
1 is used as data for both the
Since B is input, the flip-flop 201-1 becomes
Each time the signal SECLK rises, the flip-flop 2
A signal obtained by inverting the potential level of the signal output from its own output terminal Q is output from the output terminal Q as a signal OUT1. When the set signal SET is at the H level, the output signal from the selection circuit 251 is substantially input to the J-side input terminal, and 0B is input to the K-side input terminal as data.
01-1 is a signal R1 or a signal R1 which is an output signal of the selection circuit 251 in response to the rise of the signal SECLK.
A signal corresponding to the potential level of 2 (or the value of the data) is output from the output terminal Q as the signal OUT1.

The 0-side input terminal of the selection circuit 203-2 has
The signal OUT1 is input, and an output signal of the selection circuit 252 is input to a first input terminal. The signal OUT1 is input to the 0-side input terminal of the selection circuit 204-1, and 0B is input to the 1-side input terminal as data. For this reason, when the set signal SET is at the L level, both the selection circuits 203-2 and 204-2 output the signal OU.
A signal corresponding to T1 is output. Set signal SET is H
At the time of the level, the selection circuit 203-2 is connected to the selection circuit 252.
, And the selection circuit 204-2 outputs a signal corresponding to 0B as data.

The signal output from the selection circuit 202-2 is input to the J-side input terminal of the flip-flop 201-2, and the signal output from the selection circuit 204-2 is input to the K-side input terminal. The signal SECLK is input to a clock terminal of the flip-flop 201-2.

Therefore, when the set signal SET is at the L level, a signal corresponding to the signal OUT1 is input to both the J-side input terminal and the K-side input terminal. That is, the signal O
When the UT1 is at the L level, the flip-flop 201-2 outputs a signal of a potential level that maintains the potential level of the signal OUT2 output from the output terminal Q of the flip-flop 201-2 at every rise of the signal SECLK. The signal is newly output from the output terminal Q as the signal OUT2. If the signal OUT1 is at the H level, the flip-flop 201-2 renews a signal obtained by inverting the potential level of the signal OUT2 output from the output terminal Q of the flip-flop 201-2 at every rise of the signal SECLK. The signal OUT2 is output from the output terminal Q. When the set signal SET is at the H level, the output signal of the selection circuit 252 is substantially input to the J-side input terminal, and 0B is input to the K-side input terminal as data. Is the signal S
In response to the rising edge of ECLK, a signal corresponding to the potential level (or data value) of signal R2 or signal R3 is output from output terminal Q as signal OUT2.

The AND gate 205 has a signal OUT 1,
OUT2 is input. Therefore, the signal OUT1,
When both OUT2 are at H level, AND gate 205
Outputs an H level signal. Also, the signals OUT1, O
When one or both of UT2 are at L level,
AND gate 205 outputs an L-level signal.

The 0-side input terminal of the selection circuit 203-3 has
An output signal of the AND gate 205 is input, and an output signal of the selection circuit 253 is input to a first input terminal.
The output signal of the AND gate 205 is input to the 0-side input terminal of the selection circuit 204-3, and 0B is input to the 1-side input terminal as data. Therefore, when the set signal SET is at the L level, both the selection circuits 203-1 and 204-2 output a signal corresponding to the output signal of the AND gate 205. When the set signal SET is at the H level, the selection circuit 203-1 outputs a signal of a potential level corresponding to the signal R3 or the signal R4 as an output signal of the selection circuit 253, and the selection circuit 204-2 corresponds to 0B as data. Output a signal.

The signal output from the selection circuit 203-1 is input to the J-side input terminal of the flip-flop 201-3, and the signal output from the selection circuit 204-3 is input to the K-side input terminal. The signal SECLK is input to a clock terminal of the flip-flop 201-3.

When the set signal SET is at L level, J
An AND gate 2 is connected to both input terminals
A signal corresponding to the output signal 05 is input. That is,
If the output signal of the AND gate 205 is at the L level, the flip-flop 201-3 maintains the potential level of the signal OUT3 output from the output terminal Q of the flip-flop 201-3 at every rise of the signal SECLK. The signal of the potential level is newly output from the output terminal Q as the signal OUT3. If the output signal of AND gate 205 is at H level, flip-flop 201
-3 outputs a signal obtained by inverting the potential level of the signal OUT3 output from the output terminal Q of the flip-flop 201-3 itself as a new signal OUT3 from the output terminal Q every time the signal SECLK rises. . When the set signal SET is at the H level, the output signal of the selection circuit 253 is substantially input to the J-side input terminal,
Since 0B is input as data to the K-side input terminal,
The flip-flop 201-3 outputs the signal R output from the selection circuit 253 in response to the rise of the signal SECLK.
3 or a signal corresponding to the potential level (or data value) of the signal R4 is output from the output terminal Q as the signal OUT3.

The signal OUT 3 and the output signal of the AND gate 205 are input to the AND gate 207. Therefore, the signal OUT3 and the AND gate 205
Are both at the H level, the AND gate 20
7 outputs an H level signal NX. Also, the signal OUT
3 and one or both of the output signals of the AND gate 205 are at the L level, the AND gate 207 becomes the L level.
The level signal NX is output.

The 0-side input terminal of the selection circuit 203-4 has
The signal NX is input, and the selection circuit 25 is
4 is input. The signal NX is input to the 0-side input terminal of the selection circuit 204-4, and 0B is input to the 1-side input terminal as data. For this reason,
When the set signal SET is at the L level, the selection circuit 203
-4 and the selection circuit 204-4 both output a signal corresponding to the signal NX. When the set signal SET is at the H level, the selection circuit 203-4 outputs 1B as a signal of a potential level corresponding to the signal R4 or 1B as data stored in the register 273 as an output signal of the selection circuit 254. Outputs a signal corresponding to 0B as data.

The signal output from the selection circuit 203-4 is input to the J-side input terminal of the flip-flop 201-4, and the signal output from the selection circuit 204-4 is input to the K-side input terminal. The signal SECLK is input to the clock terminal of the flip-flop 201-4.

When the set signal SET is at the L level, J
A signal corresponding to the signal NX is input to both the side input terminal and the K side input terminal. That is, when the signal NX is at the L level, the flip-flop 201-4 outputs the signal SECL.
Each time K rises, a signal of a potential level that maintains the potential level of the signal OUT4 output from the output terminal Q of the flip-flop 201-4 itself is newly added to the signal OUT4.
Is output from the output terminal Q. When the signal NX is at the H level, the flip-flop 201-4 causes the flip-flop 20-4 to rise every time the signal SECLK rises.
The signal OUT output from the output terminal Q of 1-4 itself.
4 is output from the output terminal Q as a new signal OUT4. When the set signal SET is at the H level, the output signal of the selection circuit 254 is substantially input to the J-side input terminal, and 0B is input to the K-side input terminal as data. Outputs a signal corresponding to the potential level (or data value) of the signal R4 output from the selection circuit 254 or a signal corresponding to 1B as data from the output terminal Q in response to the rise of the signal SECLK. .

The signal OUT4 and the signal NX are input to the AND gate 209. Therefore, when both the signal OUT4 and the signal NX are at the H level, AND
Gate 209 outputs an H level signal. Further, one or both of the signal OUT4 and the signal NX are at L level.
At the time of the level, the AND gate 209 outputs an L level signal. The output signal of the AND gate 209 becomes the carry signal CARRY of the count circuit 222.

As described above, the selection circuits 203-1 to 203-3
-4, 204-1 to 204-4, flip-flop 20
4-bit counts are performed by 1-1 to 201-4 and AND gates 205 and 207. More specifically, when the set signal SET is at the H level, each of the flip-flops 201-1 to 201-4 is connected to the selection circuit 25.
Signals corresponding to the potential levels of the signals output from 1 to 254 can be stored and output. Thus, the initial value is stored in the counting unit 200.

The initial value stored in the counting section 200 depends on the value of the least significant bit of the initial value stored in the register 10.

More specifically, when the least significant bit of the initial value corresponds to 1B as data, the output signal JV of the detection circuit 230 goes low, so that it is output from the register 10 as signals R1 to R4. The initial data is output directly from the initial data control circuit 250. Therefore, the initial data output from the register 10 as the signals R1 to R4 are stored in the flip-flops 201-1 to 201-4, respectively.
For example, if the initial value stored in the register 10 is 0001B
, The flip-flop 201-1 has 1B as initial data, and the flip-flops 201-2 to 201-2.
0B is stored in 201-4 as initial data. When the least significant bit of the initial value corresponds to 1B as data, the output signal SECLK of the selection circuit 271 becomes the first signal.
In response to the clock signal CLK.

The least significant bit of the initial value is 0B as data.
, The output signal JV of the detection circuit 230 goes to the H level.
Are output as signals R2 to R4,
And the data stored in the register 273 are output from the initial data control circuit 250. Therefore, the initial data output as the signals R2 to R4 and the data stored in the register 273 are stored in the flip-flops 201-1 to 201-4, respectively.
For example, if the initial value stored in the register 10 is 0010B
, The flip-flop 201-1 has 1B as initial data, the flip-flop 201-2,
0B is stored as initial data in 201-3, and 1B of output data from the register 273 is stored in flip-flop 201-4 as initial data. When the least significant bit of the initial value corresponds to 0B as data, the output signal SECLK of the selection circuit 271 corresponds to the second clock signal CLK / 2.

After that, the set signal SET is set to the L level, and the count circuit 222 responds to the rising edge of the signal SECLK by using the flip-flops 201-1 to 201-2.
01-4 operates to implement the counting operation.

In terms of the entire configuration of the AND gates 205, 207, and 209, the flip-flops 201-1 to 201-2
When all the data output from 01-4 are 1B,
AND-level carry signal CARR from AND gate 209
Outputs Y.

The counting circuit 22 configured as described above
Operation 2 will be described in detail below. FIG. 5 shows the second
9 is a timing chart illustrating an operation of the count circuit 222 according to the embodiment. FIG. 5 is an operation example when the initial value set in the count circuit 222 is 0001B. In FIG. 5, CLK represents the first clock signal CLK, and CLK / 2 represents the second clock signal CLK.
/ 2, SECLK is the output signal SEC of the selection circuit 271
LK, SET is a set signal SET, and R1 to R4 are signals R1 to R4 which are output signals of the register 10, respectively.
And JV is the signal JV output from the detection circuit 230,
UT1 to OUT4 are flip-flops 201-1 to 20-1
Signals OUT1 to OUT4, which are outputs of 1-4, and signal NX, which is an output of AND gate 207, is output from CARR.
Y indicates the carry signal CARRY.

First, before time t0, set signal SET
Becomes H level. Therefore, the selection circuits 203-1 to 203-2
Each of 03-4 and 204-1 to 204-4 selects a signal input from the first input terminal as an output. Note that the output signals OUT1 to OUT4 of the flip-flops 201-1 to 201-4 before the time t0 are at the L level. In addition, since the initial value is 0001B, the output signal SECLK of the selection circuit 271 corresponds to the first clock signal CLK.

In response to the rising edge of signal SECLK at time t0, flip-flops 201-1 to 201-2
01-4 stores data corresponding to the output signal from the initial data control circuit 250 as initial data for setting an initial value of the count. In the case of FIG. 5, since the output signal JV of the detection circuit 230 is at the L level, signals corresponding to the signals R1 to R4 are stored in the flip-flops 201-1 to 201-4, respectively, and the signals OUT1 to OUT4 are stored.
Output as OUT4. Since the initial value is 0001B, the output signal OU of the flip-flop 201-1 is output.
T1 becomes H level and flip-flops 201-2 to 201-2
The output signals OUT2 to OUT4 of 201-4 are L
Remains at the level.

Before time t1, set signal SET attains an L level. Therefore, each of the selection circuits 203-1 to 203-4 and 204-1 to 204-4 selects a signal input from the 0-side input terminal as an output.

In response to the rising edge of signal SECLK at time t1, each of flip-flops 201-1 to 201-1
201-4 outputs signals having potential levels corresponding to the potential levels of the signals input to the J-side input terminal and the K-side input terminal, respectively, as signals OUT1 to OUT4. Note that, as described above, the output signal SEC of the selection circuit 271 is output.
Since LK is in response to the first clock signal CLK, each of the flip-flops 201-1 to 201-4 performs a normal operation substantially in response to the rising edge of the first clock signal CLK. .

In response to the rising edge of signal SECLK at time t2, output signal OUT1 from flip-flop 201-1 attains an H level, and the count number becomes one.
1B. Therefore, the output signal of the AND gate 205 becomes H level. However, flip-flop 2
Since the output signals OUT3 and OUT4 of 01-3 and 201-4 are both at the L level, the output signal NX of the AND gate 207 and the carry signal CARRY output from the AND gate 209 are maintained at the L level.

Thereafter, from time t3 to time t5, the counts become 100B, 101B, and 110B, respectively. In response to the rising edge of signal SECLK at time t6, output signal OUT from flip-flop 201-1
1 becomes H level, and the count number becomes 111B. Therefore, the output signal NX of the AND gate 207 becomes H level. However, the output signal OUT4 of the flip-flop 201-4 is at the L level. Therefore, carry signal CARRY output from AND gate 209 is maintained at the L level.

Thereafter, from time t7 to t9, the counts become 1000B, 1001B, and 1010B, respectively. In response to the rising edge of the signal SECLK at the time t10, the output signal OUT1 from the flip-flop 201-1 becomes H level, and the count number becomes 1011.
B. Therefore, the output signal of the AND gate 105 becomes H level. However, flip-flop 10
Since the output signal OUT3 of 1-3 is at L level,
Output signal NX of D gate 207 is at L level. Therefore, carry signal CAR output from AND gate 209 is output.
RY is maintained at the L level.

Thereafter, at times t11 to t13, the counts become 1100B, 1101B, and 1110B, respectively. In response to the rising edge of the signal SECLK at time t14, the output signal OUT1 from the flip-flop 201-1 becomes H level, and the count number becomes 111.
1B. Therefore, the output signal of the AND gate 205 becomes H level. At this time, the flip-flop 101
Since the output signals OUT3 and OUT4 of -3 and 104-4 are both at the H level, the output signal NX of the AND gate 207 is at the H level, and the carry signal CARRY output from the AND gate 209 is at the H level.

Next, signal SECLK at time t15
Of each flip-flop 20 in response to the rising edge of
The output signals OUT1 to OUT4 1-1 to 201-4 become L level, respectively, and the count number returns to 0000B. Therefore, carry signal CARRY is also at L level.

In response to the rising edge of signal SECLK at time t16, output signal OUT1 from flip-flop 201-1 goes high, and the count number becomes 1B. After time t17, the same operation as after time t1 is performed.

As described above, when the initial data for the least significant bit in the initial value is 1B, such as when the initial value is 0001B, it can operate as a 4-bit counter corresponding to the first clock signal CLK.

Next, an example in which the initial data for the least significant bit is 0B will be described. FIG. 6 is a timing chart for explaining the operation of the count circuit 222 according to the second embodiment. FIG. 6 is an operation example when the initial value set in the count circuit 222 is 1010B. The register 273 stores 1 as data in advance.
B is assumed to be stored.

First, before time t0, set signal SET
Becomes H level. Therefore, the selection circuits 203-1 to 203-2
Each of 03-4 and 204-1 to 204-4 selects a signal input from the first input terminal as an output. Note that the output signals OUT1 to OUT4 of the flip-flops 201-1 to 201-4 before the time t0 are at the L level. In addition, since the initial value is 1010B, the output signal SECLK of the selection circuit 271 corresponds to the second clock signal CLK / 2. Therefore, each of the flip-flops 201-1 to 201-4 performs a normal operation substantially according to the rising edge of the second clock signal CLK / 2.

In response to the rising edge of signal SECLK at time t0, flip-flops 201-1 to 201-2
01-4 stores data corresponding to the output signal from the initial data control circuit 250 as initial data for setting an initial value of the count. In the case of FIG. 6, since the output signal JV of the detection circuit 230 is at the H level, the flip-flops 201-1 to 201-4 store the signals corresponding to the signals R2 to R4 and the data stored in the register 273, respectively. It is stored and output as signals OUT1 to OUT4. Since the initial value is 1010B, the output signals OUT1, OUT3, and OUT4 of the flip-flops 201-1, 201-3, and 201-4 all become H level, and the output signal OU of the flip-flop 201-2 is output.
T2 is at the L level. In other words, the initial value 1010
The initial value 1101B is replaced by the flip-flop 20 instead of B.
1-1 to 201-4.

Before time t1, set signal SET attains an L level. Therefore, each of the selection circuits 203-1 to 203-4 and 204-1 to 204-4 selects a signal input from the 0-side input terminal as an output.

In response to the rising edge of signal SECLK at time t2, each of flip-flops 201-1 to 201-1
201-4 outputs signals having potential levels corresponding to the potential levels of the signals input to the J-side input terminal and the K-side input terminal, respectively, as signals OUT1 to OUT4. Note that, as described above, the output signal SEC of the selection circuit 271 is output.
Since LK is in response to the second clock signal CLK, each of the flip-flops 201-1 to 201-4 performs a normal operation substantially in response to the rising edge of the second clock signal CLK. . The count number at time t2 is 1110B.

In response to the rising edge of signal SECLK at time t4, output signal OUT1 from flip-flop 201-1 attains an H level, and the count number becomes one.
111B. Therefore, the output signal of the AND gate 205 becomes H level. At this time, flip-flop 1
Since the output signals OUT3 and OUT4 of 01-3 and 104-4 are both at H level, the output signal NX of the AND gate 207 becomes H level, and the carry signal CARRY output from the AND gate 209 becomes H level.

That is, after time t0 when the initial value is stored,
At time t2 and time t4, each flip-flop 201
By operating each of -1 to 201-4 twice, the carry signal CARRY becomes H level. Carry signal CA
RRY maintains the H level until time t6.

Here, consider the case where the initial value 1010B is stored in the counting section 200 at time t0 as it is, and the count operation is performed with the first clock signal CLK. In this case, the count number is 1011 at time t1.
B, 1100B at time t2, 1101B at time t3, 1110B at time t4, and 1111B at time t5. Therefore, carry signal CARRY attains H level at time t5.

As described above, according to the count circuit 222 in the second embodiment, the least significant bit of the initial value is 0.
In the case of B, even if the number of operations of the flip-flops 201-1 to 201-4 constituting the counting unit 200 is reduced, the carry signal CA is required at a necessary timing (time t5 in the above example).
RRY can be kept at the H level.

In FIG. 6, carry signal CARRY changes from the L level to the H level at time t4. However, when it is desired to change carry signal CARRY from the L level to the H level at time t5, for example, You can do as follows.

As shown in FIG. 7, D flip-flop 2
91, an inverter 293 and a 2-input / 1-output selection circuit 29
5 is provided on the output side of the carry signal CARRY in FIG. Carry signal CARRY is input to input terminal D of flip-flop 291. Flip-flop 29
The first clock signal CLK is input to one clock terminal. Reset terminal R of flip-flop 291
, A carry signal CARRY is input via an inverter 293.

The output signal of the flip-flop 291 is input to the 1-side input terminal of the selection circuit 295, and the carry signal CARRY is input to the 0-side input terminal. As a signal for selectively controlling the output of the selection circuit 295, the detection circuit 23
An output signal JV of 0 is input.

By providing the circuit of FIG. 7, the following output is possible. First, as shown in FIG. 5, when the least significant bit of the initial value is 1B, the signal JV is at the L level, so that the selection circuit 295 substantially outputs the carry signal CARRY as the output signal SECARRY. Become.
Therefore, if the signal SECARRY is handled as a carry signal of the count circuit 222, the count circuit 222
The operation of the timing chart shown in FIG.

Also, as shown in FIG. 6, when the least significant bit of the initial value is 0B, the signal JV goes to H level.
The selection circuit 295 outputs a signal corresponding to the output signal of the flip-flop 291 as the output signal SECARRY.

Here, from time t0 to time t3 shown in FIG. 6, since carry signal CARRY is at L level, flip-flop 291 is in a state where a signal at H level is inputted to reset terminal R. Therefore, the flip-flop 291 is maintained in the reset state, and does not operate even with the rising edge of the first clock signal CLK. Therefore, the output signal of the flip-flop 291 is maintained at the L level.

At time t4 shown in FIG. 6, carry signal CARRY attains H level, so that flip-flop 2
An L-level signal is input to the reset terminal R of 91,
The reset state is released. Here, the rising of the first clock signal CLK corresponds to the second clock signal CLK /
2 is synchronized with the change in the potential level of the second clock signal, and there is a delay corresponding to the counting operation in the counting unit 200 before the carry signal CARRY of the H level is transmitted to the flip-flop 291. Signal C
Flip-flop 2 for rising edge of LK
91 does not work.

At time t5 in FIG. 6, carry signal CARRY remains at H level, so that the output signal of flip-flop 291 goes to H level in response to the rising edge of first clock signal CLK. Therefore, the output signal SECARRY of the selection circuit 295 can be set to the H level. This signal SECARRY is handled as a carry signal of the count circuit 222.

Thereafter, at time t6, carry signal C
When ARRY goes low, flip-flop 291
Is reset again, so that the flip-flop 29
1 is at the L level. Therefore, the selection circuit 29
5 can be set to the L level.

Thus, by providing the circuit of FIG. 7,
The timing and the period when the carry signal CARRY is set to the H level are the same as the timing of the carry signal CARRY when the least significant bit of the initial value is 0B and the counting operation is performed at the rising edge of the first clock signal CLK. And H level during the period. FIG.
Since the operation of the circuit (1) is inhibited while maintaining the reset state except when the carry signal is at the H level, power consumption hardly increases. Therefore, the effect of the present invention is not impaired.

Here, returning to FIG. 6, the operation after time t6 will be described. Signal SECLK at time t6
Of each flip-flop 20 in response to the rising edge of
The output signals OUT1 to OUT4 1-1 to 201-4 become L level, respectively, and the count number returns to 0000B. Therefore, carry signal CARRY is also at L level.

Next, it is assumed that the initial value becomes 0000B at time t7. Therefore, the signals R1 to R4 are at the L level. Thereafter, before time t8, set signal SE
T is also set to H level.

In accordance with the rising edge of signal SECLK at time t8, flip-flops 201-1 to 201-2 are set.
01-4, an initial data control circuit 250 as new initial data for setting an initial value of the count.
Stores data corresponding to the output signal from. Register 1
Since the new initial value stored in 0 is 0000B,
Output signal O of flip-flops 201-1 to 201-3
The UT1 to OUT3 all go to L level, and the output signal OUT4 of the flip-flop 201-4 goes to H level. In other words, the initial value 1000B is stored in the counting unit 200 instead of the initial value 0000B.

The reason why 0000B is newly stored in the register 10 as an initial value is as follows. At time t8, unless a new initial value is stored in the register 10, the counting unit 200 changes from 0B to 1111.
B is counted up to the second clock signal CLK / 2.
Operates in response to the rising edge of. In this case, when the counting unit 200 operates the count process from 0B to 1111B in response to the rising edge of the first clock signal CLK, the carry signal CARR at the H level is used.
This is because the carry signal CARRY cannot be set to the H level at the same timing as the timing when Y is generated. Before time t8,
0001B is stored in the register 10 as an initial value and the first
In response to the rising edge of the clock signal CLK, the counting unit can be switched to perform the counting process, but as shown in FIG.
The value stored in 00 is more effective in reducing power consumption because the counting section 200 can be operated according to the rising edge of the second clock signal CLK / 2.

Thereafter, at time t10, time t12, and time t
14, the counts at time t16, time t18, and time t20 are 1001B, 1010B, and 101, respectively.
1B, 1100B, 1101B, and 1110B. At time t22, the count number becomes 1111B again, and carry signal CARRY attains H level. Carry signal CARRY maintains the H level until time t24 (not shown) (corresponding to the timing at which the rising edge of second clock signal CLK / 2 occurs after time t22).

Here, consider the case where 0000B, which is the initial value, is stored in the counting section 200 at time t8 as it is, and the count operation is performed with the first clock signal CLK. In this case, the count number becomes 1B at the time t9, and thereafter, the count number becomes 10B at the time t10 to the time t22.
1110B. Therefore, at time t23 (not shown in FIG. 6, but corresponding to between time 22 and time 24), the count number becomes 1111B and carry signal CARR.
Y becomes H level.

Therefore, as in the case of times t0 to t6,
Flip-flops 201-1 to 201-1 constituting counting section 200
Even if the number of operations of 201-4 is reduced, carry signal CARRY can be kept at the H level at a necessary timing (not shown in the above example, but at time t23).

As described above, when the least significant bit in the initial value is 0B, the initial data stored in each flip-flop is changed, and each flip-flop is changed to the second clock signal CLK obtained by dividing the first clock signal CLK. Clock signal CLK / 2
The counting operation is executed in accordance with. Even in this case, the carry signal CARRY is set to H at the same timing as when each flip-flop constituting the counting section 200 is operated according to the first clock signal CLK.
Level.

As described above, the count circuit 222 of the second embodiment realizes a reduction in power consumption without impairing the functionality as a counter.

In the second embodiment, a 4-bit counter has been described as an example. However, the present invention is not limited to this, and is an n-bit counter (where n is a positive integer of 2 or more). Is also good. In this case, the initial data of the m-th bit (m is a positive integer of n ≧ m) in the initial value of n bits,
That is, the initial data for the m-th flip-flop may be supplied as the initial data for the (m-1) -th flip-flop.

It is sufficient that the register 273 is not provided and a signal corresponding to 1B is supplied as data to the one-side input terminal of the selection circuit 254. Also, the selection circuit 2
When the first clock signal CLK is selected at 71, the operation of the circuit that generates the second clock signal CLK / 2 may be stopped according to the output signal of the detection circuit 230. In this case, further reduction in power consumption can be expected.

Note that the counter circuit of the present invention is not limited to the configuration shown in FIG. 1 or FIG. 4, but can be variously modified.

For example, a portion where 0B is input as data may be connected to a ground potential source, and a portion where 1B is input as data may be connected to a power supply potential source. Also, the flip-flop constituting the counting unit is JK
The present invention is not limited to the flip-flop, but may be a D flip-flop as long as it realizes a synchronous counting circuit.

The detection circuit 20, the clock supply control circuit 30, and the detection circuit 230 are not limited to the circuits shown in FIGS. 1 and 4, but may have other configurations. In particular, in FIG.
Each selection circuit 251 constituting the initial data control circuit 250
If the signal input to the 0-side input terminal of the selection circuit 271 and the signal input to the 1-side input terminal of the selection circuit 271 are reversed, the inverter 231 included in the detection circuit 230 can be omitted. In this case, the function of the detection circuit 230 is included in the initial data control circuit 250 and the selection circuit 271.

Further, in the above-described embodiment, the description has been given of a count circuit that performs a count-up operation. However, the present invention can be applied to a count circuit that performs a count-down operation.

[0146]

As described above, according to the present invention, it is possible to provide a count circuit capable of reducing power consumption without impairing its original function.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a count circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the count circuit according to the first embodiment of the present invention when the initial value is 0000B.

FIG. 3 is a timing chart for explaining the operation of the count circuit according to the first embodiment of the present invention when the initial value is 1100B.

FIG. 4 is a circuit diagram of a count circuit according to a second embodiment of the present invention.

FIG. 5 is a timing chart for explaining the operation of the count circuit according to the second embodiment of the present invention when the initial value is 0001B.

FIG. 6 is a timing chart for explaining the operation of the count circuit according to the second embodiment of the present invention when the initial value is 1010B.

FIG. 7 is a circuit diagram showing an improved part in an improved example of the count circuit according to the second embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 10 register 20 detection circuit 30 clock supply control circuit 100, 200 counting section 101-1 to 101-4, 201-1 to 201-4
Flip-flops 103-1 to 103-4, 104-1 to 104-4, 2
03-1 to 203-4, 204-1 to 204-4, 27
1 selection circuit 111, 222 count circuit 230 detection circuit 250 initial data control circuit

Claims (3)

[Claims] 1. An n-bit (where n is a positive integer of 2 or more) flip-flops each capable of storing initial data, and each flip-flop is an n-bit flip-flop that operates when a clock signal is supplied. In the counting circuit, of the initial data for each of the flip-flops of the counting circuit, a predetermined upper k bits (however,
k is a positive integer of n> k) and a detection circuit for detecting whether the initial data is 1 or not; and, in accordance with a detection result of the detection circuit, the detection circuit outputs the data to the flip-flop corresponding to the predetermined upper bit. A clock circuit, comprising: a clock supply control circuit that controls supply of a clock signal. 2. The count circuit according to a detection result of the detection circuit, outputs (nk) flip-flops other than the flip-flop corresponding to the predetermined upper k bits, or the count circuit. 2. The count circuit according to claim 1, wherein a carry signal is output based on any one of the outputs of the n flip-flops that constitute the count circuit. 3. An n-bit (where n is a positive integer of 2 or more) flip-flops each capable of storing initial data, and each flip-flop is an n-bit flip-flop that operates when a clock signal is supplied. In the count circuit, a detection circuit for detecting whether or not initial data for the least significant bit of the initial data for each of the flip-flops of the count circuit is 0, and each of the flip-flops according to a detection result of the detection circuit To the m-th (where m is a positive integer of n ≧ m) flip-flop supplied to the (m)
-1) an initial data control circuit for controlling whether or not to supply the data as initial data of a flop flop; and a first signal for generating a clock pulse at a first cycle in accordance with a detection result of the detection circuit. , 2 of the first cycle
A clock selection circuit that outputs one of a second signal that generates a clock pulse at a double cycle as the clock signal.