JP2000277752A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a TFT in which a sheet resistance can be reduced fully, without being constrained by base materials in a high temperature process by setting the highest process temperature to not higher than 750 deg.C, and a method for manufacturing this. SOLUTION: In this method for manufacturing a semiconductor device, a silicon semiconductor layer is formed on an insulating surface, and a gate insulating film is formed on the silicon semiconductor layer, and a gate electrode is formed on the gate insulating film, and one part of the gate insulating film is removed, the surface of the silicon semiconductor layer can be exposed, and impurity is injected into the silicon semiconductor layer by using the gate electrode as a mask and a source region and a drain region can be formed, and a metallic film is formed on the source region and the region, and the metallic film is irradiated with intense light, and the silicon on the source region and drain region surfaces and the metallic film are allowed to react to form a silicide layer, and metallic films which are not reacted is removed. A, YAG laser is used for the intense light.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulating substrate (referred to herein as an entire object having an insulating surface, and unless otherwise specified, not only insulating materials such as glass but also materials such as semiconductors and metals). Which also means that an insulating layer is formed on the surface)
The present invention relates to a method for forming an insulated gate semiconductor device and an integrated circuit having a large number of them formed thereon. The semiconductor device according to the present invention is used as a driving circuit for an active matrix such as a liquid crystal display, an image sensor, or the like, or as a thin film transistor in an SOI integrated circuit or a conventional semiconductor integrated circuit (a microprocessor, a microcontroller, a microcomputer, a semiconductor memory, or the like). Is what is done.

[0002]

2. Description of the Related Art In recent years, research on forming an insulated gate semiconductor device (MOSFET) on an insulating substrate has been actively conducted. Forming a semiconductor integrated circuit on an insulating substrate in this manner is advantageous in driving the circuit at high speed. Because
This is because the speed of the conventional semiconductor integrated circuit is mainly limited by the capacitance (stray capacitance) between the wiring and the substrate, but such a floating capacitance does not exist on the insulating substrate. A MOSFET formed on an insulating substrate and having a thin-film active layer is called a thin film transistor (TFT). In addition, in order to form an integrated circuit with multiple layers,
TFTs are essential. At present, in a semiconductor integrated circuit, for example, a TFT is used as a load transistor of an SRAM.

[0003] Recently, a product that requires a semiconductor integrated circuit to be formed on a transparent substrate has appeared. For example, a driving circuit for an optical device such as a liquid crystal display or an image sensor. Here also, a TFT is used. Since these circuits are required to be formed in a large area, a lower temperature of the TFT manufacturing process is required. Also, for example, in a device having a large number of terminals on an insulating substrate, even when the terminals need to be connected to the semiconductor integrated circuit, in order to reduce the packaging density, the first stage of the semiconductor integrated circuit, Alternatively, it has been considered to form the semiconductor integrated circuit itself monolithically on the same insulating substrate.

Conventionally, a TFT has been coated with an amorphous, semi-amorphous, or microcrystalline semiconductor film.
Annealing at a temperature of from 1 to 1200 ° C. has improved the crystallinity and improved the quality of the semiconductor film (that is, the mobility is sufficiently large). Amorphous TFT using amorphous material for semiconductor coating
Although mobility is less than 5 cm ² / Vs, usually 1 cm
² / Vs, which is small in terms of operating speed.
Since a channel type TFT cannot be obtained, its use is greatly restricted. TF with mobility of 5 cm ² / Vs or more
To obtain T, annealing at the above-described temperature was required. Further, a P-channel TFT (PTFT) could be formed by such annealing.

[0005]

However, in such a thermal process, the substrate material is significantly restricted. That is, in a so-called high-temperature process (a process in which the maximum process temperature is 900 to 1200 ° C.), a high-quality thermal oxide film can be used as a gate oxide film, but the substrate is expensive and has a large area such as quartz, sapphire, or spinel. Only materials that were difficult to convert could be used.

On the other hand, in a low-temperature process (a process in which the maximum process temperature is 450 to 750 ° C.), a wider range of substrate materials can be selected than in a high-temperature process, but a longer annealing time is required. Thus, there is a problem that the activation of impurities is not sufficient and the sheet resistance of the source / drain is large. Further, a method of crystallization of the active layer and activation of the source / drain by irradiation with a laser or the like (hereinafter, referred to as a laser process).
However, it has been difficult to reduce the sheet resistance. In particular, the electric field mobility is 150 cm ² / V
When a TFT that exceeds s is manufactured, 2
A sheet resistance of 00Ω / □ or less was required.

The present invention has been made in view of the above problems, and has a maximum process temperature of 750 ° C. or less,
Without being limited by the substrate material as in high temperature processes,
It is an object to provide a TFT with a sufficiently reduced sheet resistance and a method for manufacturing the TFT.

[0008]

In a conventional low-temperature process (maximum process temperature of 750 ° C. or less) or a laser process, the activation of the source / drain is particularly insufficient, and the sheet resistance is at least 100 to 1 kΩ / □. I could only get it. As a result, the characteristics (particularly, mobility) as a device cannot exhibit the original characteristics.

That is, there is a problem that the ON current and the operation speed of the TFT are reduced due to the large parasitic resistance of the source / drain between the source electrode (contact portion) and the drain electrode. However, on the other hand, it is difficult to approach the source electrode and the drain electrode unnecessarily because of the limit of pattern formation (minimum design rule) and the need to reduce the parasitic capacitance between the gate electrode and other wiring. Did not.

In the present invention, in this regard, by forming a layered silicide, which is an alloy of metal and silicon, in close contact with the source / drain and forming it in substantially the same shape as the source / drain, the source / drain is substantially formed. The characteristic is to reduce the sheet resistance to 100Ω / □ or less. Further, since silicide has a layered structure, the parasitic capacitance with the gate electrode is almost the same as that of the conventional source / drain. In particular, according to the present invention, the gate electrode is covered with the anodic oxide, the source / drain regions are formed in a self-aligned manner with respect to the gate electrode, and And a thin film silicide is formed.

In the present invention, it is desired that the metal material constituting the silicide is such that the silicide can form an ohmic or near ohmic low-resistance contact with the silicon semiconductor. In particular,
Molybdenum (Mo), tungsten (W), platinum (platinum, Pt), chromium (Cr), titanium (Ti), and cobalt (Co) are suitable. To implement the present invention,
At least one of these metals is reacted with silicon to form a silicide.

In particular, the role of the insulating anodic oxide is important in the present invention. The anodic oxide serves to prevent a short circuit between the silicide on the source / drain and the gate electrode. That is, silicide is
Since it is provided on substantially the entire surface on the drain, it comes close to the gate electrode as a result. The source / drain and the gate electrode are separated by the gate insulating film.
Silicide as in the present invention, once the process requirements,
Since it is formed after removing the gate insulating film on the source / drain, the possibility that the silicide contacts the gate electrode is extremely large. If the anodic oxide is present on at least the side surfaces of the gate electrode, it is possible to prevent the contact between the silicide and the gate electrode, and to obtain a very dense anodic oxide having good insulating properties. Therefore, the probability of a short circuit can be significantly reduced.

If the anodic oxide has an etching characteristic different from that of the gate electrode, the yield can be remarkably improved in the process. If there is no anodic oxide covering the gate electrode, after forming a silicide film and then removing the metal film that has not been silicided, if this metal film has an etching rate that is not much different from that of the gate electrode, In etching the metal film, part or all of the gate electrode is etched. Therefore, from the viewpoint of etching, it is preferable that anodic oxide is present on the upper surface of the gate electrode.

The method of manufacturing a TFT according to the present invention basically includes a step of anodizing a gate electrode and a step of forming a metal film for forming a silicide on an exposed element surface (including a silicon semiconductor region). The method includes four basic steps of reacting silicon and the metal film by irradiating strong light such as a laser to form silicide at the interface, and removing an unreacted metal film.

In the present invention, selecting the material of the gate electrode is important because it also determines the type of anodic oxide. In the present invention, the gate electrode may be a pure metal such as aluminum, titanium, tantalum, or silicon, or an alloy obtained by adding a small amount of an additive thereto (for example, an alloy obtained by adding 1 to 3% of silicon to aluminum, An alloy in which 1000 ppm to 5% of phosphorus is added to silicon), a conductive silicide such as tungsten silicide (WSi ₂ ) or molybdenum silicide (MoSi ₂ ), or a conductive nitride represented by titanium nitride can be used. . In this specification, unless otherwise specified, for example, aluminum means not only pure aluminum but also 10 aluminum.
% Or less containing additives. The same is true for silicon and other materials.

In the present invention, a gate electrode having a single layer structure using these materials alone may be used.
A gate electrode having a multilayer structure in which layers are stacked may be used. For example, a two-layer structure in which tungsten silicide is stacked on aluminum or a two-layer structure in which aluminum is stacked on titanium nitride. The thickness of each layer may be determined by a practitioner according to the required device characteristics.

In the present invention, the metal film is irradiated with strong light such as a laser to react with an underlying silicon semiconductor film to form silicide. If a laser is used, a pulsed laser is preferable. . With a continuous wave laser, the irradiation time is long, so that there is a danger that the object to be irradiated will be separated by expansion due to heat, and there is also thermal damage to the substrate.

As for the pulse laser, Nd: YAG
Infrared laser such as laser (preferably Q-switched pulse oscillation) and its visible light such as its second harmonic, Kr
Various ultraviolet lasers using excimers such as F, XeCl, and ArF can be used. However, when laser irradiation is performed from the upper surface of the metal film, it is necessary to select a laser having a wavelength that is not reflected by the metal film. However, there is almost no problem when the metal film is extremely thin. Further, the laser light may be applied from the substrate side. In this case, it is necessary to select a laser beam that passes through the underlying silicon semiconductor film.

The thickness of the silicide is selected depending on the sheet resistance required for the source / drain regions. If the sheet resistance does not reach 10 to 100 Ω / □, the specific resistance of the silicide is 0.1. Therefore, the thickness of the silicide is suitably from 10 nm to 1 μm.

[0020]

[Embodiment 1] FIG. 1 shows this embodiment. First, a substrate (Corning 7059, 300 mm × 400 m
A silicon oxide film having a thickness of 100 to 300 nm was formed as a base oxide film 101 on the substrate 100 (m or 100 mm × 100 mm). As a method for forming this oxide film, a sputtering method in an oxygen atmosphere was used. However, in order to further improve mass productivity, a film obtained by decomposing and depositing TEOS by a plasma CVD method may be annealed at 450 to 650 ° C.

Then, an amorphous silicon film is formed by plasma CVD or LPCVD for 30 to 500 nm.
m, preferably 100-300 nm,
It was left in a reducing atmosphere at 50 to 600 ° C. for 24 hours to be crystallized. This step may be performed by laser irradiation. Then, the silicon film crystallized in this manner was patterned to form the island regions 102.
Further, a thickness of 70 to 150 is further formed thereon by sputtering.
A silicon oxide film 103 having a thickness of nm was formed.

Thereafter, an aluminum (Al 99% / Si 1%) film having a thickness of 200 nm to 5 μm is formed by an electron beam evaporation method and is patterned to form a gate electrode 104, which is further passed through an electrolyte in an electrolytic solution to pass an anode. It was oxidized to form an anodic oxide 105 having a thickness of 50 to 250 nm. This situation is shown in FIG. Regarding the conditions of anodic oxidation, etc., refer to Japanese Patent Application No. 4-30220 (Jan.
(One-day application) was used.

Thereafter, the portion of the silicon oxide film 103 other than the portion under the gate electrode and the anodic oxide was removed to expose the surface of the silicon semiconductor 102. In order to remove the silicon oxide film 103, wet etching using an etching solution mainly containing hydrofluoric acid or dry etching can be used.

Thereafter, impurities are implanted into the island-like silicon film of each TFT in a self-aligned manner using the gate electrode portion (that is, the gate electrode and the anodic oxide film around the gate electrode) as a mask by ion doping. The impurity region 106 was formed as shown in FIG. Phosphine (PH ₃ ) may be used as a doping gas to form an NMOS TFT, and phosphorus may be implanted. To form a PMOS TFT, diborane (B ₂ H ₆ ) may be used as a doping gas and boron is injected. The acceleration energy was 10 to 60 keV.

Thereafter, as shown in FIG.
A tungsten film 107 of about 50 nm was formed by a sputtering method. Next, as shown in FIG. 1D, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 ns)
ec) was applied to react tungsten and silicon to form tungsten silicide regions 108 on the impurity regions (source / drain). The energy density of the laser is 200 to 400 mJ / cm ² , preferably 250 to 3
00 mJ / cm ² was appropriate. Since much of the laser light was absorbed by the tungsten film, it was rarely used to restore the crystallinity of the underlying silicon impurity region, which was significantly damaged by the previous ion doping. However, since tungsten silicide has a low resistivity of 30 to 100 μΩ · cm, the sheet resistance of the substantial source and drain regions (the region 108 and the impurity region thereunder) is, of course, 10 Ω / □ or less. Immediately after the impurity introduction step, the crystallinity deteriorated by the impurity introduction may be recovered by laser irradiation, thermal annealing, or the like.

Thereafter, as shown in FIG. 1E, the unreacted tungsten film was etched. For example, if reactive etching is performed in a fluorocarbon atmosphere, tungsten becomes tungsten hexafluoride, evaporates, and can be removed.

Finally, an interlayer insulator 109 is formed on the entire surface.
A silicon oxide film was formed to a thickness of 300 nm by a CVD method. Contact holes were formed in the source / drain of the TFT, and aluminum wiring / electrodes 110 and 111 were formed. Thus, the TFT was completed. In order to activate the impurity region, hydrogen annealing may be further performed at 200 to 400 ° C.

Embodiment 2 FIG. 2 shows this embodiment. First, a base oxide film 202, an island-shaped silicon semiconductor region, and a silicon oxide film 204 functioning as a gate oxide film are formed on a substrate (Corning 7059) 201 as in the first embodiment.
The gate electrode 205 was formed of an aluminum film (thickness: 200 nm to 5 μm). Then, as shown in FIG. 2A, impurity implantation was performed by ion doping using the gate electrode as a mask to form an impurity region 203.

Thereafter, the anodic oxide 20 is formed around the gate electrode (side surface and upper surface) by anodic oxidation as in the first embodiment.
6 was formed. In this case, compared to the case of the first embodiment,
It should be noted that the impurity regions penetrate into the anodic oxide. Thereafter, as shown in FIG. 2B, a region of the silicon oxide film 204 other than a portion existing under the gate electrode was removed to expose the surface of the impurity region.
Before the next step, laser irradiation or thermal annealing may be performed in order to improve the crystallinity of the impurity region whose crystallinity has been deteriorated by ion doping.

Then, as shown in FIG.
A molybdenum film 207 of about 50 nm was formed by a sputtering method. Next, as shown in FIG. 2D, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 ns)
Irradiation was carried out to cause molybdenum and silicon to react to form a molybdenum silicide region 208 on the impurity region (source / drain).

Thereafter, as shown in FIG. 2E, the unreacted molybdenum film is etched.
As shown in (F), an interlayer insulator 209 is formed on the entire surface.
Forming a silicon oxide film with a thickness of 300 nm by a CVD method,
Contact holes were formed in the source / drain of the TFT, and aluminum wiring / electrodes 210 and 211 were formed. Through the above steps, a TFT was completed.

Embodiment 3 FIG. 3 shows this embodiment. First, as shown in FIG.
9) A base oxide film 301, an island-shaped silicon semiconductor region 302, and a silicon oxide film 303 functioning as a gate oxide film are formed on 300 in the same manner as in the first embodiment, and a gate electrode 304 of an aluminum film (200 nm to 5 μm in thickness) is formed. Was formed. Then, anodic oxide 305 was formed around the gate electrode (side surface and upper surface) by anodic oxidation in the same manner as in Example 1.

Then, a region other than the portion under the gate electrode portion of the silicon oxide film 103 is removed, and as shown in FIG. 3B, a platinum (Pt) film 306 having a thickness of 5 to 50 nm is formed by sputtering. Formed. Further, impurities were introduced by ion doping through the molybdenum film, and an impurity region 307 was formed as shown in FIG. Next, as shown in FIG. 3D, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 ns)
Irradiation is carried out to react platinum and silicon, and to form silicide platinum region 308 as an impurity region (source / drain).
Formed on top.

Thereafter, as shown in FIG. 3E, the unreacted platinum film is etched.
As shown in (F), an interlayer insulator 309 is formed on the entire surface.
Forming a silicon oxide film with a thickness of 300 nm by a CVD method,
Contact holes were formed in the source / drain of the TFT, and aluminum wiring / electrodes 310 and 311 were formed. Through the above steps, a TFT was completed.

Embodiment 4 FIG. 4 shows this embodiment. First, as shown in FIG.
9) A base oxide film 401, an island-shaped silicon semiconductor region 402, and a silicon oxide film 403 functioning as a gate oxide film are formed on 400 in the same manner as in the first embodiment, and a gate electrode 404 of an aluminum film (200 nm to 5 μm in thickness) is formed. Was formed. Then, anodic oxide 405 was formed around the gate electrode (side surface and upper surface) by anodic oxidation in the same manner as in Example 1.

Then, a region other than the portion under the gate electrode portion of the silicon oxide film 403 was removed, and a titanium film 406 having a thickness of 5 to 50 nm was formed by a sputtering method as shown in FIG. Further, as shown in FIG.
rF excimer laser (wavelength 248 nm, pulse width 2
0 nsec) to react titanium and silicon to form a titanium silicide region 407.

Thereafter, as shown in FIG. 4D, the unreacted titanium film is etched, and impurities are introduced in a self-aligned manner by ion doping using the gate electrode as a mask to form a titanium silicide region 407. The impurity region 408 was formed below the substrate. Finally, as shown in FIG. 4E, a 300-nm-thick silicon oxide film is formed by CVD as an interlayer insulator 409, contact holes are formed in the source / drain of the TFT, and aluminum wiring and electrodes are formed. 410 and 411 were formed. Through the above steps, a TFT was completed.

[0038]

According to the present invention, the substantial resistance between the source and the drain can be significantly reduced. Conventionally, a method of performing thermal annealing for a long time has been used to reduce the resistance between the source and the drain. However, this method has a low throughput and the substrate temperature rises to 550 ° C. or higher, so that the substrate material is limited. On the other hand, although a method using laser irradiation has been attempted, it is necessary to optimize the energy density of the laser in order to lower the sheet resistance, and an appropriate sheet resistance can be obtained regardless of whether the energy density is low or high. Did not. Therefore, the variation in the characteristics of the obtained TFT is large,
Also, the resulting sheet resistance is at most several tens.
It was 0 Ω / □.

On the other hand, in the present invention, the sheet resistance is remarkably reduced by forming a very thin silicide film on the surface of the silicon semiconductor (source / drain), typically to 100Ω / □ or less. be able to. In the present invention, laser irradiation is required in order to obtain this silicide film, but the condition is remarkably mild as compared with the conventional condition for activating silicon, which contributes to a great improvement in yield.

In the present invention, with respect to the impurity region of the silicon semiconductor under the silicide layer, a step (activation step) for restoring crystallinity after ion implantation may or may not be provided. For example, when impurities are implanted by an ion doping method, 10 ¹⁵ cm
^When heavy doping of ⁻² or more is performed, a sheet resistance of about 10 kΩ / □ can be obtained without providing an activation step, and a low-resistance silicide layer is formed in close contact with the impurity region as in the present invention. If so, the effective source and drain sheet resistance is sufficiently low.

However, many defects exist in the silicon semiconductor which has not been subjected to the activation step, and depending on the purpose, it may not be preferable from the viewpoint of reliability. For such a purpose, activation of the impurity region should be performed. However, this increases the number of steps. However,
In the case where laser irradiation is used as the activation step in this case, since the purpose is not to optimize the sheet resistance of the impurity region, a milder condition than in the conventional case can be applied. As described above, the present invention is extremely useful for improving the characteristics of the TFT and improving the yield.

[Brief description of the drawings]

FIG. 1 shows a method for manufacturing a TFT according to the present invention.

FIG. 2 shows a method for manufacturing a TFT according to the present invention.

FIG. 3 shows a method for manufacturing a TFT according to the present invention.

FIG. 4 shows a method for manufacturing a TFT according to the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 insulating substrate 101 base oxide film (silicon oxide) 102 silicon semiconductor region 103 silicon oxide film (to be a gate oxide film) 104 gate electrode (aluminum) 105 anodic oxide 106 impurity region 107 metal film (tungsten) 108 silicide film (silicide) Tungsten) 109 Interlayer insulating film (silicon oxide) 110, 111 Metal wiring / electrode (aluminum)

Claims (6)

[Claims] 1. A silicon semiconductor layer is formed on an insulating surface, a gate insulating film is formed on the silicon semiconductor layer, a gate electrode is formed on the gate insulating film, and a part of the gate insulating film is removed. And exposing a surface of the silicon semiconductor layer, implanting impurities into the silicon semiconductor layer using the gate electrode as a mask, forming a source region and a drain region, and forming a metal film on the source region and the drain region. Forming a silicide layer by irradiating the metal film with a YAG laser to react the silicon on the surface of the source region and the drain region with the metal film, and removing an unreacted metal film from the metal film A method for manufacturing a semiconductor device. 2. A silicon semiconductor layer is formed on an insulating surface, a gate insulating film is formed on the silicon semiconductor layer, a gate electrode is formed on the gate insulating film, and the silicon semiconductor is formed using the gate electrode as a mask. Injecting impurities into a layer to form a source region and a drain region, removing a part of the gate insulating film to expose surfaces of the source region and the drain region, and on the source region and the drain region Forming a silicide layer by irradiating the metal film with a YAG laser to react the silicon on the surfaces of the source region and the drain region with the metal film; A method for manufacturing a semiconductor device, comprising: removing a substrate. 3. A silicon semiconductor layer is formed on an insulating surface, a gate insulating film is formed on the silicon semiconductor layer, a gate electrode is formed on the gate insulating film, and a part of the gate insulating film is removed. Exposing a part of the surface of the silicon semiconductor layer; forming a metal film on the exposed silicon semiconductor layer; implanting impurities into the silicon semiconductor layer using the gate electrode as a mask; Forming a region, irradiating the metal film with a YAG laser, and reacting the silicon on the surface of the source region and the drain region with the metal film to form a silicide layer; And a method for manufacturing a semiconductor device. 4. A silicon semiconductor layer is formed on an insulating surface, a gate insulating film is formed on the silicon semiconductor layer, a gate electrode is formed on the gate insulating film, and a part of the gate insulating film is removed. Exposing a part of the surface of the silicon semiconductor layer, forming a metal film on the exposed silicon semiconductor layer, irradiating the metal film with a YAG laser, Reacting silicon with the metal film to form a silicide layer, removing unreacted metal film, implanting impurities into the silicon semiconductor layer using the gate electrode as a mask, and forming a source region and a drain region Of manufacturing a semiconductor device for forming a semiconductor device. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the YAG laser uses a second harmonic. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the silicon semiconductor layer has a thickness of 30 to 500 nm.