JP2000269476A - Semiconductor crystal, manufacturing method thereof, and semiconductor device - Google Patents

Abstract

(57) [Summary] PROBLEM TO BE SOLVED: To provide a crystal structure accompanying a heat treatment in a SiGeC layer.
And a structure capable of suppressing the deterioration of the semiconductor device. SOLUTION: It is so thin that discrete quantization levels do not occur.
A few atomic layers of Si_1-x Ge_x Layer (0 <x <
1) and Si_1-y C_y Layers (0 <y <1) alternately
That can function as a single SiGeC layer
_1-x Ge_x / Si_{1- y} C_y Form a short-period superlattice.
This eliminates the Ge—C bond and provides good crystallinity.
And a thermally stable SiGeC ternary mixed crystal is obtained.
Si_1-x Ge _x / Si_1-y C_y How to form short-period superlattices
As a method, Si_1-x Ge_x Layer and Si _1-y C_y Interchange with layers
A method of epitaxial growth with each other and Si / Si_1-x
Ge_xAfter forming a short-period superlattice, C ion implantation is performed.
C atoms are transferred to the Si layer by heat treatment.
There is a way to make it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a group IV element mixed crystal semiconductor, a method of manufacturing the same, and a semiconductor device using the same.

[0002]

2. Description of the Related Art In recent years, attempts have been made to fabricate a device that operates at a higher speed than a conventional homojunction type Si device by forming a semiconductor device using a heterojunction on a Si substrate. As a material for forming a heterojunction, SiGe or SiGeC, which is a mixed crystal semiconductor using Ge and C, which are the same group IV elements as Si, is considered to be promising.

[0003] In particular, a SiGeC mixed crystal semiconductor composed of three types of elements can be obtained by changing the composition ratio of the three types of elements.
Since it is possible to control the band gap and the lattice constant independently of each other, attention has been paid to the reason that the degree of freedom in device design is high and lattice matching with Si is also possible. For example, Japanese Patent Application Laid-Open No. H10-116919
As disclosed in Japanese Patent Application Publication No. 2002-157, the two-dimensional electron gas formed at the interface is used as a carrier by utilizing the conduction band discontinuity generated at the hetero interface between the Si layer and the SiGeC layer. It is also said that a high-speed field-effect transistor is possible.

At present, a method of adding a C source gas during epitaxial growth of a SiGe layer or a method of adding C by performing ion implantation into the SiGe layer are used for producing a SiGeC mixed crystal. I have.

[0005]

However, for example,
As described in Applied Physics Letters, Vol. 65 (1994), p. 2559, the addition of C to the SiGe layer has a solid solution limit, and the crystallinity is increased by adding about 4% or more of C atoms. Is known to deteriorate significantly and become amorphous. Further, according to experiments performed by the present inventors, it has been found that heat treatment (annealing) of the SiGeC layer at various temperatures deteriorates crystallinity. In particular, there was a tendency that as the C concentration was increased, the deterioration of crystallinity became remarkable.

FIG. 8 is a diagram showing data obtained from experiments conducted by the present inventors, showing changes in the X-ray diffraction spectrum of a sample obtained by heat-treating (annealing) a SiGe _0.31 C _0.0012 crystal layer at various temperatures. As shown in the figure, the position of the diffraction peak of the sample heat-treated at a temperature of 800 ° C. or less is almost the same as the position of the diffraction peak of the as-grown sample. However, the position of the diffraction peak of the sample heat-treated at 900 ° C is
It starts to shift slightly from the position of the diffraction peak of the as-grown sample. Then, the position of the diffraction peak of the sample that has been heat-treated at a temperature of 950 ° C. or more starts to shift greatly from the position of the diffraction peak of the as-grown sample. In addition, the diffraction peak of the sample heat-treated at a temperature of 1000 ° C. or more has a large half-value width, and the fringe observed by as-grown has almost disappeared. According to the experimental data, when the heat treatment at a temperature of about 950 ° C. or more is performed, SiGe _0.31
It can be seen that the crystallinity of the C _0.0012 crystal layer has deteriorated.

Therefore, the present inventors have developed such a SiG.
An experiment was conducted to determine the cause of the crystallinity degradation of the eC crystal layer. The degradation of the SiGeC crystal layer due to the heat treatment was mainly due to the fact that the Ge—C bond was significantly unstable compared to the Si—C bond in the mixed crystal. I found that it was due to something.

FIGS. 7A and 7B show Ge on a Ge substrate.
_{When a 0.98} C _0.02 crystal layer is subjected to heat treatment to a sample obtained by growing a Si _0.98 C _0.02 crystal layer on a Si substrate,
It is a figure showing a change of a line diffraction spectrum. However, Ge
_{The 0.98} C _0.02 crystal layer is formed by ion implantation of C into the Ge substrate and heat treatment, and the Si _0.98 C _0.02 crystal layer is epitaxially grown on the Si substrate using a gas serving as a raw material of Si and C.

[0009] As shown in FIG.
e_0.98C_0.02In the case of a crystalline layer, at a temperature of 475-550 ° C
The diffraction peaks from the heat-treated sample are observed at almost the same position.
Measured at a temperature below 450 ° C.
No diffraction peak from the sample was observed. On the other hand, 6
Ge heat treated at a temperature of 00 ° C or higher_0.98C_0.02Crystal layer
The diffraction peak position shifts,
Ge heat treated _0.98C_0.02The peak from the crystal layer is
Has disappeared. This result was obtained by heat treatment at a temperature of 600 ° C or higher.
That the GeC crystal has undergone some change
In particular, it shows that the Ge—C bond is dissociated.
I have.

On the other hand, as shown in FIG. 7B, in the case of the Si _0.98 C _0.02 crystal layer on the Si substrate, the diffraction peak from the Si _0.98 C _0.02 crystal layer is clearly observed in the heat treatment up to 1000 ° C. I have.

When the above results are combined, instability of the Ge—C bond is one of the causes of crystal deterioration in the SiGeC crystal, and suppressing the formation of the Ge—C bond is the key to improving the crystallinity. It can be said that.

An object of the present invention is to focus on the cause of the instability of the SiGeC layer, and to form a short-period superlattice layer that can be regarded as a SiGeC crystal layer without including a Ge—C bond, thereby achieving good crystallinity. , And thermally stable SiGeC
It is an object of the present invention to provide a ternary mixed crystal, a manufacturing method thereof, and a semiconductor device using a SiGeC ternary mixed crystal.

[0013]

According to the present invention, there is provided a semiconductor crystal comprising:
Si _1-x Ge _x layer containing Si and Ge as main components (0 <x
<1) and, Si and Si _1-y as a main component and C C _y layer (0 <y <1) and was laminated alternately two periods or more Si _1-x
Having a Ge _x / Si _1-y C _y superlattice structure,
_{The 1-x} Ge _x / Si _1-y C _y superlattice is a single SiGe
It functions as a C layer.

Thus, the Si _1-x Ge _x / Si functioning as a SiGeC layer with almost no Ge—C bond
_{Since a 1-y} C _y superlattice structure is obtained, a semiconductor crystal having a function equivalent to that of a SiGeC layer that can stably maintain good crystallinity even when subjected to heat treatment is obtained.

The thickness of the Si _1-x Ge _x layer and the Si _1-y C _y layer in the Si _1-x Ge _x / Si _1-y C _y superlattice is smaller than the thickness at which discrete quantization levels are generated. Is thinner, so that Si _1-x Ge functioning as a single SiGeC layer
_x / Si _1-y C _{y A} short-period superlattice is obtained.

A semiconductor device according to the present invention includes a substrate, a first semiconductor layer provided on the substrate and containing at least Si.
A second semiconductor layer provided in contact with the semiconductor layer and functioning as a SiGeC layer, wherein the second semiconductor layer comprises:
Si _1-x Ge _x layer containing Si and Ge as main components (0 <x
It has a structure in which <1) and a Si _1-y C _y layer (0 <y <1) containing Si and C as main components are alternately stacked for at least two periods.

Thus, a heterojunction such as Si / SiGeC can be formed between the first semiconductor layer and the second semiconductor layer, and a high-performance semiconductor device utilizing the heterojunction can be formed. Thus, for example, a field effect transistor functioning as a HEMT can be obtained.

It is preferable that the Si _1-x Ge _x layer and the Si _1-y C _y layer are thinner than a thickness at which discrete quantization levels are generated.

The first method for producing a semiconductor crystal according to the present invention comprises:
Si _{1- x} Ge _x layer containing Si and Ge as main components (0 <x
The epitaxial growth of <1) and the epitaxial growth of a Si _1-y C _y layer (0 <y <1) containing Si and C as main components are alternately repeated twice or more, thereby forming a single SiGeC layer. Functional Si _1-x Ge _x / Si _{1- y}
This is a method for forming a _Cy short-period superlattice.

According to this method, the above-mentioned semiconductor crystal is easily formed.

According to a second method of manufacturing a semiconductor crystal of the present invention,
Si _{1- x} Ge _x layer containing Si and Ge as main components (0 <x
<1) Epitaxial growth and S containing Si as a main component
(a) forming an Si _1-x Ge _x / Si laminate by alternately repeating the epitaxial growth of the i-layer two times or more, and implanting C ions into the Si _1-x Ge _x / Si laminate. Performing step (b) and the above S in which C is introduced
subjecting the i _1-x Ge _x / Si laminate to a heat treatment (c), wherein the Si _1-x Ge _x / Si _{1-y Cy} laminate (0 <y
This is a method for forming <1).

According to this method, a gas for doping C is not required at the time of epitaxial growth by utilizing the phenomenon that C atoms move to the Si layer due to the destruction of the Ge—C bond due to the heat treatment, thereby eliminating the need for a gas for doping C. While maintaining
It is possible to obtain a Si _1-x Ge _x / Si _{1-y Cy} laminate that can be used in various applications.

In the step (a), the Si _1-x Ge _{x
/ Si 1-y C Si 1} -x Ge x layer of _y laminate in the Si _1-y
By the C _y layer to form a Si _1-x Ge _x layer and the Si layer so as to have a thickness of discrete quantization levels occurs, the multi-quantum barrier layer useful for forming the quantum device Thus, a Si _1-x Ge _x / Si _1-y C _y laminate functioning as such is obtained.

In the step (a), the Si _1-x Ge _{x
/ Si 1-y C Si 1} -x Ge x layer of _y laminate in the Si _1-y
By the C _y layer to form a Si _1-x Ge _x layer and the Si layer so as to have a thickness less than the thickness discrete quantized levels occurs, for configuring the heterojunction semiconductor device That can function as a single SiGeC layer useful for
An i _1-x Ge _x / Si _1-y C _y laminate is obtained.

In this case, the heat treatment temperature in the step (c) is preferably a temperature exceeding 700 ° C.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment relating to a semiconductor crystal and a method for manufacturing the same according to the present invention and an embodiment relating to an application to a semiconductor device will be described with reference to the drawings.

(First Embodiment) FIGS. 1A and 1B
Is a SiGeC mixed crystal (Si _1-x ) according to the first embodiment.
And _{Ge x / Si 1-y C} y macroscopic multilayer structure of the short-period superlattice), the short-period superlattice of microscopic multilayer structure and (atomic arrangement) is a diagram schematically showing.

As shown in FIG. 1A, the S of this embodiment
The iGeC mixed crystal has a Si _0.68 G
e The _0.32 layer 102 and the Si _0.96 C _0.04 layer 103
It is configured by being alternately stacked for the period. As shown in FIG. 1B, each of the layers 102 and 103 has three atomic layers.

The formation of the SiGeC mixed crystal is based on Si (00
1) An ultra-high vacuum chemical vapor deposition method (U
HV-CVD method) (Ultra High Vacuum Chemical Vapor)
Si _0.68 G consisting of three atomic layers by the Deposition method
e Si _0.96 C _0.04 layer 1 consisting of _0.32 layer 102 and 3 atomic layers
03 are alternately epitaxially grown, and this is
The cycle is repeated. The total thickness of the SiGeC mixed crystal is about 160 nm. The source gases of Si, Ge, and C include Si ₂ H ₆ , GeH ₄ , and SiH ₃ CH ₃ , respectively.
And the growth temperature is about 550 ° C.

The actual atomic arrangement in the formed short-period superlattice forms a diamond structure.
In (b), for easy understanding of the concept of the invention, a stack of atoms is shown using a tetragonal crystal. Thus, G
Since e atoms and C atoms are not present in a common layer, formation of a Ge—C bond hardly exists. Moreover, as described below, this short-period superlattice is
It functions as one SiGeC crystal.

FIG. 2 shows a reference (Semiconductor and Semime).
tals Vol.24 (ACADEMIC PRESS, INC.) p.29 Volume Editor
FIG. 19 is a diagram showing a change in an energy band structure when the thickness of a well layer and a barrier layer of a certain laminated body is changed, which is described in FIG. 18 of (RAYMOND DINGLE) (by C. Weisbuch). In the figure, the horizontal axis represents the thickness (nm) of the well layer and the barrier layer, and the vertical axis represents the potential energy (eV). As shown in the figure, in this laminate, a well layer,
When the thickness of the barrier layer is about 10 nm, discrete quantization levels are formed. On the other hand, when the thicknesses of the well layer and the barrier layer are about 1.5 nm or less, the discrete quantization levels are reduced. It changes to one bulk band. In other words, by eliminating the quantum effect, the carrier operates by recognizing the entire short-period superlattice layer as one layer. Similarly, in the short-period superlattice shown in FIGS. 1A and 1B, when the thickness of each layer becomes about 1 nm, there is no discrete quantization level, and it functions as a single SiGeC layer. Will do.

Therefore, the Si _1-x Ge _x / S of this embodiment
The i _1-y C _y short-period superlattice (0 <x, y <1) has an average thickness of about 0.8 nm for each layer, and therefore has little crystallinity due to almost no Ge—C bond. The function as a SiGeC layer can be exhibited while maintaining stability.

That is, the manufacturing method of the present embodiment focuses on the fact that the cause of the defect in the conventional SiGeC layer is the instability of the Ge—C bond, and does not include the Ge—C bond. _1-x Ge that can function as
_It can be said that this is a method of forming a _x / Si _1-y C _y short-period superlattice.

(Second Embodiment) In this embodiment, Si
/ Si _1-x Ge x multilayer film implanted C ions into (0 <x <1), by the heat _{treatment, Si 1-x Ge x /} Si 1-y C
_A method of manufacturing a Si _1-x Ge _x / Si _1-y C _y laminate that can be used for forming a _y short-period superlattice (0 <y <1) will be described. FIGS. 3A and 3B are cross-sectional views illustrating the steps of manufacturing the Si _1-x Ge _x / Si _{1-y Cy} laminate according to the present embodiment.

First, in the step shown in FIG.
01) A 10 nm thick Si layer 105 and a 10 nm thick Si layer 105 are formed on the substrate 101 by UHV-CVD.
_{The 0.8} Ge _0.2 layers 106 are alternately epitaxially grown to form a total of 10 periods of a Si / Si _0.8 Ge _0.2 superlattice.

Next, in the step shown in FIG. 3B, C ions are implanted into the superlattice body at an acceleration energy of about 45 ke.
V and the dose are about 1 × 10 ¹⁵ cm ⁻² . Thereafter, heat treatment is performed at 950 ° C. for 15 seconds.

FIGS. 4A, 4B, and 4C show, respectively, the concentration distribution of Ge atoms and C atoms before and after the heat treatment in the superlattice, and the distribution of C atoms in the superlattice immediately after C ion implantation. It is a figure which shows the distribution state and the distribution state of C atom in the superlattice body after heat processing.

In FIG. 4A, the horizontal axis represents the depth in the superlattice, and the vertical axis represents the concentration. Also, the curve Ger
Represents the Ge concentration, the curve Cimpl represents the C concentration immediately after the ion implantation and before the heat treatment, and the curve Canea represents the C concentration after the heat treatment. As shown by a curve Cimpl in the same figure, before the heat treatment, the Si layer 105 and the Si _0.8 Ge _0.2 layer 1
06, C is distributed almost uniformly at a concentration of about 1 × 10 ²⁰ cm ⁻³ . On the other hand, as shown by the curve Canea in FIG.
It can be seen that the concentration increases and the C concentration decreases in the Si _0.8 Ge _0.2 layer 106. This is shown in FIG.
As shown in (c), C atoms in the Si _0.8 Ge _0.2 layer moved to the adjacent Si layer during the heat treatment.

Therefore, by using C ion implantation and heat treatment into the Si / Si _0.8 Ge _0.2 superlattice, Si _1-y can be obtained without doping C during epitaxial growth.
It can be seen that a C _y / Si _0.8 Ge _0.2 superlattice can be formed.

FIG. 5 is a diagram showing the difference in the distribution of the C concentration when annealing is performed on the superlattice having undergone the steps shown in FIGS. 3A and 3B while changing the heat treatment temperature. In the figure, the curve Ger represents the Ge concentration in the superlattice and the curve Cas
im represents the C concentration in the superlattice immediately after the ion implantation and has not been subjected to the heat treatment, curve C700 represents the C concentration in the superlattice subjected to the heat treatment at 700 ° C., and curve C950 represents the C concentration in the superlattice subjected to the heat treatment at 950 ° C. The C concentration in the lattice is 1000 ° C.
Respectively show the C concentration in the superlattice body subjected to the heat treatment. The heat treatment time is 15 seconds in each case. As can be seen from the figure, C atoms did not move sufficiently by the heat treatment at 700 ° C.
The effect of transferring atoms is sufficiently obtained, and the distribution of the C concentration hardly changes between the two. Therefore, it is presumed that the structure of the SiC / SiGe interface formed by this method is stable.

According to the manufacturing method of this embodiment, Si _1-x
The following advantages are obtained as compared with a method of forming a Si _1-x Ge _x / Si _1-y C _y laminate by alternately epitaxially growing a Ge _x layer and a Si _1-y C _y layer.

Si_1-x Ge_x Layer and Si_1-y C_y Interchange with layers
When formed together, Si_1-y C _y After forming the layer
Clean substrate surface due to C material remaining in growth chamber
May not be obtained. On the other hand,
When C is added using on-injection, a laminate is formed
Selectively doping only one of the two layers with C
That was considered impossible. In contrast, this embodiment
Si_1-x Ge_x / Si_1-y C_y In the manufacturing method of the laminate
First, Si / Si_1-x Ge_x Forming a laminate
This Si / Si_1-x Ge_x C ions are implanted into the laminate
And then transfer of C atoms generated during heat treatment to the Si layer
By utilizing the phenomenon, Si_1-x Ge_x / Si
_1-y C_y A laminate can be formed.

That is, in the manufacturing method of this embodiment,
Is that the cause of the defect in the conventional SiGeC layer is Ge-
Focusing on the instability of the C bond, this Ge-C bond
Using the transfer of C atoms due to the instability of
, Si_1-x Ge_x / Si_1-y C _y Forming a laminate
Can be.

Then, the Si _1-x Ge _x / Si _1-y C
and _y Si _1-x Ge x layer of the laminate in the Si _1-y C _y layer is,
When the thickness is large enough to generate discrete quantization levels (such as in the present embodiment), the multiple quantization barrier layer (M
QB) etc. which can function as Si _1-x Ge _x / Si _1-y
A C _y superlattice can be obtained.

On the other hand, this Si_1-x Ge_x / Si_1-y C_y 
Si in the laminate_1-x Ge_x Layer and Si _1-y C_y Layers are separated
Has a thickness less than the thickness at which the scattered quantization levels occur
In this case, as in the first embodiment, a single SiG
Si that can function as an eC layer _1-x Ge_x / Si_1-y C_y 
A short-period superlattice (0 <x, y <1) can be obtained.
You. The reason will be described below.

The C atom migration phenomenon described in the present embodiment can be similarly generated even when a 1 nm-thick Si layer and a 1 nm-thick Si _0.8 Ge _0.2 layer are used.
Qualitatively confirmed. In addition, it has been confirmed that the C atoms can be moved by the heat treatment for any Ge content ratio and any C ion implantation conditions in the SiGe layer.

Therefore, by applying the method of this embodiment, the Si layer having a thickness of 1 nm level and the Si _1-x Ge _x
After the layer is formed, the ion implantation of C and the heat treatment are sequentially performed, and thus, as in the first embodiment,
Si _0.8 Ge _0.2 / functioning as one SiGeC layer
An SiC short-period superlattice can be formed.

When using the manufacturing method of the first embodiment,
The Si _1-x G _x layer and the Si _1-y C _y layer are alternately formed. However, as described above, the C raw material remains in the growth chamber after the formation of the Si _1-y C _y layer, resulting in the cleanliness. There is a problem that a proper substrate surface cannot be obtained. On the other hand, first, Si
/ Si _1-x Ge _x superlattice is formed, and this Si /
After C is ion-implanted into the Si _1-x Ge _x superlattice, the movement of C atoms to the Si layer during the heat treatment is utilized to make use of the Si _1-x Ge _x / Si _1-y C _y. By forming a short-period superlattice, Si that can function as a SiGeC layer
_{A 1-x} Ge _x / Si _1-y C _y short-period superlattice can be easily and rapidly manufactured.

Third Embodiment FIG. 6 is a sectional view showing the structure of a heterojunction field effect transistor (HMOSFET) which is a semiconductor device using a short-period superlattice according to a third embodiment. The short-period superlattice of the present embodiment is:
It is formed by any one of the first and second embodiments. In the present embodiment, an application to an n-channel HMOSFET will be described. However, it is needless to say that the invention can be applied to a p-channel HMOSFET.

As shown in FIG.
The FET comprises a Si substrate 111 and a p-type well 11 made of Si containing a high concentration of p-type impurities provided on the Si substrate.
2 and i-Si layer 11 formed on p-type well 112
3, a δ-doped layer 114 in which a region close to the surface in the i-Si layer 112 and a region spaced apart from the surface by a predetermined distance are doped with a high concentration n-type impurity (such as arsenic); Tier 1
14 formed on Si _0.68 Ge _0.32 / Si _0.96 C
_A SiGeC layer 116 composed of a _0.04 short-period superlattice;
Intrinsic Si formed on GeC layer 116
Cap layer 117 made of Si and the Si cap layer 11
7, a gate insulating film 118 made of a silicon oxide film and a gate electrode 119 made of polysilicon provided on the gate insulating film 118. In addition, a source formed by doping high-concentration n-type impurities (such as arsenic) into a region extending over the i-Si layer 114, the SiGeC layer 116, and the Si cap layer 117 by ion implantation using the gate electrode 119 as a mask. A region 120 and a drain region 121 are provided.

The energy level Ec at the conduction band edge of each layer 113, 114, 116, 117 below the gate electrode of this HMOSFET is shown on the left side of FIG. In other words, the SiGeC layer 116 made of the Si _0.68 Ge _0.32 / Si _0.96 C _0.04 short-period superlattice and the i-Si layer 113
A so-called hetero-barrier is formed due to the band discontinuity at the conduction band edge existing between the Si and SiGeC layers, and electrons are confined in a region of the SiGeC layer 116 that is in contact with the Si / SiGeC hetero-barrier. Then, an n-channel is formed in this region by the two-dimensional electron gas, and electrons can travel on this n-channel at a high speed.

That is, according to the HMOSFET of this embodiment, the n-channel 115 is formed along the Si / SiGeC hetero-barrier, and electrons can travel on the n-channel 115 at high speed. In this case, since the mobility of electrons is higher in the SiGeC layer than in the Si layer, and impurity doping is not required in the n-channel, scattering of ionized impurities is suppressed and high-speed operation is possible.

Next, the SiGeC layer 116 of the present embodiment
Are Si _{1-x as in the first} embodiment already described.
By alternately epitaxially growing a Ge _x layer and a Si _1-y C _y layer (0 <x, y <1), a Si _1-x Ge layer is formed.
_x / Si _1-y C _{y A} short-period superlattice may be formed, or as in the second embodiment, Si _1-x Ge _x
After a Si / Si _1-x Ge _x short-period superlattice is formed by alternately epitaxially growing layers (0 <x <1) and a Si layer, C ion implantation is performed, followed by heat treatment. , Si _1-x Ge _x / Si _1-y C _y
A method of forming a short-period superlattice (0 <y <1) may be used.

The semiconductor layer for forming a heterojunction with the SiGeC layer composed of the Si _1-x Ge _x / Si _1-y C _y short-period superlattice is not limited to the Si layer in the present embodiment. There are Si-containing layers such as a SiGe layer and a SiC layer, and any of them may be used.

[0055] _{Moreover, Si 1-x Ge x /} Si 1-y C y be n-type or p-type impurity in the short period superlattice body be _{doped, Si 1-x Ge x /} Si 1-y C y The function of the short-period superlattice as a single SiGeC layer is not impaired.

[0056] Incidentally, in the characteristic shown in FIG. 2, Si _1-x
Even _{if a} few discrete quantization levels are generated in the Ge _x / Si _1-y C _y short-period superlattice, SiGeC
What is necessary is that there is an energy range that can function as a layer.

[0057]

According to the present invention, a remarkable effect is obtained in that the crystallinity of the SiGeC-based semiconductor crystal can be improved and the high-speed performance of a device using the SiGeC-based semiconductor crystal can be improved.

[Brief description of the drawings]

FIGS. 1A and 1B show a Si according to a first embodiment; FIGS.
And _{1-x Ge x / Si 1} -y C y macroscopic multilayer structure of the short-period superlattice, and a microscopic multilayer structure of the short-period superlattice is a diagram schematically showing.

FIG. 2 is a diagram showing a change in an energy band structure when the thicknesses of a well layer and a barrier layer of a stacked body are changed.

FIGS. 3 (a) and 3 (b) show S in the second embodiment.
i is a cross-sectional view showing the manufacturing process of the _{1-x Ge x / Si 1} -y C y multilayer body.

4 (a), (b), and (c) respectively show the concentration distribution of Ge atoms and C atoms before and after heat treatment in the superlattice, and the distribution of C atoms in the superlattice immediately after C ion implantation. FIG. 4 is a diagram showing a state and a distribution state of C atoms in a superlattice body after heat treatment.

FIG. 5 is a graph showing C when annealing was performed on the superlattice body through the steps shown in FIGS. 3A and 3B while changing the heat treatment temperature.
It is a figure which shows the difference of density distribution.

FIG. 6 shows a heterojunction field effect transistor (H) which is a semiconductor device using the short-period superlattice according to the third embodiment.
FIG. 2 is a cross-sectional view illustrating a structure of a MOSFET.

FIGS. 7A and 7B show Ge on a Ge substrate; FIGS._0.98C
_0.02The crystal layer is formed on a Si substrate by Si _0.98C_0.02Remove the crystal layer
X-ray diffraction when heat-treated to each grown sample
It is a figure showing a change of a spectrum.

FIG. 8 is a diagram showing a change in an X-ray diffraction spectrum of a sample obtained by heat-treating (annealing) a SiGe _0.31 C _0.0012 crystal layer at various temperatures.

[Explanation of symbols]

101 Si substrate 102 Si _0.68 Ge _0.32 layer 103 Si _0.96 C _0.04 layer 105 Si layer 106 Si _0.8 Ge _0.2 layer 111 Si substrate 112 p-type well 113 i-Si layer 114 δ-doped layer 115 n-channel 116 SiGeC layer 117 Si cap layer 118 gate insulating film 119 gate electrode 120 source region 121 drain region

 ──────────────────────────────────────────────────の Continued on the front page (72) Koji Katayama, 1006 Kadoma, Kadoma, Osaka Prefecture, Matsushita Electric Industrial Co., Ltd. (72) Inventor Gaku Sugawara 1006 Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Minoru Kubo 1006 Odaka Kadoma, Kadoma City, Osaka Pref. DC02 EC07 EE04 EE06 5F045 AA07 AA15 AB01 AB02 AB06 AC01 AD09 AF03 BB12 BB16 CA07 DA54 HA15 HA16

Claims (9)

[Claims] _1. A Si _1-x G containing Si and Ge as main components.
S for e _x layer (0 <x <1), mainly Si and C
i _1-y C y layer (0 <y <1) and a having a _{Si 1-x Ge x / Si} 1-y C y superlattice structure formed by alternately laminating two cycles or more, the Si _1-x Ge A semiconductor crystal characterized in that the _x / Si _1-y C _y superlattice functions as a single SiGeC layer. 2. The semiconductor crystal according to claim 1, wherein Si in said Si _1-x Ge _x / Si _1-y C _y superlattice.
_1-x Ge The _x layer and the Si _1-y C _y layer, a semiconductor crystal according to claim thinner than the thickness of the discrete quantization levels occurs. 3. A semiconductor device comprising: a substrate; a first semiconductor layer provided on the substrate and containing at least Si; and a second semiconductor layer provided in contact with the semiconductor layer and functioning as a SiGeC layer. Is a Si _1-x Ge _x layer containing Si and Ge as main components (0 <x
(1) A semiconductor device having a structure in which a Si _1-y C _y layer (0 <y <1) containing Si and C as main components is alternately laminated at least for two or more periods. 4. The semiconductor device according to claim 3, wherein the Si _1-x Ge _x layer and the Si _{1-y Cy} layer are thinner than a thickness at which discrete quantization levels are generated. Semiconductor device. 5. A Si _1-x G containing Si and Ge as main components.
e _x layer and the epitaxial growth of (0 <x <1), by repeating Si and Si _1-y C _y layer mainly composed of a C (0 <y <1) epitaxial growth and alternately over twice the Si _1-x Ge _x / S functioning as a single SiGeC layer
A method for producing a semiconductor crystal, comprising forming an i _1-y C _y short-period superlattice. 6. A Si _1-x G containing Si and Ge as main components.
2 and the epitaxial growth of e _x layer (0 <x <1), the epitaxial growth of the Si layer containing Si as the main component alternately
A step (a) of forming a Si _1-x Ge _x / Si laminate by repeating at least twice, a step (b) of implanting C ions into the Si _1-x Ge _x / Si laminate, Heat treating the introduced Si _1-x Ge _x / Si laminate to form a Si _1-x Ge _x / Si _{1-y Cy} laminate (0 <y <1). A method of manufacturing a semiconductor crystal. 7. The method for manufacturing a semiconductor crystal according to claim 6, wherein in the step (a), the Si _1-x Ge _x / Si _1-y C
The Si _1-x Ge _x layer and the Si _1-y C _y layer in the _y- layered body have a thickness such that a discretized quantization level is generated.
The method of manufacturing a semiconductor crystal, which comprises forming a _1-x Ge _x layer and the Si layer. 8. The method for manufacturing a semiconductor crystal according to claim 6, wherein in the step (a), the Si _1-x Ge _x / Si _1-y C
Si _y-laminate in _1-x Ge _x layer and the Si _1-y C _y layer and is discretized Si _1-x As having a thickness less than the thickness of quantization levels occurs Ge _x layer and the Si A method for manufacturing a semiconductor crystal, comprising forming a layer. 9. The method of manufacturing a semiconductor crystal according to claim 6, wherein the heat treatment temperature in the step (c) is higher than 700 ° C.