JP2000267991A - Retry processing method in reading processing of bus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance use efficiency of a bus by improving a retry processing in a reading processing. SOLUTION: The reading processing is started by selecting a target on the bus by a master. (S50). When no reading processing can be accepted, a stop signal (STOP#) to notice completion of the processing is originated by the target (S52). In this case, an address/data signal (AD) including the number of clocks equivalent to time required until acceptance of the next processing is enabled is transmitted to the master (S56) without originating a target ready signal (TRDY#) to the master (S54) by the target. The reading processing is restarted after the time equivalent to the number of clocks elapses by the master.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing method when a retry occurs during bus processing, and more particularly to a processing method when a retry occurs during reading processing.

[0002]

BACKGROUND OF THE INVENTION Early personal computer systems (PC systems) use a single bus to transfer data between the different bus units of the system, typically a 16-bit ISA bus and 32-bit EIS
A bus. However, it is difficult to increase the data transfer speed on a single bus because of the limitations on bit transmission speed and width.

In addition, a PCI bus (Peripheral Compo
A bus called a Nent Interconnection Bus is applied to a computer system having a processor, the ISA bus or the EISA bus.
There is a feature that higher-speed data transfer can be performed.

Computers employing a PCI bus
The system includes a host-PCI bus bridge (hereinafter abbreviated as a host bus bridge) and a PCI-expansion bus bridge (hereinafter abbreviated as an expansion bus bridge). The host bus bridge manages data transfer between the PCI bus, processor, and main memory, and
The bus bridge manages data transfer between the PCI bus and the expansion bus. In this configuration, the host
Data is transferred between the main memory and the device connected to the PCI bus via the bus bridge. Similarly,
Data is transferred between the device connected to the expansion bus and the device connected to the PCI bus via the expansion bus bridge and the PCI bus, and the data is transferred between the host bus bridge, the expansion bus bridge, and the PCI bus. The data is transferred between the device connected to the expansion bus and the processor or the main memory.

As illustrated in FIG. 1, the PC system 10 includes a processor 12, a host bus 14, a host bus bridge 16, a PCI bus 18, an expansion bus bridge 20, and an expansion bus 22.
It is comprised including.

The processor 12 provides various processing signals to perform calculations, operation control, and normal operations. Further, the processor 12 is connected to the host bus 14 and the host bus bridge 16 is connected to the host bus 1.
4 and a PCI bus 18. Rev. 1995 PCI local bus standard
An expansion bus bridge 20 and a bus device 26 having an interface conforming to the PCI bus standard such as 2.1 are connected to the PCI bus 18. The high bandwidth bus device 26 is generally a graphics device 26.
a, a LAN device 26b, or an input / output device such as a SCSI device 26c. A typical low bandwidth bus device, such as basic I / O function device 28, is connected to expansion bus 22. Of these bus devices, those that actively access the memory can be PCI bus masters, and the other devices are PCI bus slaves.

[0007] The host bus bridge 16 is an arbitrator that arbitrates for access conflicts.
This arbitration device has a competing bus device which has a PC
It is determined whether to acquire the control right of the I bus 18. For example,
When different PCI bus devices attempt to access the memory, each sends a request signal to the arbitration device, which determines which ones are given control of the PCI bus 18 according to a predetermined arbitration protocol. After that, the bus device to which the control right is given becomes the master as the PC
Controls the I bus.

[0008] Taking the PCI bus master 27 connected to the PCI bus 18 as an example, it has a processor that operates the master by an internal clock signal, initializes the PCI bus, and controls its operation.

The functions executed by the host bus bridge 16 include not only realizing communication between the processor 12 and the PCI bus 18, arbitration of competition for controlling the PCI bus 18, but also memory 24. And communication between the processor 12 and the memory 24 and the PCI bus 18.

[0010] The expansion bus bridge 20
By being connected to the PCI bus 18 and the expansion bus 22, it manages data transfer, control signals, and address signals between the devices connected to the PCI bus 18 and the devices connected to the expansion bus 22. The expansion bus bridge 20 further includes an arbitration device for arbitrating a conflict between the bus devices 28 connected to the expansion bus 22. Each of the bus devices 28 and the expansion bus bridge 20 includes ISA, EI.
It is configured in conformity with the SA or MCA standard.

As shown in FIG. 2, for example, the host
Bus bridge 16 and expansion bus bridge 2
0, a multiplexed address / data signal (AD), a bus command / byte enable signal (CBE), and a cycle frame signal (F).
RAME #), initiator ready signal (IRDY)
#), A target ready signal (TRDY #), an interface control signal such as a device select signal (DEVSEL #), and a stop signal (STOP #), a PCI grant signal (PGNT #), and a PCI request signal (PREQ #). ) Is included.

In addition, as shown in Table 1, the PCI
The data transfer on the bus is the arbitration phase (arbitratio
n phases), an address phase, and a plurality of data phases.
In each phase, each signal has three logic levels: low (L), high (H), and floating (X). In addition, as shown in the timing diagram of FIG. 4, each signal is sampled on the rising edge of PCLK indicated by the vertical dotted line. The # mark added to the end of the signal name indicates that the signal is in the active state when the voltage is low.

[0013]

[Table 1]

When FRAME # is activated (low), an address phase of a read process or a write process is started. In the address phase, an address is output to AD and a bus command is output to CBE.

In addition, the fact that IRDY # is active (low) indicates that data exists in the AD in the writing process, and that the master is ready to receive the data in the reading process. . The fact that TRDY # is active (low) indicates that data exists in the AD in the read process and that the target is ready to receive the data in the write process. .

For example, in a read operation requested by the processor 12 and initiated by the host bus bridge 16, the master that gains control of the PCI bus 18 is the host bus bridge 16. The target, expansion bus bridge 20 in this example, transfers data to processor 12.

However, when the expansion bus bridge 20 is in a busy state and cannot receive the processing, a STOP is executed to interrupt the processing.
# Will be sent. As one of the interruption processes by the target in this case, there is "retry" in which the target requests interruption to the master without transferring any data.

FIG. 3 shows a signal state when the processing is terminated by retry. Each signal is sampled on the rising edge of PCLK indicated by the vertical dotted line. # Added to the end of the signal name
The mark indicates that the signal is active when the signal is at a low voltage. First, the master, that is, the host bus bridge 16 in this example, is
The read or write process is started by dropping E # to IRDY # low at PCLK3. The target signals its presence by dropping DEVSEL # low at PCLK4.

Next, the target, the expansion bus bridge 20 in this example, is
If the request cannot be accepted, TRDY
STOP # on PCLK4 without dropping # low
Drop low.

Since IRDY # and STOP # are low, the first data phase is completed at the timing of PCLK4. Since TRDY # is not low, no data is transferred in this data phase. PC
In LK4, since STOP # is low and TRDY # is high, the master recognizes that the target cannot transfer data corresponding to this processing.

The master, while IRDY # is low,
FRAME # needs to be pulled high. In this case, since IRDY # is low at PCLK5, FDY #
RAME # is pulled high on PCLK5. P
At CLK5, FRAME # is high and STO
The last data phase is completed because P # is low. The target terminates the series of processing, PCL
STOP # and DEVSEL # are pulled high at K6.

This processing includes two data phases of not performing data transfer and requesting the master to execute read processing again. Therefore, the master thereafter repeatedly executes the request for the reading process until the target can accept the process.

[0023]

However, since the master does not know when the target will be able to accept the request, it will repeat the request many times, which is time consuming. In addition, the efficiency of use of the bus is reduced.

Conventionally, in order to avoid such a situation, B
There has been proposed a method in which the master requests again after a predetermined time set in a timer programmed in the IOS has elapsed.

However, even this method cannot be said to be a sufficient solution because such a predetermined time cannot be accurately matched with the time until the target can receive the request. For example, if the predetermined time is set to 40 ns and the time until the target can receive the request is 41 ns, the master makes the request again after the lapse of 40 ns. At this point, the target is not yet ready to accept the request, so the master must make the request again after another 40 ns has elapsed, reducing efficiency.

The present invention has been made to solve the above problem, and has as its object to provide a retry processing method capable of improving the bus use efficiency.

[0027]

According to the present invention, there is provided a retry processing method in a bus read process according to the present invention, wherein a master selects a target on the bus and starts a read process, Transmitting a stop signal for notifying the master of the end of the processing without transmitting a target ready signal to the master when the target cannot receive the read processing; and transmitting the stop signal by the target. Requesting the master to restart the same read processing as the read processing after a time corresponding to the clock number elapses by transmitting an address / data signal having the number of clocks as the content. It is configured with.

In this method, it is preferable that the range of the number of clocks is set to a number equal to or less than the number of bits of the address / data signal (AD). For example, address /
Assuming that the data signal is 32 bits, the maximum value of the number of clocks is ²³² .

According to the method of the present invention, when the target cannot receive a processing request from the master, the number of clocks is sent to the master, and the master makes the processing request again after the number of clocks has elapsed. Therefore, the master repeats unnecessary requests many times by setting the number corresponding to the time required until the target can receive the processing request from the master as the clock number and sending it to the master. This eliminates the need and allows processing to be performed at optimal timing. Therefore, the bus can be opened for processing by another device, and the use efficiency of the bus can be improved.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. Note that the configuration of the computer system shown in FIG. 1 and the main configuration of the PCI interface shown in FIG. 2 are the same in this embodiment.
The description is omitted.

FIG. 5 is a flowchart showing a flow of a retry process in a read process (Read Cycle) of the PCI bus according to the embodiment of the present invention.

First, in step S50, the reading process is started when the master sends FRAME # and IRDY #.

In step S52, when the target cannot execute the requested read processing,
The target sends STOP #.

In step S54, the target is T
Do not send RDY #.

In step S56, the target is A
By driving D to transmit the number of clocks, the master is requested to restart the reading process after a lapse of time corresponding to the number of clocks.

FIG. 4 is a timing chart showing signal states in the retry processing according to the embodiment of the present invention. First, the master, that is, in this embodiment, the host bus bridge 16 transmits FRAME # by PCLK2 to PCL.
The reading process is started by dropping IRDY # to low at K3. The target asserts itself by dropping DEVSEL # low at PCLK4.

Next, if the target (the expansion bus bridge 20 in this embodiment) determines that it cannot accept the master's request,
STOP on PCLK4 without dropping Y # low
# Drop low.

At this time, the target sends the number of clocks not used in the conventional method to the master by driving the AD. This number of clocks is for requesting the master to start the same read processing after a time corresponding to the number of clocks has elapsed. Clock number is set within a range of 0-2 ^32, it is data corresponding to the time required until it becomes possible to perform a reading process that would target is then required. That is, in the range of 0 to 2 ^32, the number of clocks included in the AD, the target is determined according to the time required until it becomes possible to perform the next read operation.

Since IRDY # and STOP # are low, the first data phase is completed at the timing of PCLK4. Since TRDY # is not low, no data is transferred in this data phase. Although the AD was not used in the conventional processing method, in the present invention, the target drives the AD to send the number of clocks to the master as a waiting time until the master re-requests the same read processing. I have.

Also, since STOP # is low and TRDY # is not low in PCLK4, the master recognizes that the target does not transfer any data in response to this read operation.

The master, while IRDY # is low,
FRAME # needs to be pulled high. In this case, since IRDY # is low at PCLK5, FDY #
RAME # is pulled high on PCLK5. P
At CLK5, FRAME # is high and STO
The last data phase is completed because P # is low. The target terminates the series of processing, PCL
STOP # and DEVSEL # are pulled high at K6.

This processing includes two data phases of not performing data transfer and requesting the master to re-execute the read processing.

Therefore, the master waits for the elapse of time corresponding to the number of clocks sent from the target, and sends the request for the read processing to the target. At that time, the target can almost certainly receive the processing. It is in a state where it can be done.

As described above, according to the above method, when the target is in a busy state, the master executes the read processing only once after the elapse of the above-mentioned number of clocks. Can be completed.

The embodiments described above have been described in order to facilitate understanding of the present invention, but are not described to limit the present invention. Therefore, each element disclosed in the above embodiment is intended to include all design changes and equivalents belonging to the technical scope of the present invention.

[0046]

As described above, according to the method of the present invention,
Even if the target is busy when the master requests the read operation, the master only needs to re-execute the read operation once after the number of clocks described above, and the read operation is successfully completed. Can be completed. Therefore, the master is prevented from repeatedly performing the reading process many times, so that the bus use efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a computer system having a PCI bus and an expansion bus.

FIG. 2 is a diagram illustrating a main part of a PCI interface.

FIG. 3 is a timing chart showing signal states in a conventional retry process.

FIG. 4 is a timing chart showing a signal state in a retry process according to the present invention.

FIG. 5 is a flowchart showing a retry process according to the present invention.

[Explanation of symbols]

 12 Processor 14 Host Bus 16 Host Bus Bridge 18 PCI Bus 20 Expansion Bus Bridge 22 Expansion Bus 24 Memory 26a Graphics Device 26b LAN Device 26c SCSI Device 27 PCI Bus Master 28 Basic I / O Device

Claims (11)

[Claims] 1. A retry processing method in a bus read process, comprising: a step in which a master selects a target on a bus to start a read process; and when the target cannot receive the read process, Transmitting a stop signal for notifying the end of processing without transmitting a target ready signal to the master; and transmitting an address / data signal containing the number of clocks when the target transmits the stop signal. Requesting the master to restart the same read processing as the read processing after a time corresponding to the number of clocks has passed by transmitting the signal, and retrying in the bus read processing. Processing method. 2. The method according to claim 1, wherein the number of clocks is set to a number equal to or less than the number of bits of the address / data signal. 3. The method according to claim 2, wherein the number of bits of the address / data signal is 32. 4. The apparatus according to claim 1, wherein the number of clocks is set to be longer than a time required until the target can receive the read processing by the master again. Retry processing method in bus read processing. 5. The retry processing method according to claim 1, wherein the bus is a PCI bus. 6. The retry processing method according to claim 1, wherein the bus is an AGP bus. 7. A retry processing method in a bus read process, wherein a master selects a target on the bus in response to a request from a processor and starts a read process, and the target receives the read process. Transmitting a stop signal for notifying the end of processing without transmitting a target ready signal to the master when the target cannot transmit the stop signal. Requesting the master to restart the same read process as the read process after a time corresponding to the clock number elapses by transmitting the address / data signal to the master. Retry processing method in the read processing of the bus to be executed. 8. The method according to claim 7, wherein the master is a host bus bridge. 9. The method according to claim 7, wherein the target is an expansion bus bridge. 10. The retry processing method according to claim 7, wherein the stop signal by the target is at a low level when transmitted. 11. The method according to claim 10, wherein said target ready signal is at a high level when not transmitted.