JP2000260885A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) Abstract: Provided is a semiconductor integrated circuit device having an optimal layout configuration as a two-transistor, one-capacitor DRAM core while suppressing an increase in layout area. A memory cell array of a two-transistor, one-capacitor type DRAM is configured by an open bit line method. By arranging a plurality of sense amplifier unit cells having a total of three bit lines, one through bit line, a true bit line and a bar bit line connected to the sense amplifier, in a row, Sense amplifier row 3
a, and the sense amplifier unit cells are arranged by rotating them by 180 degrees to form the other sense amplifier row 3b. Further, a dummy memory cell array 2 is formed by connecting two adjacent bit lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and to a chip layout configuration.

[0002]

2. Description of the Related Art Conventionally, various DRAM chips composed of one-transistor one-capacitor type DRAM memory cells have been developed, and various measures have been taken to increase the capacity and speed.

FIG. 6 is a layout image diagram of a conventional 1-transistor 1-capacitor DRAM memory cell, a folded type bit line pair, and a DRAM core composed of a shared sense amplifier. In the figure, 1 is a sense amplifier unit cell, 2 is a sense amplifier circuit in the sense amplifier unit cell 1, 3L is a shared switch arranged at the left end in the sense amplifier unit cell 1, and 3R is a sense amplifier unit cell 1. Are a shared switch, 4 is a word line, 5 is a bit line pair, 6 is a memory cell transistor, and 7 is a memory cell capacitor. S1, S2, and S3 indicate that the sense amplifier unit cell has four bit lines (two bit line pairs).
M12 is a first memory cell array disposed between the sense amplifier rows S1 and S2, and M23 is a sense amplifier row arranged S2 and sense amplifier row S
3 is a second memory cell array arranged between the first and second memory cell arrays. One of two adjacent bit line pairs is connected to the sense amplifier unit on the right side of the memory cell array, and the other is
Connected to left sense amplifier unit.

Here, the operation of the one-transistor, one-capacitor DRAM core shown in FIG. 6 will be described.

When the word line 4 in the first memory cell array M12 is selected, the sense amplifier row S1 and the sense amplifier row S2 are activated, and the right-hand shared switch 3R in the sense amplifier row S1 is activated. The switch is turned on, and the left shared switch 3L is turned off. On the other hand,
Shared switch 3 on the right in sense amplifier row S2
R is OFF, left shared switch 3L
Becomes ON. That is, half of all the memory cells connected to the selected word line 4 are connected to the sense amplifier 2 of the sense amplifier row S2 on the right side of the first memory cell array M12, and the other half are connected to the left side sense amplifier. Connected to sense amplifier 2 in column S1. Similarly, when the word line 4 in the second memory cell array M23 is selected, the sense amplifier row S2 and the sense amplifier row S3 are activated, and the right-hand shared switch 3R in the sense amplifier row S2 becomes The switch is turned on, and the left shared switch 3L is turned off. On the other hand, the right shared switch 3R in the sense amplifier row S3 is turned off,
The left shared switch 3L is turned ON. That is, half of all the memory cells connected to the selected word line 4 are connected to the sense amplifier 2 of the sense amplifier array S3 on the right side of the second memory cell array M23, and the other half are connected to the sense amplifier on the left side. Sense amplifier 2 in column S2
Connected to.

With the above layout configuration and operation, the one-transistor one-capacitor type DRAM core has an optimal structure in consideration of the layout area and the operation performance.

[0007]

However, the conventional DRAM core is composed of a one-transistor, one-capacitor type DRAM memory cell having only one port, and the conventional DRAM core has a folded bit line pair. When the structure is applied to a two-transistor, one-capacitor DRAM core having two ports, there is a problem that the layout area is significantly increased.

The following is a description of an example of the problem.

FIG. 7 shows a two-transistor, one-capacitor type D
FIG. 3 is a circuit diagram of a RAM memory cell. It is composed of two transistors TRa and TRb and one capacitor Ccell. One terminal of the capacitor Ccell is connected to the cell plate potential Vcp, and the other terminal is connected to the word line W.
When La is selected, it is connected to bit line BLa via transistor TRa, and when word line WLb is selected, bit line BLb is connected via transistor TRb.
Is to be connected to. Hereinafter, the transistor T
A path connecting the bit line BLa and the capacitor Ccell via Ra is called port a, and a path connecting the bit line BLb and the capacitor Ccell via the transistor TRb is called port b. FIG. 8 is a layout diagram of a two-transistor, one-capacitor DRAM memory cell. In the figure, TRa and TRb are transistors, Ccel
l is a capacitor, WLa is a word line controlling the gate of the transistor TRa, WLb is a word line controlling the gate of the transistor TRb, BLa is a bit line connected to the capacitor Ccell when the word line WLa is selected, BLb Is a bit line connected to the capacitor Ccell when the word line WLb is selected. FIG. 9 is a layout image diagram of a DRAM core composed of the two-transistor, one-capacitor DRAM memory cell of FIG. 8, the conventional folded bit line pair, and the shared sense amplifier. In the figure, Sa0, Sa1, and Sb0 are sense amplifier unit cells. These sense amplifier unit cells have a sense amplifier circuit 2 at the center and a shared amplifier at the left end.
It has a switch 3L and a shared switch 3R at the right end. WLa0 and WLa1 are the word lines corresponding to the port a, WLb0 and WLb1 are the word lines corresponding to the port b, BLa0 and / BLa0 are the bit line pairs corresponding to the port a and connected to the sense amplifier unit cell Sa0, and BLb0. / BLb0 is a bit line pair connected to the sense amplifier unit cell Sb0 and corresponding to port b, BL
a1 and / BLa1 are bit line pairs connected to the sense amplifier unit cell Sa1 and corresponding to the port a. Also,
S1, S2, and S3 are sense amplifier columns each having a plurality of sense amplifier unit cells arranged in a row at a pitch of four bit lines (two bit line pairs), and M12.
Is a first memory cell array arranged between the sense amplifier rows S1 and S2, and M23 is a second memory cell array arranged between the sense amplifier rows S2 and S3. One of two adjacent bit line pairs is connected to the right sense amplifier unit of the memory cell array, and the other is connected to the left sense amplifier unit.

The operation of the two-transistor, one-capacitor DRAM core shown in FIG. 9 will now be described. When the word line WLa0 or WLa1 in the first memory cell array M12 is selected, the sense amplifier row S1
Only the shared switch 3R on the right in the sense amplifier array S1 is turned on, and the shared switch 3L on the left is turned off. That is, only half of all the memory cells connected to the selected word line WLa0 or WLa1 are in the first memory cell array M12.
Is connected to the sense amplifier 2 of the sense amplifier row S1 on the left. When the word line WLb0 or WLb1 in the first memory cell array M12 is selected,
Only the sense amplifier array S2 is activated, and the sense amplifier array S
2, the left shared switch 3L is turned on, and the right shared switch 3R is turned off. That is, only half of all the memory cells connected to the selected word line WLb0 or WLb1 are connected to the sense amplifier 2 of the sense amplifier row S2 on the right side of the first memory cell array M12.

The same operation is performed when a word line in the second memory cell array M23 is selected.

With the above-described layout configuration and operation, it is possible to realize a two-transistor, one-capacitor type DRAM core using the configuration of the above-mentioned conventional folded bit line pair and shared sense amplifier. However, in such a configuration, half of all the memory cells in the memory cell array are dummy cells used only as a reference at the time of a sensing operation, and if it is intended to realize the same data storage capacity as a conventional one-transistor one-capacitor DRAM. In addition, there is a problem that the layout area is quadrupled.

The present invention solves the above problems,
An object of the present invention is to provide a semiconductor integrated circuit device having an optimum layout configuration as a two-transistor, one-capacitor DRAM core while suppressing an increase in layout area.

[0014]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a plurality of memory cell arrays of a two-transistor, one-capacitor type DRAM forming two ports; and a sense amplifier disposed between these memory cell arrays. One of a pair of bit lines extending in the bit line direction with the sense amplifier row extending to one of the memory cell arrays and the other of the pair of bit lines extending to the other of the memory cell array. It is characterized by being connected by an open bit line method.

According to the semiconductor integrated circuit device of the first aspect, a dummy memory cell used only as a reference at the time of a sensing operation does not exist in a normal memory cell array, and a folded bit line system is used. The layout area can be reduced to a half of the case where it is adopted.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit device comprising a plurality of memory cell arrays and a sense amplifier array arranged between the plurality of memory cell arrays, wherein the sense amplifier array includes one through bit. A plurality of sense amplifier unit cells having a total of three bit lines, a true bit line and a bar bit line connected to the sense amplifier, are arranged in a row to form one sense amplifier row. Then, the sense amplifier unit cells are arranged by rotating by 180 degrees to form the other sense amplifier row, and the through bit lines of one sense amplifier row and the true bit lines of the other sense amplifier row are connected to each other. In this case, two sense amplifier rows are arranged.

According to the semiconductor integrated circuit device of the second aspect, the pitch size when a plurality of sense amplifier / unit cells are arranged in an array can be set to a length corresponding to four bit lines. . Since this is the same as the case where the conventional method is adopted, a layout without deteriorating the characteristics of the sense amplifier can be easily realized, and a special arrangement for connecting these between two sense amplifier rows is provided. There is no need for a wiring area or the like, and it is only necessary to arrange two sense amplifier rows composed of the same sense amplifier / unit cell by rotating each other by 180 degrees, so that an optimal layout with a small area can be realized.

According to a third aspect of the present invention, in the semiconductor integrated circuit device, the plurality of memory cell arrays include a dummy memory cell array in which half bit lines are invalid and only the remaining half bit lines are valid. The length in the direction is set to の of the area of the other memory cell array, and two bit lines adjacent to the dummy memory cell array are connected to form one bit line of the other memory cell array. It is characterized by doing.

According to the semiconductor integrated circuit device of the third aspect, the area of the dummy memory cell array region can be reduced to half of that of the normal memory cell array region, and the layout area can be reduced.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit device,
A plurality of memory cell arrays each including a memory cell having a port, a sense amplifier row group including two rows each arranged between the plurality of memory cell arrays, and each of the sense amplifier row groups having two ports. And a sense amplifier control circuit for simultaneously controlling two sense amplifier rows constituting the sense amplifier row without distinction.

According to the semiconductor integrated circuit device of the fourth aspect, it is only necessary to provide one sense amplifier control circuit for two sense amplifier rows, and a layout area for arranging the sense amplifier control circuits is provided. Can be reduced.

According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit device comprising:
A plurality of data line pairs for a first port and a plurality of data line pairs for a second port arranged on the memory cell array are adjacent to each other; Characterized in that a column selection line or various power supply lines are arranged between the data line pair for the first port and the data line pair for the second port so that there is no data line. It is.

According to the semiconductor integrated circuit device of the fifth aspect, the data line pairs of the port a and the port b are separated from each other, and the column selection line or the power supply line is arranged in the space therebetween, so that the port a and the port b are arranged. The data b does not interfere with each other, malfunctions due to interference noise can be prevented, and the entire arrangement space can be reduced by effectively utilizing the space of the column selection line and the power supply line and by using the electromagnetic shield.

According to a sixth aspect of the present invention, there is provided a semiconductor integrated circuit device having a structure in which a memory cell array, a sense amplifier array, and a dummy memory cell array are arranged adjacent to each other, and a row decoder block adjacent to the memory cell array and a sense amplifier array. An adjacent sense amplifier control circuit and a dummy row region adjacent to a dummy memory cell array are arranged adjacent to each other, and a row redundancy fuse circuit is arranged in a dummy row region at an end of a row decoder block. .

According to the semiconductor integrated circuit device of the sixth aspect, a dummy row region in which it is not necessary to arrange a row decoder can be effectively utilized, and the number of wirings in the row decoder region can be reduced, so that the layout area can be reduced. Can be achieved.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a diagram showing an outline of a layout configuration of an entire DRAM (referring to dynamic random access memory) core of a semiconductor integrated circuit device according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a normal memory cell array, and reference numeral 2 denotes a memory cell array arranged at a block end of a DRAM core. Half of the bit lines are invalid and only the remaining half of the bit lines are valid. Dummy memory cell arrays 3, 3 are two sense amplifier rows arranged between the normal memory cell array 1 and the dummy memory cell array 2, and between the normal memory cell array 1 and the normal memory cell array 1, 4 are normal memory cell arrays. A row decoder arranged in contact with 1;
Reference numeral 5 denotes a sense amplifier control circuit arranged in contact with the two sense amplifier rows 3, and reference numeral 6 denotes a dummy row area in contact with the dummy memory cell array 2.

FIG. 2 is a layout diagram of a sense amplifier unit cell of the semiconductor integrated circuit device according to one embodiment of the present invention. In the figure, tBL is a through bit line passing through the sense amplifier unit cell, SA is a sense amplifier circuit portion, BL is a true bit line connected to the sense amplifier circuit SA, and / BL is a sense amplifier circuit S
A bar bit line connected to A. Through bit line t
BL and the bar bit line / BL are in contact with the cell frame of the sense amplifier unit cell at both left and right ends of the wiring end,
One end of the true bit line BL is in contact with the cell frame of the sense amplifier unit cell, and the other end is closed in the sense amplifier unit cell.

As described above, the sense amplifier unit cell of the semiconductor integrated circuit device of the present invention has three bit lines.

FIG. 3 is a diagram showing a connection relationship between a memory cell and a sense amplifier in a semiconductor integrated circuit device according to an embodiment of the present invention, and a sense amplifier control method. In the figure, 1 is a normal memory cell array, 2 is a DRAM
Dummy memory cell arrays 3a arranged at the block ends of the core are two sense amplifier rows arranged between the normal memory cell array 1 and the dummy memory cell array 2, 3a
b is a normal memory cell array 1 and two sense amplifier rows arranged between the normal memory cell array 1. 2
Each of the sense amplifier rows has a configuration in which the same sense amplifier unit cells are arranged in a plurality in a row at a pitch of four bit lines, and the sense amplifier unit cells are rotated by 180 degrees with respect to each other. Has become. With this configuration,
The bit line pair connected to the sense amplifier is of an open bit line type extending in the left and right directions, that is, in the bit line direction with the sense amplifier interposed therebetween. Needless to say, the relationship between one true bit line and the other bar bit line in the bit line pair is reversed depending on the selected word line. 5a and 5b are two sense amplifier rows 3a,
A sense amplifier control circuit arranged in contact with 3b, 7 is a word line corresponding to port a, and 8 is a word line corresponding to port b. Note that “a” or “b” described at the end of a word line in a normal memory cell array means “port a” and “port b”, respectively, and each word line is connected to either a or b port. It indicates whether they correspond. Further, 9 is a memory cell capacitor, 10 is a memory cell transistor, and 11 is a folded bar bit line connecting two adjacent bit lines at the end of the dummy memory cell array 2. Ctrl_a is a port a activation signal, which is connected to a sense amplifier control circuit 5a for controlling two rows of sense amplifier rows 3a, and ctrl_b is a port b activation signal, for controlling two rows of sense amplifier rows 3b. Connected to amplifier control circuit 5b.

The operation of the semiconductor integrated circuit device configured as described above will be described below.

First, when the port a activation signal ctrl_a is generated, the sense amplifier control circuit 5a is activated, and the two sense amplifier rows 3a are controlled by the sense amplifier control circuit 5a. At the same time, the normal memory cell 1
One of the word lines a corresponding to the port a is selected from among the plurality of word lines in the memory cell, all the memory cell transistors 10 connected to the word line a are turned on, and the memory cell capacitor 9 and the bit line are connected. The data in the memory cell capacitor 9 is accessed through the two sense amplifier rows 3a. At this time, the folded bar bit line 11 in the dummy memory cell array 2 is used as a reference for the sensing operation. When the port b activation signal ctrl_b is generated, the sense amplifier control circuit 5b is activated, and the two sense amplifier rows 3b are controlled by the sense amplifier control circuit 5b. At the same time, one of the plurality of word lines in one of the normal memory cell arrays 1 arranged on the left and right of the two sense amplifier arrays 3b corresponds to the port b corresponding to the port b.
One word line b is selected, all the memory cell transistors 10 connected to the word line b are turned on, the memory cell capacitor 9 is connected to the bit line, and the memory cell capacitor 9 is connected through the two sense amplifier rows 3b. Is accessed. At this time, the bit line in the normal memory cell array 1 on the non-selected side is used as a reference for the sensing operation.

FIG. 4 is a diagram showing a layout configuration of data lines arranged on a memory cell array of the semiconductor integrated circuit device according to one embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a normal memory cell array, and reference numeral 3 denotes two sense amplifier rows arranged on both sides of the normal memory cell array 1. DLa is a data line pair for port a, DLb
Is a data line pair for port b, and Y is a column select line. (N-1), (n), and (n + 1) added to the suffix of each wiring name indicate the order of each wiring, and the data line pair for port a DLa and the data line pair for port b in the same order. DL
Column selection lines Y in the same order as these data line pairs are arranged between b. Further, a power supply wiring VDD or a ground wiring VSS is arranged between the data line pair DLa for port a and the data line pair DLb for port b, which differ in order by one. With such a layout configuration, the data for port a and the data for port b do not interfere with each other, and malfunction due to interference noise can be prevented.

FIG. 5A is a diagram showing a layout configuration of a row redundant fuse signal wiring of the semiconductor integrated circuit device according to one embodiment of the present invention. In the figure, 4 is a row decoder, 5 is a sense amplifier control circuit, and 6 is a dummy row area. Reference numeral 12 denotes a row redundant fuse circuit arranged in the dummy row region, and reference numeral 13 denotes a row redundant fuse signal line extending from the row redundant fuse circuit 12. The row redundancy fuse circuits 12 are arranged in the respective dummy row regions 6 at both ends of the row decoder block, and the row redundancy fuse signal lines 13 extend from the respective row redundancy fuse circuits 12 toward the center of the row decoder block. It is terminated when it reaches the sense amplifier control circuit 5.

On the other hand, FIG. 5B is a diagram showing a layout configuration of the row redundancy fuse signal wiring when the row redundancy fuse circuit 12 is arranged in the peripheral circuit region 14 in contact with the left end of the row decoder block. . In the figure, a row redundant fuse signal line 13 extending from a row redundant fuse circuit 12 is terminated when reaching a rightmost sense amplifier control circuit 5 arranged in a row decoder block.

As apparent from a comparison between the layout configurations shown in FIGS. 5A and 5B, as shown in FIG. 5A, the row redundancy fuses are provided in the respective dummy row regions at both ends of the row decoder block. By arranging the circuit,
The number of row redundant fuse signal lines running on the row decoder can be reduced by half, and the layout area of the row decoder block can be significantly reduced.

[0037]

According to the semiconductor integrated circuit device of the first aspect, a dummy memory cell used only as a reference at the time of a sensing operation does not exist in a normal memory cell array, and a folded bit line is not provided. The layout area can be reduced to half of the case where the method is adopted.

According to the semiconductor integrated circuit device of the second aspect, the pitch size when arranging a plurality of sense amplifier unit cells in one row can be set to the length of four bit lines. . Since this is the same as the case where the conventional method is adopted, a layout without deteriorating the characteristics of the sense amplifier can be easily realized, and a special arrangement for connecting these between two sense amplifier rows is provided. There is no need for a wiring area or the like, and it is only necessary to arrange two sense amplifier rows composed of the same sense amplifier / unit cell by rotating each other by 180 degrees, so that an optimal layout with a small area can be realized.

According to the semiconductor integrated circuit device of the third aspect, the area of the dummy memory cell array region can be reduced to half of that of the normal memory cell array region, and the layout area can be reduced.

According to the semiconductor integrated circuit device of the fourth aspect, it is only necessary to provide one sense amplifier control circuit for two sense amplifier rows, and a layout area for disposing the sense amplifier control circuits is provided. Can be reduced.

According to the semiconductor integrated circuit device of the fifth aspect, the data line pairs of the port a and the port b are separated from each other and the column selection line or the power supply line is arranged in the space therebetween, so that the port a and the port The data b does not interfere with each other, malfunctions due to interference noise can be prevented, and the entire arrangement space can be reduced by effectively utilizing the space of the column selection line and the power supply line and by using the electromagnetic shield.

According to the semiconductor integrated circuit device of the sixth aspect, a dummy row region which does not require a row decoder can be effectively utilized, and the number of wirings in the row decoder region can be reduced, so that the layout area can be reduced. Can be achieved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram schematically showing an overall layout configuration of a DRAM core of a semiconductor integrated circuit device according to an embodiment of the present invention;

FIG. 2 is an explanatory diagram schematically showing a layout configuration of a sense amplifier unit cell of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 3 is an explanatory diagram showing a connection relationship between a memory cell and a sense amplifier and a sense amplifier control method in the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 4 is an explanatory diagram schematically showing a layout configuration of data lines arranged on a memory cell array of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 5A is a diagram schematically showing a layout configuration of a row redundant fuse signal line of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 5B is a diagram showing a row redundant fuse circuit arranged in a peripheral circuit region; FIG. 10 is a diagram showing a layout configuration of a row redundant fuse signal wiring in the case where the above is done.

FIG. 6 shows a conventional one-transistor, one-capacitor DRAM.
FIG. 3 is a layout image diagram of a DRAM core including a memory cell, a folded bit line pair, and a shared sense amplifier.

FIG. 7 is a circuit diagram of a two-transistor, one-capacitor DRAM memory cell.

FIG. 8 is a schematic layout diagram of a two-transistor, one-capacitor DRAM memory cell.

FIG. 9 is a schematic layout diagram of a DRAM core composed of a two-transistor one-capacitor DRAM memory cell, a conventional folded bit line pair, and a shared sense amplifier.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Normal memory cell array 2 Dummy memory cell array 3, 3a, 3b 2 rows of sense amplifier rows 4 Row decoder 5, 5a, 5b Sense amplifier control circuit 6 Dummy row area 7 Word line corresponding to port a 8 Word corresponding to port b Line 10 Memory cell transistor 11 Folded bar bit line 12 Row redundant fuse circuit 13 Row redundant fuse signal line 14 Peripheral circuit area

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/10 471 G11C 11/34 362G F-term (Reference) 5B015 JJ14 JJ31 JJ36 KA13 KA38 NN01 PP02 PP07 QQ15 5B024 AA03 AA07 BA03 BA05 CA07 CA18 CA21 5F083 AD69 LA01 LA03 LA10 LA11 LA12 LA13 LA17 ZA10 ZA28

Claims (6)

[Claims] 1. A plurality of memory cell arrays of a two-transistor, one-capacitor type DRAM forming two ports, and one of a pair of bit lines arranged between these memory cell arrays and extending in a bit line direction with a sense amplifier interposed therebetween. A sense amplifier array extending to one of the memory cell arrays and the other of the bit line pairs extending to the other of the memory cell arrays, wherein the memory cell array and the sense amplifier arrays are connected by an open bit line method. Semiconductor integrated circuit device. 2. A semiconductor device comprising: a plurality of memory cell arrays; and a sense amplifier array disposed between the plurality of memory cell arrays, wherein the sense amplifier array is connected to one through bit line and a sense amplifier. By arranging a plurality of sense amplifier unit cells having a total of three bit lines of true bit lines and bar bit lines in a row, one sense amplifier column is formed, and the sense amplifier unit cell is formed. Are rotated 180 degrees to form the other sense amplifier row, and each of the two sense amplifier rows is connected so that the through bit line of the one sense amplifier row and the true bit line of the other sense amplifier row are connected to each other. A semiconductor integrated circuit device having a configuration in which a sense amplifier array is arranged. 3. A plurality of memory cell arrays, half of the bit lines comprise only the bit lines of the invalid and the remaining half is effective dummy memory cell array, a bit line direction of the length of the dummy memory cell array, the other A half of the area of the memory cell array is formed, and two bit lines adjacent to the dummy memory cell array are connected to form one bit line of the other memory cell array. Semiconductor integrated circuit device. 4. A memory cell array comprising memory cells having two ports, a sense amplifier row group consisting of two rows each arranged between the plurality of memory cell arrays, and a sense amplifier row group. A semiconductor integrated circuit device comprising: a sense amplifier control circuit for controlling each of the two sense amplifier rows constituting the sense amplifier row at the same time without distinguishing each of them, corresponding to one of the two ports. 5. A memory cell array comprising memory cells having two ports, a plurality of data line pairs for a first port arranged on the memory cell array, and a plurality of data lines for a second port. A column selection line or various power supply lines are arranged between the data line pair for the first port and the data line pair for the second port so that the line pairs are not adjacent to each other. A semiconductor integrated circuit device having a configuration. 6. A row decoder block adjacent to the memory cell array, having a configuration in which a memory cell array, a sense amplifier array, and a dummy memory cell array are arranged adjacent to each other, and a sense amplifier control circuit adjacent to the sense amplifier array. A semiconductor integrated circuit device having a configuration in which a dummy row region adjacent to the dummy memory cell array is arranged adjacently, and a row redundant fuse circuit is arranged in the dummy row region at an end of the row decoder block.