JP2000259492A - Data transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer system capable of reducing transfer time in data transfer between memories. SOLUTION: In this data transfer system, an address generation circuit 2 which generates a 1st address needed to access an external memory 9 and generates a 2nd address needed to access an internal memory 4 in the same bus cycle when a 1st access control signal is outputted is outputted from a CPU 1 and a control signal generation circuit 3 generates and supplies a 2nd access control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system with improved data transfer speed between memories.

[0002]

2. Description of the Related Art FIG. 6 shows a configuration of a conventional data transfer system for transferring data between memories. In FIG.
This data transfer system includes a CPU 101 (or DMA) included in the MCU 100 and serving as a control center of data transfer.
And the internal memory 102 of the MCU 100 and the MCU 10
0 is connected to the address bus 104 and the data bus 105 in parallel,
The read signal (R
D) and a write signal (WR) are provided to the internal memory 102 and the external memory 103.

In such a configuration, the internal memory 10
When performing data transfer between the external memory 103 and the external memory 103,
First, in the first bus cycle, the address bus 1
04 from the CPU 101 via the transfer source internal memory 10
2 or the external memory 103, and a read signal is provided from the CPU 101 to the transfer source memory, whereby data is read from the transfer source memory to the data bus 105. Next, in the second bus cycle, the CPU
101 to the external memory 103 or the internal memory 1 of the transfer destination
02 is given a write address and the CPU 101
Supplies a write signal to the transfer destination memory, whereby the read data is written to the data bus 105 in the transfer destination memory, and the internal memory 102 and the external memory 1
Data transfer was performed between 03.

As described above, in the conventional data transfer between memories, one data transfer requires two bus cycles. Therefore, when transferring a large amount of data, an extremely long transfer time is required.

[0005]

As described above,
In a conventional data transfer system between memories, when transferring one data, two bus cycles, a bus cycle for reading data and a bus cycle for writing data, are required. Therefore, in spite of simple data transfer between memories, data transfer takes a long time, and when transferring a huge amount of data, a large transfer time is required. Processing took time. This has led to a problem that the performance of the entire system is reduced.

Accordingly, the present invention has been made in view of the above, and it is an object of the present invention to provide a data transfer system capable of achieving a reduction in transfer time in data transfer between memories. is there.

[0007]

In order to achieve the above-mentioned object, a first means for solving the problem is a control unit having a function of controlling data transfer, and a first memory and a second memory having a function of controlling data transfer. A data transfer system connected in parallel to a bus and a first address bus, wherein data is transferred between the first memory and the second memory via the data bus under the control of the control unit Wherein the control unit accesses the first memory within the same access cycle during data transfer.
And a second address for accessing the second memory, supplying the first address to the first memory via the first address bus, and generating the second address by the control unit. A second address bus to which the second address is exclusively transferred, and a read or write signal of a first access control signal supplied from the control unit to the first memory; A control signal generation circuit for generating a write signal or a read signal of a second access control signal within the same access cycle when the first memory is accessed and supplying the write signal or the read signal to the second memory; A first address provided from the control unit via a bus, and a first address provided from the address generation circuit via the second address bus. And an address input circuit for selecting the first address or the second address and inputting the selected address to the second memory, and receiving a first access control signal provided from the control unit. During data transfer, the second access control signal
And a control signal input circuit for prohibiting input to the memory of the second memory. In the data transfer, the second memory receives a second address supplied through the second address bus and a second signal supplied from the control signal generation circuit. 2 is accessed in accordance with the second access control signal.

The second means includes a control unit having a function of controlling data transfer, a first memory and a second memory connected in parallel to a data bus and a first address bus, and controlling the control unit. In a data transfer system in which data is transferred between the first memory and the second memory via the data bus under the same condition, the first memory is accessed within the same access cycle. An address generation circuit for generating a second address for accessing the second memory; a second address bus to which the second address generated by the address generation circuit is exclusively transferred; Upon receiving a read signal or a write signal of a first access control signal supplied to the first memory, the first memory is activated during data transfer. And a control signal generating circuit that generates a write signal or a read signal of a second access control signal and supplies the write signal or the read signal to the second memory in the same access cycle when the memory is accessed. Receiving a first address provided from a control unit and a second address provided from the address generation circuit via the second address bus, selecting the first address or the second address, In response to an address input circuit input to the second memory and a first access control signal provided from the control unit, input of the first access control signal to the second memory is inhibited during data transfer. And a control signal input circuit, wherein at the time of data transfer, the second memory is a second address provided through the second address bus. Characterized by comprising been accessed according to a second access control signal supplied from said control signal generating circuit.

The third means is the second means,
The address generating circuit includes: a register for holding an offset value given from the control unit via the data bus before data transfer; an offset value held in the register; and a first address bus from the control unit. And an adder for adding the first address given to the first memory via the first memory to generate the second address.

[0010] A fourth means is the first, second or third means, wherein the second memory comprises the control unit, the second address bus, the control signal generation circuit, the address input circuit, and the second memory. A unit having a control signal input circuit, or an internal memory included in a unit having the address generation circuit in the unit;
Is characterized by comprising an external memory provided outside the unit.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a data transfer system according to an embodiment of the present invention.

In FIG. 1, a data transfer system according to this embodiment includes a CPU 1, an address generation circuit 2, a control signal generation circuit 3, an internal memory 4, an address input circuit 5, a control signal input circuit 6, and a second address bus 7. MCU with
An external memory 9 provided outside the MCU 8 is connected to the data bus 10 and the first address bus 11 in parallel.

The CPU 1 individually accesses the internal memory 4 or the external memory 9 and functions as a control unit serving as a control center for controlling data transfer between the two memories.
That is, the CPU 1 supplies all or a part of a read signal or a write signal serving as an address, data, and an access control signal, which are necessary when each memory is accessed. Further, the CPU 1 supplies a data transfer valid signal to the control signal generation circuit 3, the address input circuit 5, and the control signal input circuit 6 when data is transferred between the internal memory 3 and the external memory 9.

The address generation circuit 2 receives a first address given from the CPU 1 to the external memory 9 via the first address bus 11, and when the external memory 9 is accessed by the first address, the same address is generated. A second address for accessing the internal memory 4 is generated within a bus cycle. The generated second address is applied to the address input circuit 5 via the second address bus 7 which exclusively transfers the second address. The address generation circuit 2 is, for example, as shown in FIG.
As shown in FIG. 3, a register 21 receives and holds an offset value given from the CPU 1 through the data bus 10.
And an ADDER (adder) 22 for adding a first address given from the CPU 1 via the address bus 11 and an offset value held in the register 21 to generate a second address for accessing the internal memory 4. It is composed. Note that the offset value given from the CPU 1 is
In a series of data transfer processing, it may be fixed or may be changed for each address generation.

The control signal generating circuit 3 receives a read signal (RD1) or a write signal (WR1) of the first access control signal given from the CPU 1 to the external memory 9, and transfers data from the CPU 1 during data transfer between the memories. When a valid signal is given (when valid), when the external memory 9 is accessed, a write signal (WR2) or a read signal (RD2) of the second access control signal is generated within the same bus cycle to generate the internal memory 4 Give to. That is, when transferring data from the external memory 9 to the internal memory 4, the control signal generation circuit 3 receives a read signal of the first access control signal for reading data from the external memory 9 and receives the read signal of the second access control signal. When a write signal is generated and data is transferred from the internal memory 4 to the external memory 9, a write signal of a first access control signal for writing data to the external memory 9 is received and a read signal of a second access control signal is received. Generate The control signal generation circuit 3 is configured by using AND gates 31 and 32 that are gated by a data transfer valid signal, for example, as shown in FIG.

The internal memory 4 is accessed based on an address supplied from an address input circuit 5, data input / output via a data bus 10, and an access control signal supplied from a control signal generation circuit 3 or a control signal input circuit 6. Is done.

The address input circuit 5 receives a first address given from the CPU 1 via the first address bus 11 and a second address given from the address generating circuit 2 via the second address bus 7. When the data transfer valid signal is valid, the second address is selected, and when the data transfer signal is invalid, the first address is selected. The selected first or second address is provided to the internal memory 4. The address input circuit 5, for example, as shown in FIG.
A buffer gate 41 for controlling buffer selection of a first address and a second address based on a data transfer valid signal;
42.

The control signal input circuit 6 receives the first access control signal from the CPU 1 and prohibits the input of the first access control signal to the internal memory 4 when the data transfer valid signal is valid. The control signal input circuit 6 is configured by using AND gates 51 and 52 which are gated by a signal obtained by inverting a data transfer valid signal, for example, as shown in FIG.

In such a configuration, the internal memory 4 or the external memory 9 is individually accessed by the first address given from the CPU 1 to the first address bus 11 and the first control signal.

Next, when data is transferred between the internal memory 4 and the external memory 9, for example, when data is transferred from the address 1000 of the external memory 9 to the address 100 of the internal memory 4, the transfer is first started. Before the initialization, the CPU 1 writes the offset value “F100” into the register 21 of the address generation circuit 2. Thereafter, when the data transfer valid signal is output from the CPU 1 and the bus cycle of the data transfer is started, the first address (address 1000) becomes C
PU1 is applied to first address bus 11, and a read signal (RD1) of a first access control signal is output. In this bus cycle, the first address given to the first address bus 11 is added to the offset value of the address generation circuit 2 and the second address (100
Address) is generated, and the generated second address is selected by the address input circuit 5 and supplied to the internal memory 4.
In this bus cycle, a write signal of the second access control signal is generated by the control signal generation circuit 3 and supplied to the internal memory 4. At this time, the input of the read signal of the first access control signal to the internal memory 4 is prohibited by the control signal input circuit 6.

Thus, in this bus cycle,
A first address output to the first address bus 11,
Data is read from address 1000 of the external memory 9 to the data bus 10 based on the read signal of the first access control signal given from the CPU 1, and the data read to the data bus 10 is stored in the address input circuit 5. Is written to the address 100 of the internal memory 4 based on the second address selected in the step (c) and the write signal of the second access control signal given from the control signal generation circuit 3;
The data transfer of one data from the external memory 9 to the internal memory 4 ends. On the other hand, when performing data transfer in which data is read from the internal memory 4 and written to the external memory 9, the first access control signal is used as a write signal, and the second access control signal is used as a read signal. Similarly, data transfer can be performed in one bus cycle.

Thus, in the same bus cycle as when the first address and the first access control signal required to access one memory are output from CPU 1, it is necessary to access the other memory. Since the second address and the second access control signal are generated and supplied, one data can be transferred between the internal memory and the external memory in the same bus cycle. As a result, the data transfer time can be reduced by half as compared with the related art that requires two bus cycles to transfer one data. Further, since the data transfer time is greatly reduced, the processing time of the processing involving data transfer is also reduced, and the processing capacity of the system can be improved.

As another embodiment of the above-described embodiment, for example, the function of the address generation circuit 2 may be included in the CPU 1, and when the MCU 8 includes a plurality of internal memories, the data transfer is performed between the internal memories. The data transfer system is not limited to a system including an MCU, but may be any system provided with a data transfer function between memories.

[0025]

As described above, according to the present invention, in the same bus cycle as when the first address and the first access control signal required to access one memory are output, the other is used. The second address and the second access control signal required to access the memory are generated and supplied, so that one data can be transferred between the memories in one bus cycle. Become. As a result, the data transfer time can be reduced as compared with the related art. Further, since the data transfer time is greatly reduced, the processing time of the processing involving data transfer is also reduced, and the processing capacity of the system can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a data transfer system according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of an address generation circuit illustrated in FIG. 1;

FIG. 3 is a diagram illustrating a configuration of a control signal generation circuit illustrated in FIG. 1;

FIG. 4 is a diagram showing a configuration of an address input circuit shown in FIG. 1;

FIG. 5 is a diagram showing a configuration of a control signal input circuit shown in FIG.

FIG. 6 is a diagram showing a configuration of a conventional data transfer system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Address generation circuit 3 Control signal generation circuit 4 Internal memory 5 Address input circuit 6 Control signal input circuit 7 Second address bus 8 MCU 9 External memory 10 Data bus 11 First address bus 21 Register 22 Adder 31, 32, 51, 52 AND gate 41, 42 Buffer gate

Claims (5)

[Claims] 1. A control unit having a function of controlling data transfer, and a first memory and a second memory are connected in parallel to a data bus and a first address bus, and under control of the control unit, In a data transfer system in which data is transferred between the first memory and the second memory via a data bus, the control unit stores the first memory in the same access cycle during data transfer. Generating a first address to access and a second address to access the second memory, supplying the first address to the first memory via the first address bus, the control unit A second address bus to which the second address generated in step (1) is exclusively transferred, and a first address bus supplied from the control unit to the first memory. Upon receiving a read signal or a write signal of an access control signal, when data transfer is performed, a write signal or a read signal of a second access control signal is generated within the same access cycle when the first memory is accessed. A control signal generation circuit that supplies the first memory with a first address provided from the control unit via the first address bus and a second control signal generated from the address generation circuit via the second address bus. An address input circuit that selects the first address or the second address and inputs the selected address to the second memory; and a first access control signal provided from the control unit. A control signal input circuit for inhibiting input of the first access control signal to the second memory during data transfer. At the time of data transfer, the second memory is accessed according to a second address provided via the second address bus and a second access control signal provided from the control signal generation circuit. Data transfer system. 2. A control unit having a function of controlling data transfer, and a first memory and a second memory are connected in parallel to a data bus and a first address bus, and under control of the control unit, In a data transfer system in which data transfer is performed between the first memory and the second memory via a data bus, the second memory may be accessed within the same access cycle when the first memory is accessed. An address generation circuit for generating a second address for accessing the memory of the first embodiment, a second address bus to which the second address generated by the address generation circuit is exclusively transferred, and a first address bus from the control unit. Upon receiving a read signal or a write signal of a first access control signal supplied to the memory, the first memory is accessed during data transfer. A control signal generation circuit that generates a write signal or a read signal of a second access control signal in the same access cycle as described above and supplies the write signal or the read signal to the second memory; In response to a given first address and a second address provided from the address generation circuit via the second address bus, the first address or the second address is selected and the second address is selected. An address input circuit for inputting to the memory; a control signal input for receiving a first access control signal provided from the control unit and for inhibiting input of the first access control signal to the second memory during data transfer A second address during data transfer, a second address provided through the second address bus, and a control circuit. Data transfer system characterized by comprising been accessed according to a second access control signal supplied from the signal generating circuit. 3. An address generating circuit comprising: a register for holding an offset value given from the control unit via the data bus before data transfer; an offset value held in the register; Adding a first address provided to the first memory via a first address bus to add the second address to the second memory;
3. The data transfer system according to claim 2, further comprising: 4. The second memory includes: the control unit, the second address bus, the control signal generation circuit,
A unit having the address input circuit and the control signal input circuit, or an internal memory included in a unit including the address generation circuit in the unit, wherein the first memory is an external memory provided outside the unit. 4. The data transfer system according to claim 1, comprising a memory. 5. A data transfer valid signal provided from the control unit selects a second address when valid.
3. The data transfer system according to claim 1, wherein the first address is selected when the data is invalid.