JP2000243893A - Integrated circuit device and module mounting the same - Google Patents

Abstract

(57) [Summary] (with correction) [PROBLEMS] To make connections between terminals, leads, and external terminals of a module for data input / output signals requiring high-speed operation all the same length and the shortest length. According to the present invention, a data input / output terminal group is arranged along a first side of a chip. Then, the data input / output terminal lead group 12B is arranged along the first side and connected to the data input / output terminal group 30B on the chip.
The data input / output terminal group 30B includes a plurality of data input / output terminals DQ, a data input / output strobe signal terminal DQS for controlling the timing, data input / output power supply terminals VCCQ and VSSQ, and data A terminal DQM for a mask signal is included. The data input / output terminal lead group 12B is connected to the data input / output terminal DQ and the data input / output strobe signal terminal DQS, and is arranged along the first side of the chip. In the device after the above, lead terminals 12B for data input / output terminals are arranged in a line along the first side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device using a semiconductor substrate or the like and a module equipped with the same, and more particularly, to a novel external terminal and external lead on a chip corresponding to high-speed data input / output. And an integrated circuit device such as a memory device having the configuration described above.

[0002]

2. Description of the Related Art An integrated circuit device includes a chip in which an external terminal for connecting an integrated circuit to the outside is formed in a semiconductor substrate, a plurality of leads for leading out the external terminal, an entire chip and one of the leads. And a package made of a plastic resin for covering the portion. The plurality of leads and the external terminals on the chip are connected by connection wires which are usually attached by a wire bonding method. Also, a plurality of such integrated circuit devices having a chip inside and a plurality of leads drawn outside are mounted on a small printed circuit board to form a module. When the integrated circuit device is a memory device such as a DRAM, a plurality of memory devices are mounted on a printed circuit board and used as a memory module. A plurality of connection terminals are provided on one side of the printed board of the memory module, and one side of the memory module board is mounted by being inserted into a memory module connector on the motherboard.

FIG. 1 is a diagram showing the structure of a conventional integrated circuit device. In this example, a synchronous DRAM (SDRA
M) shows the structure of the memory device 20. A memory circuit (not shown) is formed on the chip 10 made of a semiconductor substrate, and external terminals 16 are provided in a line at the center of the chip. The external terminals 16 include address terminals A0 to A1.
2. Power supply terminals VCC, VSS, command signal terminals / CS, / RAS,
/ CAS, / WE, clock CLK, data input / output terminal DQ0
To DQ15, power supply terminals VCCQ and VSSQ for input / output terminals, input / output mask signal terminals DQMU and DQML, and the like. By arranging the external terminals in a line at the center of the chip 10 in this manner, it is possible to lay out the wiring inside the chip symmetrically and to have a uniform length, which is convenient as a high-speed memory device. .

In order to connect to the external terminals 16 on these chips, a plurality of leads 12 are extended from the outside of the chip 10 onto the chip and are connected by wires 18. Then, the entire chip 10 and a part of the leads 12 are covered with a package 14 made of a plastic mold,
The other end of the lead 12 is drawn out. in this way,
The configuration in which the leads are extended on the chip 10 is generally called a lead-on-chip structure, and is widely used in a memory device such as a DRAM.

FIG. 2 is a diagram showing an example of a memory module on which the memory device of FIG. 1 is mounted. FIG. 2 shows a part of the case where a plurality of memory devices 20 are mounted on a module substrate 22 formed of a printed circuit board. Specifically, for example, four memory devices 20 are mounted on each of the left and right sides of the module substrate 22, but FIG. 2 only shows the two memory devices on the right side of the center. On one side of the lower side of the module substrate 22, an external terminal group connected to the leads of the memory device via the wiring in the module substrate is formed.

A common external terminal group 24 for a clock CLK, commands / CS, / RAS, / CAS, / WE, and address signals A0 to A12 common to a plurality of memory devices is concentrated in the center of the substrate 22. These are supplied to the left and right memory devices 20 in parallel by the internal wiring 25 of the module substrate 22. Therefore, these lead terminal groups are provided above each memory device 20. Further, data input / output terminals DQ0 to DQ15 unique to each memory device 20 and input / output mask signals
External terminal groups 23 for memory devices such as QM and a DQ strobe signal DQS for controlling data input / output timing are provided at positions corresponding to the positions of the respective memory devices 20. Then, as shown, the lead group and the module substrate 22 located in the lower half of the memory device are formed.
And the external terminal group 23 are connected by internal wiring. The power supplies VCCQ and VSSQ for data input / output are connected by power supply wiring (not shown).

[0007]

In recent years, a double data rate (DDR) type SDRAM has been proposed in order to further increase the data input / output speed. In this high-speed SDRAM, an address and a command signal are input in synchronization with a clock CLK.
Data input and output are performed in synchronization with rising and falling edges of a data input / output strobe signal DQS different from the clock CLK. Therefore, in addition to the data input / output terminal DQ and the data mask signal DQM for controlling the mask, the data input / output strobe signal DQS
Requires a higher speed operation, and therefore, it is preferable that the wiring lengths in the module substrate in the memory module are substantially the same for the reason of timing control.

However, as shown in FIG. 2, in the conventional memory device structure, a data input / output terminal DQ, a data mask signal DQM, and a data input / output strobe signal DQS are provided on both sides of the memory device 20. The length of the wiring connected to the external terminal group on the lower side is not uniform. In the example of FIG. 2, one of the wirings on the board for the same data input / output terminals DQ1 and DQ14 is extremely shorter than the other. Further, one of the wirings on the substrate for the data mask signals DQM and DQL is long and the other is short. All of these signals are required to have the same timing on the memory device for the reason of high-speed operation, but the variation in the length of the wiring in the substrate as described above does not satisfy the requirement. Can not.

Further, in the example of FIG. 2, the data input / output terminal DQ1 and the data mask signal DQS are compared with the length of the wiring of the data input / output strobe signal DQS in the module substrate.
The QML also has a longer length in the module substrate and becomes unbalanced, causing a difference between the timing of the strobe signal DQS and the timing of the data input / output terminal DQ1 and the data mask signal DQML. Loss of synchronization. In addition, the wiring length of some data input / output terminals and data mask signals within the module substrate becomes longer, and the waveform of the propagation signal due to the wiring capacitance there is distorted, so that the input / output voltage level standard can be satisfied. Disappears.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit device suitable for equalizing the lengths of all wirings in a module substrate connected to data input / output terminals and the like, and a module using the same. is there.

It is a further object of the present invention to provide an integrated circuit device suitable for minimizing the length of wiring in a module substrate connected to data input / output terminals and the like, and a module using the same. .

It is a further object of the present invention to provide an integrated circuit device suitable for facilitating the arrangement of common in-board wiring connected to address and command signal terminals and a module using the same. .

[0013]

According to the present invention, a data input / output terminal group is arranged along a first side of a chip. Then, a data input / output terminal lead group is arranged along the first side and connected to the data input / output terminal group on the chip. The data input / output terminal group includes a plurality of data input / output terminals DQ, a data input / output strobe signal terminal DQS for controlling the timing, data input / output power supply terminals VCCQ and VSSQ, and a data mask as required. A signal terminal DQM is included. These data input / output terminal leads are connected to the data input / output terminal DQ and the data input / output strobe signal terminal DQS, and are arranged along the first side of the chip. In a later device, lead terminals for data input / output terminals are arranged in a line along the first side.

Therefore, even if a plurality of the integrated circuit devices are mounted on the module substrate, the external terminals for the data input / output terminals are arranged on the side of the module substrate opposite to the first side, and the lead terminals are provided. It is possible to connect to the group with the shortest distance and the same length of wiring in the substrate.

The data input / output terminal group includes a plurality of power supply terminals VCCQ and VSSQ for data input / output circuits. The pitch of the leads tends to be larger than the pitch of the external terminals in the chip. Therefore, according to the present invention, the leads for the power supply terminal group for the data input / output circuit have a lead-on-chip structure extended on a chip, and the plurality of data arranged on the first side of the integrated circuit device are provided. The width of the input / output lead group is balanced with the width of the data input / output terminal group on the chip.

According to the present invention, there is provided an integrated circuit device having a plurality of data input / output terminals, wherein an integrated circuit is formed, and the plurality of data input / output terminals are connected to the plurality of data input / output terminals along a first side. A chip on which a data input / output terminal group having an output power supply terminal is formed; and data arranged along a first side facing the first side and connected to a data input / output terminal on the chip An input / output terminal lead group, an input / output power supply terminal lead extended on the chip and connected to the data input / output power supply terminal, and a package part covering the chip and a part of the lead; It is characterized by.

Further, in the above invention, one end of the data input / output power supply terminal lead is extended on the chip, and the other end is on the first side of the package section, It is characterized by being disposed outside the output terminal lead group.

Further, in the above invention, the data input / output terminal group further includes a data input / output strobe signal terminal for controlling data input / output timing. And a common signal terminal group including a clock terminal for controlling the timing of (1) is arranged on a side different from the first side.

Further, in the above invention, the input / output power supply terminal lead has a multilayer structure having a high power supply lead and a low power supply lead on the chip. The power supply capacitor is characterized in that a dielectric layer is interposed between the power supply capacitor and the power supply capacitor.

Further, in the above invention, a common signal terminal lead group connected to the common signal terminal group has one end extending to the vicinity of the common signal terminal group on the chip, and the other end connected to the package. Second or third adjacent to the first side of
Is drawn out to the outside on the side of.

In order to achieve the above object, a second invention relates to a module, wherein a plurality of integrated circuit devices of the invention are mounted side by side on a module substrate, and a first side of the integrated circuit device is First of the module substrate
And the data input / output terminal lead group is connected to the module external terminal group provided along the first side of the module substrate by wiring in the substrate at opposing positions. It is characterized by having been done.

To achieve the above object, a second invention relates to a module, wherein a plurality of integrated circuit devices according to the invention are mounted side by side on a module substrate, and a first side of the integrated circuit device is First of the module substrate
And the data input / output terminal lead group is connected to the module external terminal group provided along the first side of the module substrate by wiring in the substrate at opposing positions. The common signal terminal lead group of the plurality of integrated circuit devices is connected in parallel with a module common signal terminal wiring arranged on the module substrate.

According to the above invention, the data input / output terminal unique to the semiconductor device and the strobe signal terminal thereof are connected to the lead group at the same distance from the device, and the lead group is connected to the shortest and equal distance. Is connected to the external terminal of the module substrate.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. However, such embodiments do not limit the technical scope of the present invention.
INDUSTRIAL APPLICABILITY The present invention can be applied to a wide variety of integrated circuit devices including memory modules and modules thereof. However, in the following embodiment, a memory module and its module will be described as an example.

FIG. 3 is a diagram showing a memory device according to the first embodiment. In this example, the data input / output terminal group 30 is arranged along a first side which is a lower side of the chip 10.
B is arranged. The data input / output terminal group 30B includes data input / output terminals DQ0 to DQ15, a data input / output strobe signal terminal DQS for controlling the data input / output timing, and a data input / output mask for controlling the data input / output mask timing. Signal terminals DQML, DQMU
including. Further, the data input / output terminal group 30B includes data input / output power supply terminals VCCQ and VSSQ supplied to a data input / output circuit formed on the chip 10 (not shown). It is provided between input / output terminal groups.

A common signal terminal group 30A is arranged along an upper side different from the first side of the chip 10. The common signal terminal group 30A includes address terminals A0 to A12,
Command terminals / CS, / RAS, / CAS, / WE and clock terminal CL
K, a clock enable terminal CKE, and power supplies VCC and VSS.

The memory device according to the first embodiment is further provided with lead groups 12A and 12B for leading external terminal groups of the chip to the outside. First of chip 10
The data input / output terminal lead group 3
3 are arranged. This data input / output terminal lead group 33
Are the data input / output terminals DQ0 to DQ15, the data input / output mask terminals DQML and DQMU, and the data strobe signal terminal D
Includes leads connected to QS. These lead groups 33
Are arranged such that the lateral width thereof is substantially equal to the width of the first side on which the input / output terminal group 30B in the chip 10 is arranged. The lead group 33 is directly connected to a corresponding terminal in the data input / output terminal group 30B provided on the first side of the chip 10 by a wire.

Normally, the pitch of the external terminal group 30B on the chip 10 is smaller than the lead group 12B connected thereto. Therefore, it is difficult to match the widths of the two. Therefore, in the first embodiment, among the external terminal group 30B formed on the first side of the chip, four pairs of data input / output power supply terminals VCCQ and VSSQ are provided on the chip 10. Extending power supply leads 34, 36 are provided, and are connected to the power supply leads 34, 36 via wires, instead of the leads arranged at positions facing the first side. Then, the power leads 34 and 36 bypass the sides on both sides of the first side, and extend to the first side (the lower side in the figure) of the package 14 facing the first side. As a result, the power supply leads 34 and 36 also become the data input / output terminal lead group 33.
Are arranged on the same side as.

On the other hand, the lead group 12A for the common signal terminal group 30A that is commonly connected when the memory module configuration such as the address terminal and the command terminal is formed is the chip 1
0 are arranged side by side on the side opposite to the upper side. These lead groups 12A are also connected to the common signal terminal group 30A.
And the corresponding terminals are connected by wires. When a package 14 made of plastic resin is provided to cover the chip 10 and one end of the lead groups 12A and 12B, the data input / output terminal leads 12B are arranged in a line along the lower side of the package 14, and the upper side of the package 14 Are arranged in a line along the common terminal lead group 12A.

FIG. 4 is a diagram showing a memory device according to the second embodiment. In this example, the configuration of the chip 10 is the same as that of the first embodiment. That is, the data input / output terminal group 30B is disposed on the first side located on the lower side of the chip 10, and the data input / output terminal lead group 12B is disposed opposite thereto. In addition, lead group 12
At both ends of B, power supply leads 34 and 36 having a lead-on-chip structure connected to four pairs of power supply terminals arranged in the data input / output terminal group 30B are drawn out. Further, a common signal terminal group 12A is provided on the upper side of the chip 10, and a common signal terminal lead group 12A is provided facing the common signal terminal group 12A, and the corresponding terminals and leads are connected via wires.

In the second embodiment, the power supply leads 38 and 39 connected to the power supplies VCC and VSS arranged in the common signal terminal group 30A have a lead-on-chip structure, and It is drawn out to both ends of the use lead group 12A. Then, the data input / output power supply leads 34, 36
Have a relatively large area on the chip 10 and are formed in a hierarchical structure. A dielectric layer (not shown) is formed between the data input / output power supply leads 34 and 36, and the leads 34 and 36 and the dielectric layer form a first chip capacitor. That is, the first chip capacitor inserted between the data input / output power supplies is formed using a wide area on the chip 10, and a relatively large capacitance can be realized. The first chip capacitor absorbs noise between data input / output power supplies.

The power supply lead 3 on the common signal terminal side
8 and 39 also have a lead-on-chip structure, have a relatively large area on the chip 10, and are formed in a hierarchical structure. Then, these common signal power supply leads 38, 3
9, a dielectric layer (not shown) is formed.
Is formed. This second chip capacitor can also absorb noise between the two power supplies VCC and VSS. Also in the memory device according to the second embodiment, when a package 14 made of a plastic resin covering one end of the chip 10 and the lead groups 12A and 12B is provided, the data input / output terminals are arranged in a line along the lower side of the package 14. And the common terminal lead group 12A is arranged in a line along the upper side of the package 14.
Is arranged.

FIG. 5 is a diagram showing a memory module on which the first and second memory devices are mounted. In the first and second memory devices, the data input / output terminal lead group 12B is provided along the first side, and the common signal terminal lead group 12A is provided along the upper side opposed to the first side. The plurality of memory devices 20 include, as shown in FIG.
The first side is arranged so as to face the lower side of the module substrate 22. Therefore, the individual data input / output terminal lead group 12B of the memory device 20 is
Among the external terminal groups for modules formed along the lower side of the module 2, the external terminal group for data input / output 23 is disposed to face. Therefore, the lead group 12B and the external terminal group 23 can be connected by the module wiring 56 having the shortest and the same length.

On the other hand, the common signal lead group 12A of each memory device 20 is arranged along the upper side facing the first side. Therefore, it is connected to the common signal external terminal group 24 in the module external terminal group arranged on the lower side of the module substrate 22, and is connected in parallel to the plurality of memory devices 20 arranged on the left and right in the module wiring 25. Can be provided. Although not shown, the wiring 25 in the module includes a clock CLK, address signals A0 to A1.
2. Lead 12A for command signal / CS, / RAS, / CAS, / WE
Has a plurality of wiring groups to be connected.

According to the above-described memory module configuration, the module external terminal 23 relating to data input / output signals required to operate at high speed, the memory device read group 12B,
And the terminal group 30B in the chip are connected by the shortest intra-module wiring 56, the lead 12B, and the wire at substantially the same distance. Therefore, the timing consistency is ensured for the high-speed operation, and the problem of the rounding of the signal waveform is solved.

FIG. 6 is a diagram showing a memory device according to the third embodiment. In this example, similarly to the first embodiment, the data input / output terminal group 30B is provided on the first side (lower side) of the chip 10, and the common signal terminal group 30A is provided on the upper side opposed thereto. Can be Similarly to the first embodiment, a lead group 12B is arranged to face the data input / output terminal group 30B. The four pairs of power supply terminals VCCQ and VSSQ in the data input / output terminal group 30B are connected to power supply leads 34 having a lead-on-chip structure.
36 is provided extending on the chip and connected to a power supply terminal on the chip by a wire. Then, the other ends of the power leads 34, 36 are drawn out to both ends of the lead group 12B.

A characteristic point of the third embodiment is that all the lead groups connected to the common signal terminal group 30A have a lead-on-chip structure, and the left half of the lead group 12C is a chip-on-chip structure. 10 is drawn on the left side to the first side. The lead group 12D in the right half is
The chip 10 is pulled out on the right side with respect to the first side. The arrangement of these lead groups 12C and 12D facilitates connection with the wiring inside the module board when mounted on the module board.

FIG. 7 is a diagram showing a memory device according to the fourth embodiment. In this example, the data input / output terminal group 20B and its lead group 12B are the same as in the third embodiment. The difference from the third embodiment is that an address signal, a command signal, a clock CLK,
The point is that the common signal terminal group including the clock enable CKE and the power supply is separately arranged on the left and right sides of the chip 10. Lead groups 12C and 12D are provided at positions facing the common signal terminal groups 30C and 30D, respectively, and are connected via wires.

In the fourth embodiment, the common signal terminal groups 30C and 30D on the chip may be arranged in a line at the center of the chip 10 as shown in FIG. A lead-on-chip lead group is provided for the common signal terminal group arranged in the center of the chip as shown in FIG. 1 and connected by wires, and the lead group is divided into left and right sides. You may pull it out.

In the third and fourth embodiments described above, the data input / output terminal lead group 12B is arranged on the first side of the package 14, and the common signal terminal lead groups 12C and 12D are provided. It is arranged separately on the left and right sides of the package 14.

FIG. 8 is a diagram showing a memory module on which the third and fourth memory devices are mounted. In this memory module also, a module external terminal group is formed on the lower side of the module substrate 22. And the memory device 2
Lead group 12 formed along the lower side (first side)
B is directly connected to the opposing module external terminal group 23 by the shortest wiring 56 having the same length. Furthermore, in the third and fourth memory devices, the common signal terminal lead groups 12C and 12D are formed along the left and right sides on both sides of the first side, so that the wiring in the module that connects them in common is provided. 25 is also provided so as to extend along the lateral direction. Although not shown, a clock CL is connected to the wiring 25.
K, clock enable CKE, addresses A0 to A1
2, and the respective wirings connected to the leads for the command are connected in parallel with the common signal terminal lead groups 12C and 12D of each memory device. The wiring 25 is connected to the module external terminal 24 on the lower side of the module substrate 22.

Also in the memory module shown in FIG. 8, the module external terminals 23 relating to data input / output signals required to operate at high speed, the lead group 12B of the memory device, and the terminal group 30B in the chip are substantially equidistant from each other. The shortest in-module wiring 56, leads 12B and wires are connected. Therefore, the timing consistency is ensured for the high-speed operation, and the problem of the rounding of the signal waveform is solved.

The present invention is not limited to memory devices or memory modules. The present invention is also applicable to an integrated circuit device having a signal terminal required to operate at high speed, a lead thereof, and a module having a plurality of such terminals.

[0044]

As described above, according to the present invention, the data input / output terminal can be arranged on the first side of the chip, and the lead group can be arranged opposite to the first side. In addition, in the case of a module configuration, a group of external terminals for modules and a group of leads arranged on one side of the module substrate can be provided close to each other so as to be opposed to each other, and can be connected by the same module wiring in the shortest time. Therefore, the connection of the data input / output terminal group, which requires high-speed operation, to the lead group and the module external terminal group can be realized with the shortest and the same length.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of a conventional integrated circuit device.

FIG. 2 is a diagram illustrating an example of a memory module equipped with the memory device of FIG. 1;

FIG. 3 is a diagram illustrating a memory device according to the first embodiment;

FIG. 4 is a diagram illustrating a memory device according to a second embodiment;

FIG. 5 is a diagram showing a memory module on which first and second memory devices are mounted.

FIG. 6 is a diagram illustrating a memory device according to a third embodiment;

FIG. 7 is a diagram illustrating a memory device according to a fourth embodiment;

FIG. 8 is a diagram showing a memory module equipped with third and fourth memory devices.

[Explanation of symbols]

 Reference Signs List 10 chip 12 lead 14 package, plastic mold 30A common signal terminal group 30B data input / output terminal group 12A common signal terminal lead group 12B data input / output terminal lead group

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yasuo Matsuzaki 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa F-term within Fujitsu Limited 5F067 BE10 CD00 CD03

Claims (7)

[Claims] 1. An integrated circuit device having a plurality of data input / output terminals, wherein an integrated circuit is formed, and the data input / output terminal includes a plurality of data input / output terminals and a data input / output power supply terminal along a first side. A chip on which an output terminal group is formed; a data input / output terminal lead group arranged along a first side facing the first side and connected to a data input / output terminal on the chip; An integrated circuit device comprising: a lead for an input / output power supply terminal that is extended on a chip and connected to the data input / output power supply terminal; and a package part that partially covers the chip and the lead. 2. The data input / output power supply terminal lead according to claim 1, wherein one end of the data input / output power supply terminal lead is extended on the chip, and the other end of the data input / output power supply terminal lead is connected to the first part of the package part.
, And arranged outside the data input / output terminal lead group. 3. The data input / output terminal group according to claim 1, further comprising: a data input / output strobe signal terminal for controlling data input / output timing. An integrated circuit device, wherein a common signal terminal group including a clock terminal for controlling the timing of the common signal terminal is arranged on a side different from the first side. 4. The input / output power supply terminal lead according to claim 1, wherein the input / output power supply terminal lead has a multilayer structure having a high power supply lead and a low power supply lead on the chip. An integrated circuit device comprising a power supply capacitor with a dielectric layer interposed between the power supply lead and a low power supply lead. 5. The common signal terminal lead group connected to the common signal terminal group, one end of the lead group extending to the vicinity of the common signal terminal group on the chip, and the other end of the common signal terminal lead group being connected to the package. The integrated circuit device is drawn out on a second or third side adjacent to the first side of the integrated circuit device. 6. A plurality of integrated circuit devices according to claim 1 are mounted side by side on a module substrate, and a first side of the integrated circuit device is connected to a first side of the module substrate.
And the data input / output terminal lead group is connected to the module external terminal group provided along the first side of the module substrate by wiring in the substrate at opposing positions. A module characterized by being performed. 7. A plurality of integrated circuit devices according to claim 5 are mounted side by side on a module substrate, and a first side of the integrated circuit device is connected to a first side of the module substrate.
And the data input / output terminal lead group is connected to the module external terminal group provided along the first side of the module substrate by wiring in the substrate at opposing positions. A module, wherein a group of common signal terminal leads of the plurality of integrated circuit devices is connected in parallel with a module common signal terminal wiring disposed on the module substrate.