JP2000222876A - Semiconductor storage device - Google Patents

Abstract

(57) [Problem] To provide two transistors and one transistor in one memory cell
In a semiconductor memory device having two capacitors, among bit lines adjacent to each other, interference noise generated on one bit line is prevented from being mixed into the other bit line. SOLUTION: In a read operation Tre, a port b
During the period in which the second precharge signal EQb controlling the second bit line BLb (n) is at a low level and the second sense amplifier activation signal SEb is held at a high level. The first precharge signal EQa for controlling one bit line BLa (n) and the first sense amplifier activating signal SEa are both at a low level, the first bit line BLa (n) is in a floating state, and subsequently, , The first sense amplifier activation signal SEa rises.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device comprising a dynamic random access memory circuit and the like, and more particularly to a semiconductor memory device having two transistors and one storage capacitor in one memory cell.

[0002]

2. Description of the Related Art U.S. Pat. No. 5,856,940 discloses a memory cell having two transistors and one storage capacitor, each of which is connected to two word lines and two bit lines. The "low latency DRAM cell" using the dual word line and dual bit line method will be described with reference to the drawings.

FIG. 7 shows a circuit configuration of a memory cell of a conventional semiconductor memory device having a DRAM with a reduced waiting time. The memory cell 100 shown in FIG. 7 has, for example, a first switch transistor 10 having a gate connected to the first word line WL0A, a drain connected to the first bit line BL0A, and a source connected to the storage node 101.
2, a second switch transistor 103 having a gate connected to the second word line WL0B, a drain connected to the second bit line BL0B, a source connected to the storage node 101, and one electrode connected to the storage node 1
01, and the other electrode has a storage capacitor 104 serving as a cell plate.

As described above, the memory cell 100 has the first switch transistor 102 and the second switch transistor 103 that can independently control one storage capacitor 104. Accordingly, in the plurality of memory cells 100, the first word line WL0A and the first word line WL0A
Of the bit line BL0A and the second word line WL0B and the second bit line BL0B, so that the read operation and the write operation can be performed at high speed.

[0005]

However, the conventional semiconductor memory device having a DRAM cell with a reduced waiting time has the following problems.
Since the first bit line system BLnA and the second bit line system BLnB operate independently of each other to perform an interleave operation on adjacent bit lines, coupling noise caused by a change in bit line potential at this time is reduced. There is a problem of mixing in adjacent bit lines. Due to the coupling noise, the data value held by the memory cell 100 may be inverted in the worst case.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problem. In a semiconductor memory device having two transistors and one capacitor in one memory cell, it occurs in one of bit lines adjacent to each other. An object is to prevent interference noise from being mixed into the other bit line.

[0007]

In order to achieve the above-mentioned object, the present invention provides a method for controlling a state in which a precharge signal in one bit line system is kept active or a sense amplifier activation signal is kept active. A precharge signal or a sense amplifier activating signal in the other bit line system is set to an inactive state.

More specifically, the semiconductor memory device according to the present invention includes a first switch transistor and a second switch transistor each having a source connected to each other,
A plurality of memory cells each including a storage capacitor for data storage having one electrode connected to the source; a plurality of first bit lines each connected to the drain of the first switch transistor; And a plurality of first sense amplifiers connected to the drains of the second switch transistors and alternately provided with the first bit lines, and a plurality of first sense amplifiers each connected to the plurality of first bit lines. And a plurality of second sense amplifiers respectively connected to the plurality of second bit lines, and a first precharge signal or a plurality of first precharge signals for performing precharge for each of the plurality of first bit lines. A second precharger that performs precharge for each of the plurality of second bit lines while the first sense amplifier activating signal for activating the sense amplifier is kept active; Second sense amplifier activating signal for activating the second sense amplifier di- signals and a plurality are both inactivated.

According to the semiconductor memory device of the present invention, for example, when the data held in the memory cell is read from the second bit line, the second precharge applied to the second bit line After the signal is turned off, the second switch transistor is activated,
The charge stored in the storage capacitor flows into the second bit line. Usually, at this time, the second sense amplifier activation signal is in an inactive state, so that the second sense amplifier is not driven. At this time, the first precharge signal or the first sense amplifier activating signal applied to the first bit line adjacent to the second bit line is kept active.

Therefore, first, when the first precharge signal is held at a high level and the first sense amplifier activating signal is held at a low level, the first bit line is precharged to a low level. Since the state is in the impedance state, the first bit line in the low impedance state functions as a shield line even if the second sense amplifier activation signal goes high to activate the second sense amplifier thereafter. .

When the first precharge signal is held at a low level and the first sense amplifier activating signal is held at a high level, the potential of the first bit line becomes high or low. Is in a low-impedance state and the second sense amplifier activating signal subsequently goes high to activate the first bit in a low-impedance state even if the second sense amplifier is activated. The wire functions as a shield wire.

In the semiconductor memory device of the present invention, it is preferable that the signal levels of the first precharge signal and the second sense amplifier activating signal change at one operation timing of the synchronization clock signal. Here, for example, the first precharge signal and the first sense amplifier activation signal are changed at one operation timing of the synchronization clock signal, and the second precharge signal and the second sense amplifier activation are changed. In a configuration in which the signal changes at another operation timing of the synchronization clock signal, when the period of the synchronization clock signal is changed, the first precharge signal and the second precharge signal are changed.
Since the relative timing of the change of the sense amplifier activation signal is shifted, the first precharge signal changes when the second precharge signal and the second sense amplifier activation signal are inactive. That can happen. However, if the first precharge signal and the second sense amplifier activating signal are configured to change at one operation timing of the synchronization clock signal, the first precharge signal and the second sense amplifier activation signal are changed even if the clock cycle is changed. And the relative timing of the second sense amplifier activating signal does not shift, so that the first precharge signal changes when the second precharge signal and the second sense amplifier activating signal are inactive. I won't.

In the semiconductor memory device of the present invention, data stored in the storage capacitor is transferred to the second bit line when both the second precharge signal and the second sense amplifier activation signal are inactive. Preferably, it is read. With this configuration, at the time of reading data to the second bit line selected from the outside, interference noise generated from the second bit line is shielded by the adjacent first bit line.

In the semiconductor memory device of the present invention, it is preferable that data stored in the storage capacitor is written when both the second precharge signal and the second sense amplifier activation signal are in an inactive state. With this configuration, at the time of writing data to the second bit line selected from the outside, the interference noise generated from the second bit line is shielded by the adjacent first bit line.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a schematic plan configuration of a memory cell array in a semiconductor memory device according to one embodiment of the present invention. As shown in FIG. 1, the memory device according to the present invention employs an open bit line configuration that does not have a complementary bit line pair adjacent to one sense amplifier SAa or SAb. Therefore, the first bit lines BLa (n) and the second bit linear BLb (n) (where n = 0, 1, 2,...) Each extending in the row (row) direction are provided alternately. .

A first sense amplifier system circuit 10A is provided at one end of the first bit line BLa (n).
A second sense amplifier circuit 10B is provided at an end of the second bit line BLb (n) opposite to the first sense amplifier 10A.

Each of the first bit lines BLa
(N) and a first bit line crossing the second bit line BLb (n).
Word line WLa (m) and second word line WLb
(M) (where m = 0, 1, 2, 3,...) Are provided so as to extend alternately in the column (row) direction.

As shown in FIG. 1, the first word line WLa
Memory cells 20 are provided in regions surrounded by (m) and the second word line WLb (m) and the first bit line BLa (n) and the second bit line BLb (n), respectively. ing. Here, the memory cell 20 is referred to as a 2T1C cell.

FIG. 2 shows a 2T1C cell 20 according to this embodiment.
The circuit configuration of FIG. As shown in FIG. 2, 2T1C
The cell 20 has a first switch transistor 22 having a gate connected to the first word line WLa, a drain connected to the first bit line BLa, a source connected to the storage node 21, and a gate connected to the second switch transistor 22. A second switch transistor 23 connected to the word line WLb, the drain connected to the second bit line BLb, the source connected to the storage node 21, one electrode connected to the storage node 21, and the other electrode connected Have a storage capacitor 24 serving as a cell plate.

Here, for convenience, the 2T1C cell 20
First word line WLa (m) and first bit line BLa
One system accessed by (n) is called port a,
Second word line WLb (m) and second bit line BLb
The other system accessed by (n) is called port b.

FIG. 3 shows an example of a detailed circuit configuration of the first sense amplifier circuit 10A shown in FIG. As shown in FIG. 3, the first sense amplifier circuit 10A is a sense amplifier circuit of a port a, and a first memory cell array 31 connected to one of the first bit lines BLa.
And a second memory cell array 32 connected to the other first bit line BLXa extending on the opposite side of one first bit line BLa with respect to first sense amplifier circuit 10A.
Are provided.

The first sense amplifier system circuit 10A includes a sense amplifier main body 40 which reads out from the selected 2T1C cell 20 and amplifies a small potential difference generated between the first bit lines BLa and BLXa, and the sense amplifier main circuit 40A. A precharge / equalize circuit 50 provided between the amplifier main body 40 and the first memory cell array 31 for equalizing the first bit lines BLa and BLXa with each other;
0, which is provided between the first memory cell array 32 and the second memory cell array 32 and outputs the potential difference amplified by the sense amplifier body 40 as read data.
0 and a write switch circuit 70 that is provided between the sense amplifier main body 40 and the direct sense read amplifier 60 and writes externally input data to the first bit lines BLa and BLXa.

The sense amplifier body 40 has a gate receiving the first sense amplifier activation signal SEa, a drain connected to the sense amplifier body 40, a source grounded, and a ground potential supplied to the sense amplifier body 40. n-type switch transistor 81 and inverter 82 for inverting and outputting the polarity of first sense amplifier activation signal SEa
And a p-type switch transistor 83 having a gate receiving the output of the inverter 82, a drain connected to the sense amplifier main body 40, a power supply potential applied to the source, and supplying the power supply potential to the sense amplifier main body 40. It is connected to the circuit 80.

The sense amplifier body 40 has a gate connected to one first bit line BLa, a source connected to a ground line from the sense amplifier drive circuit 80, and a drain connected to the other first bit line BLXa. The first n-type transistor 41 and the gate of the other first bit line BL
Xa, a second n-type transistor 42 having a source connected to the ground line from the sense amplifier driving circuit 80 and a drain connected to one first bit line BLa,
First p-type transistor 43 having a gate connected to one first bit line BLa, a source connected to a power supply line from sense amplifier drive circuit 80, and a drain connected to the other first bit line BLXa. And a second p-type having a gate connected to the other first bit line BLXa, a source connected to a power supply line from the sense amplifier driving circuit 80, and a drain connected to the first bit line BLa. And a transistor 44.

Here, assuming that one of the first bit lines BLa is activated with a potential slightly higher than that of the other first bit line BLXa, for example, the sense amplifier body 40 has a first n-type. When the transistor 41 and the second p-type transistor 44 start driving, the first n-type transistor 41 sets the potential of the other first bit line BLXa to low level, and the second p-type transistor 4
4 boosts one of the first bit lines BLa to a high level which is a power supply potential. Thereby, the first bit line B
The potentials read out to La and BLXa are fixed to the high level or the low level, respectively.

The precharge equalizing circuit 50 has a gate receiving the first precharge signal EQa,
The drains are respectively connected to the first bit lines BLa and BLXa, the equalizing transistor 51 for equalizing the potentials of the first bit lines BLa and BLXa, the gate receives the first precharge signal EQa, and the source is connected to one side. A first precharge transistor 52 connected to the first bit line BLa, and having a drain to which the precharge power supply VBLP is applied, and a gate connected to the first precharge signal EQ.
and a second precharge transistor 53 whose source is connected to the other first bit line BLXa and whose drain is applied with the precharge power supply VBLP.

The direct sense read amplifier 60 has a gate receiving the potential of one first bit line BLa and a first n-type switch transistor 61 whose source is grounded.
And a second n-type switch transistor having a gate receiving the first read control signal REa, a source connected to the drain of the first n-type switch transistor 61, and a drain connected to one first data line DLa. And a third n-type switch transistor 63 whose gate receives the potential of the other first bit line BLXa and whose source is grounded.
And a fourth n-type switch transistor whose gate receives the first read control signal REa, whose source is connected to the drain of the third n-type switch transistor 63, and whose drain is connected to the other first data line DLXa 64.

The write switch circuit 70 has a gate receiving a first write control signal WTa having a decoding function, and has a source and a drain connected to one first bit line BLa and one first data line DLa, respectively. The first n-type switch transistor 71, the gate of which receives the first write control signal WTa, and the source and drain of which are connected to the other first bit line BLXa and the other first data line DLXa, respectively. And two n-type switch transistors 72.

Although the detailed configuration of only the first sense amplifier system circuit 10A has been described here, the configuration of the second sense amplifier system circuit 10B for amplifying a minute potential difference between the second bit lines BLb and BLXb is also described. Assume that it is equivalent to the first sense amplifier circuit 10A.

Hereinafter, the operation of the semiconductor memory device configured as described above will be described with reference to the drawings.

FIG. 4 shows operation timings of a read operation and a write operation in the semiconductor memory device according to the present embodiment.

First, the read operation period Tre shown in FIG.
Will be described.

First, as shown in FIG. 4, four read commands RD0 to RD3 continuously inputted from the outside are received as a command Cmd, and simultaneously inputted address signals are sequentially received as address signals add0 to add3. In the present apparatus, a first clock signal CLKa for a port a having a cycle twice as long as a system clock signal CLK serving as a synchronization signal of the entire apparatus and a port performing an operation complementary to the first clock signal CLKa. b for the second clock signal CLKb.

Here, for example, the address signal add0
And add2 access port a, and address signal a
The case where dd1 and add3 access port b will be described. Further, in the memory cell array shown in FIG. 1, for example, a first word line WLa (0) is selected by an address signal add0, a second word line WLb (0) is selected by an address signal add1, and an address signal add2. It is assumed that the first word line WLa (0) is selected and the second word line WLb (0) is selected by the address signal add3.

Accordingly, next, the first clock signal CLK of the port a during the read operation period Tre shown in FIG.
Triggered by the first rising edge of a, the first precharge signal EQa changes from the active state to the inactive state, and the first word line signal WLa changes from the inactive state to the active state. At this time, the first sense amplifier activation signal S
Since Ea is inactive, the first bit line BLa
(N) (where n = 0, 1, 2, 3,...) Is in a floating state, and the charge moves between the selected first word line WLa and the 2T1C cell 20 connected to the selected first word line WLa. The potential of the first bit line BLa (n) slightly changes.

Next, as shown in FIG. 4, when the first sense amplifier activating signal SEa transitions from the inactive state to the active state, the sense amplifier driving circuit 80 shown in FIG.
Is activated, and the potential of the first bit line BLa (n) is determined by the operation of the sense amplifier body 40 described above.

Next, when the first read control signal REa is activated, the direct sense read amplifier 60 shown in FIG. 3 is activated, and the bit line potential is applied to the first data line DLa or DLXa. The inverted read data is output.

Next, the first falling edge of the first clock signal CLKa is used as a trigger to trigger the first word line signal WL.
a transitions to the inactive state, the first sense amplifier activation signal SEa and the first read control signal REa.
a becomes inactive, and the access to the first bit line BLa (n) ends.

On the other hand, as shown in FIG. 4, the second precharge signal EQb also transitions from the active state to the inactive state at the port b, triggered by the first rise of the second clock signal CLKb. Second word line signal W
Lb transitions from the inactive state to the active state. At this time,
Since the second sense amplifier activating signal SEa is in an inactive state, the second bit line BLb (n) is in a floating state, and the second bit line BLb (n) is in a floating state between the selected second word line WLb and the 2T1C cell 20 connected thereto. , The potential of the second bit line BLb (n) slightly fluctuates.

Next, as shown in FIG. 4, when the second sense amplifier activating signal SEb transitions from the inactive state to the active state, the potential of the second bit line BLb (n) is determined, Further, when the second read control signal REb is activated, read data is output to the second data line DLb.

Next, following the transition of the second word line signal WLb to the inactive state, the second sense amplifier activating signal SEb and the second read control signal REb enter the inactive state. Of the bit line BLb (n) is terminated.

Next, the first clock signal C shown in FIG.
With the next rise of LKa as a trigger, the first precharge signal EQa transitions from the active state to the inactive state again, and the first word line signal WLa transitions from the inactive state to the active state. At this time, since the first sense amplifier activation signal SEa is in an inactive state, the first bit line BLa (n) is in a floating state, and the 2T1C cell 20 connected to the selected first word line WLa. Between the first bit line BL and the first bit line BL.
The potential of a (n) slightly fluctuates, and subsequently, the first sense amplifier activation signal SEa transitions from the inactive state to the active state, whereby the potential of the first bit line BLb (n) is determined. I do. At this time, the second bit line B of the port b
In Lb (n), the second precharge signal EQb
Is in a low level inactive state, and the second sense amplifier activating signal SEb is held in a high level active state, so that the second bit line BLb (n) is in a low impedance (Lo-Z) state. It is in.

As described above, as a feature of the present embodiment, in the read operation period Tre, the port a is in the selected state, and the first bit line BLa (n) is connected to the first precharge signal EQa and the first sense line. During the floating state in which the amplifier activation signals SEa are both inactive, the sense amplifier body 40
Is activated, the port b retains the active state of the second precharge signal EQb at the high level and the second sense amplifier activation signal SEb at the inactive state of the low level. Is held. This allows
The second bit line BLb (n) of the port b shown in FIG. 1 is held at the precharge potential VBLP, is in a low impedance state, and is in a floating state.
Since the potential of the second bit line BLb adjacent to La is fixed at the precharge potential VBLP, interference from the second bit line BLb to the first bit line BLa can be prevented.

The second operation in the read operation period Tre
When port a is selected at the next rising of clock signal CLKb, first bit line BLa
(N) is during a floating state in which both the first precharge signal EQa and the first sense amplifier activating signal SEa are inactive, and during a period during which the sense amplifier body is activated from this floating state. , Port b, the second precharge signal EQb is held in a low-level inactive state, and the second sense amplifier activation signal SEb is held in a high-level active state. Thereby, the second bit line BLb shown in FIG.
(N) is a low-impedance state by the active sense amplifier main body, and the first state in the floating state.
Bit line BLa adjacent to the second bit line BLa
b is fixed at a high level or a low level, the second bit line BLb to the first bit line BLa
Interference can be prevented.

It is needless to say that interference between the first bit line BLa of the port a and the second bit line BLb of the port b can be prevented by changing the reading order of the port a and the port b.

Next, the write operation period Twt shown in FIG. 4 will be described.

First, as shown in FIG. 4, four write commands WT0 to WT3 successively input from the outside are received as commands Cmd, and simultaneously input address signals are sequentially received as address signals add0 to add3.

Here, for example, the address signal add0
And add2 access port a, and address signal a
The case where dd1 and add3 access port b will be described. Further, in the memory cell array shown in FIG. 1, for example, a first word line WLa (0) is selected by an address signal add0, a second word line WLb (0) is selected by an address signal add1, and an address signal add2. It is assumed that the first word line WLa (0) is selected and the second word line WLb (0) is selected by the address signal add3.

Next, the write operation period Twt shown in FIG.
Triggered by the first rising edge of the second clock signal CLKb of the port b at the port b, the second precharge signal EQb transitions from the active state to the inactive state, and the second word line signal WLb and the second write control Signal WTb transitions from the inactive state to the active state. At this time, since the second sense amplifier activation signal SEb is in an inactive state, the second bit line BLb (n) is in a floating state. At this time, in the present embodiment, the normal DR
Unlike the write operation of AM, during the floating state before the bit line potential is determined, the externally input data Din0 is selected via the second data line DLb by the second write control signal WTb. Bit line BL
b (0). Therefore, usually, the time required until the read data is determined and the time required to write a data value different from the read data value after the data determination, that is, the time required for so-called inversion writing, can be reduced. It becomes easy. Further, since the inversion writing is not performed, the driving capability of the writing circuit can be reduced, so that the circuit scale and the power consumption of the writing circuit can be reduced.

Subsequently, the second sense amplifier activating signal S
Eb is activated, the potential of the second bit line BLb (n) is determined, and the second word line WLb is deactivated, so that the storage capacitor 2 of the 2T1C cell 20
The input data value of 1 is determined.

Next, following the transition of the second word line signal WLb to the inactive state, the second sense amplifier activating signal SEb becomes inactive and the second bit line BLb
Access to (0) ends.

On the other hand, triggered by the first rising edge of the first clock signal CLKa of the port a in the write operation period Twt, the first precharge signal EQa transitions from the active state to the inactive state and the first word Line signal W
La and the first write control signal WTa transition from the inactive state to the active state. At this time, since the first sense amplifier activation signal SEa is in an inactive state, the first bit line BLa (n) is in a floating state, and data Din1 input from the outside is transmitted via the first data line DLa. Input to the first bit line BLa (1) selected by the first write control signal WTa. Then, the first
Is activated, and the potential of the first bit line BLa (n) is determined.

At this time, the second bit line BL of the port b
In b (n), the second precharge signal EQb is in a low-level inactive state, and the second sense amplifier activating signal SEb is held in a high-level active state. The line BLb (n) is in a low impedance state, and the precharge operation of the port b has not started yet.

As described above, as a feature of the present embodiment, in the write operation period Twt, the port b is in the selected state, and the second bit line BLb (n) is set to the second precharge signal EQb and the second sense. During the floating state in which the amplifier activation signals SEb are both inactive, and during the period when the sense amplifier body is activated from this floating state, the first precharge signal EQa is at the high level at the port a. Is held, and the first sense amplifier activating signal SEa is held in a low-level inactive state. As a result, the first bit line BLa (n) of the port a shown in FIG. 1 is held in the precharge potential VBLP and is in a low impedance state, so that the first bit line BLa (n) serves as a shield line. Therefore, the second bit line BLb selected by the second write control signal WTb of the port b
Even if a large potential change due to the write operation occurs in (0), it is possible to prevent the adjacent port b from interfering with another unselected second bit line BLb (1).

The first operation during the writing operation period Twt is performed.
When port a is selected at the first rise of the clock signal CLKa, the first bit line BL
a (n) is in a floating state in which the first precharge signal EQa and the first sense amplifier activating signal SEa are both inactive, and during a period in which the sense amplifier body is activated from this floating state. In the port b, the second precharge signal EQb is kept in a low-level inactive state, and the second sense amplifier activation signal SEb is kept in a high-level active state. Thereby, the second bit line BL shown in FIG.
Since b (n) is in a low impedance state by the active sense amplifier main body, the second bit line B
Since Lb (n) plays the role of a shield wire, port a
Of the first write control signal WTa selected by the first write control signal WTa.
Even if a large potential change occurs due to the write operation to the bit line BLa (1), it is possible to prevent the adjacent port a from interfering with another unselected first bit line BLa (0).

As described above, according to the semiconductor memory device having the 2T1C cell according to the present embodiment, the bit line potential BLa of each of the ports a and b in FIG.
For example, as shown in the timing chart of the potential change of BLb and BLb, when attention is paid to port a, the floating state in which the first precharge signal EQa and the first sense amplifier activation signal SEa of port a are both inactive is shown. (= High impedance state) and the subsequent period during which the first sense amplifier activating signal SEa is activated, at the port b, the active state of the second precharge signal EQb and the activation of the second sense amplifier The inactive state of the signal SEb is maintained, or the second precharge signal EQ
b and the second sense amplifier activation signal SE
The active state of b is maintained.

Therefore, the first bit line BLa of port a
And the second bit lines BLb of the port b are arranged alternately, so that the first bit lines B
When La is in a high-impedance state, the adjacent second
Bit line BLb is always in a low impedance state, and the potential of the second bit line BLb is fixed, so that interference with the adjacent first bit line BLa can be prevented. Further, at the time of the write operation, the second bit line BLb serves as a shield line of the first bit line BLa whose potential greatly changes due to the write operation,
Can be prevented from interfering with each other.

Further, as shown in the timing chart of each clock signal and the change of the bit line potential for each port in the semiconductor memory device according to the present embodiment, the first clock signal for the port a is obtained from the system clock signal CLK. And a second clock signal CLKb for the port b obtained by inverting the first clock signal CLKa, and the second clock signal CLKa triggered by the falling edge of the first clock signal CLKa. The precharge operation is started based on the transition of the first precharge signal EQa to the active state, and the second clock signal CLK has the same timing as the falling edge of the first clock signal CLKa.
The sensing operation is started based on the transition of the second sense amplifier activation signal SEb to the active state triggered by the rising edge of b.

For example, the port a uses only the rising edge of the first clock signal CLKa as a trigger of the first precharge signal and the first sense amplifier activating signal SEa, and the port b uses the second rising edge of the second clock signal CLKa. When only the rising edge of the second clock signal CLKb is used as a trigger for the precharge signal and the second sense amplifier activation signal SEb, the system clock signal CL is used.
When the operation cycle of K is changed, the floating operation of the second bit line BLb of port b and port a shown in FIG.
May overlap with the precharge operation of the first bit line BLa.

However, in the present embodiment, the first precharge signal EQa of the port a and the second sense amplifier activating signal SEb of the port b, and the second precharge signal EQb of the port b are Since the first sense amplifier activation signal SEa of the port a is changed by using one edge of the system clock signal CLK as a trigger, even if the operation cycle of the system clock signal CLK is changed, for example, Second bit line BLb
Operation of the first bit line B of the port a.
It is possible to prevent a situation in which the La precharge operation overlaps.

The first sense amplifier system circuit 10A according to the present embodiment comprises a sense amplifier body 40, a precharge / equalize circuit 50, a direct sense read amplifier 60, a write switch circuit 70, and a sense amplifier drive circuit 80. Are not limited to the configuration shown in FIG. 3 and may be other circuit configurations having equivalent functions.

[0063]

According to the semiconductor memory device of the present invention, a first precharge signal for precharging a plurality of first bit lines or a first sense amplifier for activating a plurality of first sense amplifiers is provided. A second precharge signal for precharging the plurality of second bit lines for each of the plurality of second bit lines and a second sense amplifier for activating the plurality of second sense amplifiers while the activation signal is held in the active state; Since the activation signal is in an inactive state, in this inactive state,
Since the bit line is in a floating state and the first precharge signal or the first sense amplifier activating signal is kept active, the first bit line is in a low impedance state. As a result, the potential of the second bit line adjacent to the first bit line in the floating state is fixed, so that interference from the second bit line to the first bit line can be prevented. Further, since the first bit line functions as a shield line, noise does not enter the second bit line adjacent to the second bit line in which the potential change has occurred due to the write operation, The operation of the storage device is stabilized.

In the semiconductor memory device of the present invention, when the signal levels of the first precharge signal and the second sense amplifier activating signal change at one operation timing of the synchronization clock signal, the clock cycle is changed. As
Since the relative timings of the first precharge signal and the second sense amplifier activation signal do not shift, the first precharge signal and the second sense amplifier activation signal are inactive when the first precharge signal and the second sense amplifier activation signal are inactive. Does not change, so that the function of the first bit line as a shield line can be reliably maintained.

In the semiconductor memory device of the present invention, data stored in the storage capacitor is transferred to the second bit line when both the second precharge signal and the second sense amplifier activation signal are inactive. When read,
Since the potentials of the first bit lines adjacent to each other are fixed, noise does not mix from the first bit line to the second bit line, so that the operation of the storage device is stabilized.

In the semiconductor memory device of the present invention, when data stored in the storage capacitor is written when both the second precharge signal and the second sense amplifier activating signal are inactive, the data is externally selected. When data is written to the second bit line, the interference noise generated from the second bit line is shielded by the adjacent first bit line. Since noise is not mixed into another bit line adjacent to the bit line, the operation of the storage device is stabilized. In addition, since the write operation is performed during the floating state before the bit line potential is determined, a time until the read data is determined and a data value different from the read data value after the data determination is determined. Since the writing time can be reduced, the operation can be further speeded up.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a memory cell array of a semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is a circuit diagram of a memory cell of the semiconductor memory device according to one embodiment of the present invention.

FIG. 3 is a circuit diagram of a sense amplifier circuit in the semiconductor memory device according to one embodiment of the present invention;

FIG. 4 is a timing chart showing a read operation and a write operation of the semiconductor memory device according to one embodiment of the present invention.

FIG. 5 is a timing chart schematically showing how a bit line potential changes in a semiconductor memory device according to an embodiment of the present invention.

FIG. 6 is a timing chart schematically showing how a clock signal and a bit line potential change in a semiconductor memory device according to an embodiment of the present invention.

FIG. 7 is a circuit diagram of a memory cell in a conventional semiconductor memory device having a DRAM with a reduced waiting time.

[Explanation of symbols]

 Reference Signs List 10A First sense amplifier circuit 10B Second sense amplifier circuit 20 2T1C cell (memory cell) 21 Storage node 22 First switch transistor 23 Second switch transistor 24 Storage capacitor 31 First memory cell array 32 Second Memory cell array 40 sense amplifier main body 41 first n-type transistor 42 second n-type transistor 43 first p-type transistor 44 second p-type transistor 50 precharge / equalize circuit 51 equalize transistor 52 first precharge Transistor 53 Second precharge transistor 60 Direct sense read amplifier 61 First n-type switch transistor 62 Second n-type switch transistor 63 Third n-type switch transistor 64 N-type switch transistor 70 write switch circuit 71 first n-type switch transistor 72 second n-type switch transistor 80 sense amplifier drive circuit 81 n-type switch transistor 82 inverter 83 p-type switch transistor BLa first bit line BLb 2 bit lines EQa first precharge signal EQb second precharge signal SEa first sense amplifier activation signal SEb second sense amplifier activation signal

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tsutomu Fujita 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Naoki Kuroda 1006 Odaka Kadoma, Kadoma City Osaka Pref. 72) Inventor Toshiro Yamada 1006 Kazuma Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. F-term (reference) 5B024 AA03 AA15 BA03 BA05 BA07 BA09 BA21 CA11 CA21

Claims (4)

[Claims] 1. A plurality of memory cells each comprising a first switch transistor and a second switch transistor having sources connected to each other, and a storage capacitor for data storage having one electrode connected to the source. A plurality of first bit lines each connected to the drain of the first switch transistor; and a plurality of first bit lines each connected to the drain of the second switch transistor and provided alternately with the first bit line. A plurality of second bit lines, a plurality of first sense amplifiers each connected to the plurality of first bit lines, and a plurality of first sense amplifiers each connected to the plurality of second bit lines A first precharge signal for performing a precharge for each of the plurality of first bit lines or a plurality of first sense amplifiers. A second precharge signal for precharging the plurality of second bit lines for each of the plurality of second bit lines while the first sense amplifier activating signal for activating the sense amplifier is held in an activated state; The second to activate the second sense amplifier
Wherein both of the sense amplifier activation signals are inactive. 2. The semiconductor memory according to claim 1, wherein the signal levels of the first precharge signal and the second sense amplifier activation signal change at one operation timing of the synchronization clock signal. apparatus. 3. The data stored in the storage capacitor is read out to the second bit line when both the second precharge signal and the second sense amplifier activation signal are in an inactive state. 2. The semiconductor memory device according to claim 1, wherein: 4. The data storage device according to claim 1, wherein the data stored in the storage capacitor is written when both the second precharge signal and the second sense amplifier activation signal are in an inactive state. 13. The semiconductor memory device according to claim 1.