JP2000216680A - Improved oversampling sigma delta modulator - Google Patents

Abstract

(57) Abstract: An oversampling sigma-delta modulator having a sampling frequency sufficiently higher than an input signal frequency is provided. The problem is solved by an improved architecture (uni-MASH using the concept of time division for architecture and circuit reuse) based on a recently developed MASH (multi-stage noise shaping) architecture. Oversampling sigma-delta modulators with a uni-MASH architecture use a single-stage time and capacitor integrator instead of the multi-stage integrator, digital-to-analog converter and quantizer used in the MASH architecture. Uni-MASH retains the advantages of MASH, such as excellent stability and high-order noise shaping ratio.

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital-analog (D / A conversion) and analog-digital conversion (A
/ D conversion), and more particularly to a multi-stage noise shaping (MASH) modulator.

2. Description of the Related Art With the advent of VLSI digital IC technology,
Digitizer that focuses on A / D conversion and D / A conversion
To perform many signal processing functions in
It was started. Conventional A / D conversion method and D / A conversion
It can avoid the various difficulties encountered in
And an oversaturator composed of relatively high tolerance analog components
Sampling sigma-delta converters have become popular in recent years.
This is shown in FIGS. 1 (a), 1 (b) and 1 (c).
A typical sigma-delta modulator has about
Move to the high frequency band, well outside the signal band.
Using oversampling and noise shaping techniques
I have. In this case, a low-pass filter and decimator
High frequency so that the SNR in the signal band increases significantly.
Noise can be easily filtered off. In addition, sigma-delta transformation
Modulator (SDM) can use incorrect analog circuitry
Thus, the time resolution can be exchanged for the amplitude resolution. high frequency
A / D converter by using numerical modulation and demodulation
Stairs with analog anti-aliasing pre-filter when inputting
Not only cut-off, but also analog output of D / A converter
Eliminates the need for a staircase cutoff
You can comb. In addition, the performance of SDM is analog
Influenced by non-ideal effects such as component matching or amplifier imperfections
Not. However, instability means that higher order SD
This is a serious problem for M. Oscillation of the feedback loop
High-order integration is not feasible, which limits high-order SDM
It is. In this case, the modulator has a large amplitude and low frequency,
Becomes unstable. To improve the stability of higher-order SDM
In US Pat. No. 4,704,600 (1987),
A three-stage MASH configuration has been proposed. FIG. 2 (a) and FIG.
As shown in (b), MASH always produces stable modulation.
High-order noise reduction without the problem of instability.
This is a promising architecture for obtaining form factors. MASH
Comprises several (primary) SDMs in cascade. Next
The input of the stage SDM is the quantization noise of the previous stage SDM.
The quantization noise of the middle stage SDM is then all digitally erased.
Is done. Therefore, the quantization noise from the last stage SDM
Only MASH remains and MASH is always stable. However
The MASH architecture still has some flaws.
You. For example, quantization noise cancellation is performed between each stage of MASH.
It is affected by the gain matching accuracy. Furthermore, in MASH,
More operational amplifiers and more than a typical architecture
The size of the MASH chip
The size increases. As shown in FIG.
The transfer function of a second order sigma-delta modulator is
Y = X + (1-Z^-1)^TwoQ (where Y is a digit
X is analog input, Q is quantization
Noise). According to the above transfer function, a typical sig
The resolution of the mar-delta modulator is mainly the order of the noise shaping function.
It is governed by the number and the oversampling ratio. Ma
The transfer function of a two-stage MASH as shown in FIG.
Is as follows: C₁= X + (1-Z^-1) Q₁ C_Two= -Q₁+ (1-Z^-1) Q_Two Y = C₁+ (1-Z^-1) C_Two= X + (1-Z^-1) Q₁−
(1-Z^-1) Q₁ + (1-Z^-1)^TwoQ_Two= X + (1-Z
^-1)^TwoQ_Two (Where C₁Is the first stage digital output, C_TwoIs the
Two-stage digital output, Q₁Is the first-stage quantization noise
And Q_TwoIs the second-stage quantization noise, and Y is
And X is an analog input signal).
According to the above transfer function, the two-stage MASH has a typical second order
Provide a second-order noise shaping factor as SDM. But
However, the characteristic that MASH is highly stable is that the primary SDM
Is the same as

SUMMARY OF THE INVENTION It is an object of the present invention to provide an oversampling sigma-delta modulator having a sampling frequency sufficiently higher than the input signal frequency.

The oversampling sigma-delta modulator of the present invention comprises N parallel integrators (where N is greater than one) which integrates the difference between the input terminal signal and the feedback signal. A quantizer for quantizing the output from each of the N integrators; means for converting the output from the quantizer to the feedback signal; and When quantizing the output from the (n-1) th integrator (where n is an integer of 2 to N) of the integrators,
Means for detecting an (n-1) th quantization error generated by the quantizer, wherein an output of a first one of the N integrators is quantized by the quantizer. When the first loop output signal is generated at the output terminal of the quantizer, the output of the n-th integrator among the N integrators is quantized by the quantizer. Generating a signal at the output terminal of the quantizer; selectively supplying an input signal as the input terminal signal to the first integrator, or providing the (n-1) th quantization error to the input terminal signal; A first switch for selectively supplying the first loop output signal to a delay circuit, or selectively supplying the n-th loop output signal to the first to (n). -1) the inverse of the product of the transfer function of the integrator A second switch for selectively supplying an n-th differentiator having a transfer function; an adding means for adding an output from the differentiator to the first loop output signal from the delay circuit; The (n-1) th quantization error is sequentially supplied to the first integrator and the nth integrator, and the first loop output signal and the nth loop output signal are sequentially supplied to the delay circuit and the nth integrator. Switch control means for controlling the first switch and the second switch so as to be supplied to a third differentiator. Preferably, the N integrators of the oversampling sigma-delta modulator of the present invention include an operational amplifier having a grounded non-inverting (+) terminal and an operational amplifier each having an inverting (-) terminal and an output terminal of the operational amplifier. N capacitors connected in parallel via a switch circuit between the first integrator and n capacitors.
A capacitor controlled by a switch control circuit such that a first or nth capacitor is connected between the inverting terminal and the output terminal of the operational amplifier when operating the integrator. And a capacitor multiplexing switching capacitor integrator comprising: The means for detecting the (n-1) th quantization error of the oversampling sigma-delta modulator of the present invention comprises: the output from the (n-1) th integrator and the output from the quantizer. And an adding means for providing a difference between the output and the (n-1) th quantization error.
The means for converting the output from the quantizer of the oversampling sigma-delta modulator of the present invention to the feedback signal preferably has a digital-to-analog conversion function for converting a digital input signal to an analog signal. .

DESCRIPTION OF THE PREFERRED EMBODIMENTS A conventional MASH shown in FIG.
A careful examination of the architecture shows that the first stage structure and the second stage structure are substantially the same. The difference between these two stages is as follows: the first stage input is the analog input signal X (z), while the second stage input is the quantization error from the first stage- Q1 (z). Furthermore, the output of the second stage must pass through a digital differentiator before being added to the output of the first stage,
No first stage output is required. Therefore, in the present invention, the existing MASH architecture is improved using the concept of time division, and this new architecture is referred to as Uni-MASH. Our main idea is to reuse the architecture and circuitry at different stages of the MASH. MA
Due to the similarity of the different stages of SH, we have found that the conventional M
In order to reduce unnecessary circuits in the ASH architecture, a uni-MASH architecture as shown in FIG. 3 is proposed. The operating principle of the Uni-MASH architecture
This will be described below. First, switch sw1 determines what the input to the modulator is (X (z) or -Q
₁ (z)). If X (z) is an input, switch sw2 selects integrator int1. Otherwise, select integrator int2. Finally, switch sw
3 determines whether a differentiator 10 is needed. FIG.
FIGS. 4A and 4B are diagrams focusing on the data path of the uni-MASH modulator shown in FIG. 3 corresponding to the first-stage or second-stage operation of the two-stage MASH. In FIG. 4A and FIG. 4B, useless data paths corresponding to desired stages are indicated by thin lines. Because the concept of time division is used in the architecture of the present invention, additional delay circuits must be added to the signal circuits for latency. FIG. 4 (a)
In the first stage operation as shown in FIG. 7, the integrator int1 integrates the difference between the input X (z) and the feedback signal, and
The output of the first stage generated at the output terminal of
To be added to the output from the differentiator 10 in the second stage operation. The feedback signal is a conventional MASH
It is obtained in the same manner as the modulator, and by converting the output of the quantizer 30 into an analog signal via a digital-analog converter 40 (1-bit DAC). FIG.
In the second stage operation as shown in (b), the integrator int2
Integrates the difference between the first-stage quantization error (first quantization error) and the feedback signal, and supplies the second-stage output generated at the output terminal of the quantizer 30 to the differentiator 10. . The first quantization error is a difference between the output from the integrator int1 and the output from the quantizer 30 in the first stage operation, and is stored in the delay circuit 20 until the first stage operation is completed. FIG. 4 (a)
4 (b), the quantizer 30 and the digital-to-analog converter 40 are common elements for the first-stage operation and the second-stage operation. The transfer function of the two-stage MASH architecture implemented by the uni-MASH architecture shown in FIG. 3 is as follows: C ₁ = X + (1-Z ⁻¹ ) Q ₁ C ₂ = −Q ₁ Z ^−1/2 + (1-Z ^-1 ) Q ₂ Y = Z ^-1/2 C ₁ + (1-Z ^-1 ) C ₂ = X + (1-Z ^-1 ) Z ^-1/2 Q _1- (1-Z ^-1 ) Z ^-1/2 Q ₂ + (1-Z ^-1 ) ² Q ₂ = XZ ^-1/2 + (1-Z ^-1 ) ² Q ₂ (where C ₁ is the first stage digital output and C ₂ is the second stage digital output) Output, Q ₁ is first stage quantization noise, Q ₂ is second stage quantization noise, Y is a digital output signal, and X is an analog input signal).
Except for the delayed input signal in Uni-MASH,
All properties of the transfer function between SH and MASH are identical. Further, the MAS shown in FIGS. 5 (a) and 5 (b)
According to the pseudo power spectra of the H and Uni MASH modulators, both have the same output S corresponding to 16 bit resolution.
NR (106 dB) and the same dynamic range (10
6 dB). Here, the input signal is a 1 kHz sine wave signal, the sampling frequency is 128 kHz, and the oversampling ratio is 64. Clearly, Uni-MASH has the same performance as MASH. However, as can be easily understood from FIGS. 7 (a) and 7 (b), the number of operational amplifiers and capacitors required in Uni-MASH is greatly reduced. Although two parallel integrators are shown in FIG. 3, one amplifier is sufficient to implement these two (or more) integrators. FIG. 6 shows that the two parallel integrators are implemented by time and capacitor multiplexing switched capacitor integrators. In these two (or more) parallel integrator circuit configurations, the switch frequency must be doubled (or more) in the time division architecture of the present invention. Connect the capacitor Cs to the input signal (voltage) V
When charging up to i, the capacitors Ci1 and Ci2 are all discharged. On the other hand, when the voltage of Cs is applied to the operational amplifier, Ci1 or Ci2 forms a feedback path and performs integration, and accordingly, the integrator is switched by the switch sw2 in the uni-MASH modulator shown in FIG. Selected. In the execution of the VLSI shown in FIG.
The MASH architecture must be able to tolerate finite gain in operational amplifiers and capacitor ratio mismatch in analog circuits. Gain mismatch between different stages in a MASH modulator results in degradation of the output SNR. Typically, the gain mismatch is determined by the accuracy of the capacitor ratio that determines the scaling factor between the input analog signal and the feedback signal from the DAC. We define the gain of each primary SDM as the ratio between its digital output and analog input. As shown in FIG. 2B, C ₁ and C ₂ are ideal outputs in an ideal first-order SDM (gain 1). αC
₁ and βC ₂ are the digital outputs in the non-ideal first-order SDM (gain ≠ 1). Therefore, the transfer function of a two-stage MASH is: Y = αC ₁ + β (1-Z ⁻¹ ) C ₂ = αX + (α−β) (1-Z ⁻¹ ) Q ₁ + β (1- Z ^-1 ) ² Q ₂ , where Q ₁ is the first stage quantization noise, Q ₂ is the second stage quantization noise, Y is the digital output, and X
Is the analog input, C ₁ is the ideal first stage output, C ₂ is the ideal second stage output, α is the actual first stage output gain, and β is the actual second stage output. Gain).
Obviously, the first stage quantization error is not actually strictly canceled, and the output performance is degraded. However, FIG.
As shown in FIG. 5, uni-MASH uses the same primary SDM circuit for both the first and second stage operation of MASH. Therefore, the effect of gain mismatch is reduced. Specifically, Uni-MASH has a first stage SDM and a second stage SDM.
Share the same sampling capacitor C _s and the feedback capacitor C _d in both. Therefore, even gain mismatch effects caused by different sampling capacitor C _s and the feedback capacitor Cd in MASH, Uni MAS
H removes it. Finally, different operational amplifiers are used to synthesize integrators at different stages of a conventional MASH (FIG. 7 (a)). Due to the concept of architecture reuse and the circuit shown in FIG. 6, only one operational amplifier is required in the integrator of the Uni-MASH (FIG. 7 (b)). Thus, the mismatch effect resulting from using different operational amplifiers for different integrators in MASH is a
Not present in SH. The only mismatch effect left is from the integrating capacitor in the integrator. Further, since the circuit is reused, the uni-MASH of the present invention is used.
The size of the chip shown in FIG. 7B is reduced. In a uni-MASH modulator for a D / A converter, an integrator and a feedback circuit can be easily provided as a MASH by a switch capacitor method. Two-stage Uni MA suitable for MOSVLSI technology
The SH architecture, as shown in FIG. 7 (b), comprises only one 1-bit comparator, a time and capacitor multiplexing switching capacitor integrator, a digital differentiator, and additional delay elements. Input signals to the first stage or second stage is sampled by the capacitor C _s, it is sequentially accumulated in the C _i1 or C _i2. The first-stage or second-stage quantized 1-bit signal is supplied with a reference voltage by a feedback capacitor C.
It is fed back to the input by charging _d . The comparator and the analog switch are shown in FIG.
Is controlled by the sequence clock shown in FIG. The clock timing is divided into four stages per cycle in the uni-MASH: bar φ ₁ → φ ₁ → bar φ ₂ →
φ ₂ → bar φ ₁ . In the first quarter cycle, the analog input signal is sampled by C _s and the previous second stage quantized output is integrated into C _i2 by feedback capacitor C _d . In the second quarter cycle, the first-stage input signal sampled by C _s is integrated into C _i1 . C
The charge accumulation in _i1 ends, and the comparator calculates
The integrator output value and the GND level are compared at the same time. next,
The feedback capacitor C _d, depending on whether the high or low quantizer is precharged to the positive or negative full scale charge. In the third quarter cycle, the integrator uses C _d
Accumulates the first-stage quantized output signal from the comparator to _Ci1 . Next, the output of the integrator at this point is sampled by Cs and input to the second stage operation. This quarter
The value of the integrating capacitor C _{i1 in} the cycle is MASH
It is equal to the difference between the integrator output and the quantizer output of the first stage operation (FIG. 2 (b)). In the fourth quarter cycle, the integrator converts the second stage input signal to the integrating capacitor C _i2
, And then precharges the feedback capacitor _Cd to a reference voltage associated with the second stage quantized signal to provide the output of the second stage feedback D / A converter.

As described above, according to the present invention,
An improved architecture (Uni-MASH with the concept of time division for architecture and circuit reuse) based on the recently developed MASH (Multi-Stage Noise Shaping) architecture is provided. That is, an oversampling sigma-delta modulator having a sampling frequency sufficiently higher than the input signal frequency is provided. Advantageously, the oversampling sigma-delta modulator of the present invention retains the advantages of MASH, including excellent stability and high order noise shaping ratio.

[Brief description of the drawings]

FIG. 1 (a) is a block diagram illustrating the architecture of a typical primary sigma-delta modulator for an analog-to-digital converter. (B) is a block diagram illustrating the architecture of a typical second-order sigma-delta modulator for an analog-to-digital converter. (C) A block diagram illustrating the architecture of a typical higher order sigma-delta modulator for an analog-to-digital converter.

FIG. 2 (a) is an architecture of a cascaded sigma-delta modulator for analog-to-digital conversion, comprising a three-stage MAS;
It is a block diagram which shows H. (B) is a block diagram showing the architecture of a cascaded sigma-delta modulator for analog-digital conversion, showing a two-stage MASH.

FIG. 3 is a block diagram showing the architecture of a two-stage uni-MASH modulator for analog-digital conversion configured according to a preferred embodiment of the present invention.

FIG. 4A is a block diagram showing an operation of a first stage of the two-stage uni-MASH modulator shown in FIG. 3; FIG. 4B is a block diagram showing the operation of the second stage of the two-stage uni-MASH modulator shown in FIG. 3.

FIG. 5 (a) is a pseudo power spectrum of a modulator with the MASH architecture shown in FIG. 2 (b) by ignoring the problem of gain mismatch between the two stages (input signal 1 kHz sine signal, Sampling frequency 128kHz
z, oversampling ratio 64). (B) A pseudo power spectrum of the modulator with the uni-MASH architecture shown in FIG. 3 by ignoring the problem of gain mismatch between the two stages (input signal 1 kHz
Sine signal, sampling frequency 128 kHz, oversampling ratio 64).

FIG. 6 is a circuit diagram of a time and capacitor multiplexing switching capacitor integrator realizing two parallel integrators int1 and int2 of the uni-MASH in FIG. 3;

7A is a diagram showing a circuit configuration of the conventional MASH modulator shown in FIG. 2B together with its clock timing. FIG. 4B is a diagram showing a circuit configuration of the modulator shown in FIG. 3 together with its clock timing.

[Explanation of symbols]

 C capacitor X analog input Y digital output Q quantization noise V voltage sw switch int integrator 10 differentiator 20, 50 delay circuit 30 quantizer 40 digital-analog converter

Claims (4)

[Claims] An integrator in parallel for integrating the difference between the input terminal signal and the feedback signal, wherein N is an integer greater than or equal to 2; and a signal from each of the N integrators. A quantizer for quantizing an output; means for converting an output from the quantizer into the feedback signal; wherein the quantizer is an (n-1) th integrator of the N integrators (Where n is an integer of 2 to N) means for detecting the (n-1) th quantization error generated by the quantizer when quantizing an output from the N integrals. When the output of the first integrator among the integrators is quantized by the quantizer, a first loop output signal is generated at the output terminal of the quantizer, and the n-th integrator of the N integrators is generated. When the output of the integrator is quantized by the quantizer, the n-th loop output signal is The input signal is selectively supplied to the first integrator as the input terminal signal, or the (n-1) th quantization error is input to the n-th integrator as the input terminal signal. A first switch for selectively supplying the first loop output signal to a delay circuit, or supplying the n-th loop output signal to the first to (n-1) -th integrators. And a second switch for selectively supplying an n-th differentiator having a transfer function of a reciprocal of a product of the transfer function of the second transfer function; and an adder for adding an output from the differentiator to the first loop output signal from the delay circuit. Means; the input signal and the (n-1) th quantization error are sequentially supplied to the first integrator and the nth integrator, and the first loop output signal and the nth loop output signal are provided. Are sequentially the delay circuit and the nth Oversampling having a sampling frequency sufficiently higher than the input sigma frequency, comprising: switch control means for controlling the first switch and the second switch so as to be supplied to a divider. converter. 2. The N integrators according to claim 1, further comprising an operational amplifier having a grounded non-inverted (+) terminal and a parallel connected via a switch circuit between each of the inverting (-) terminals and the output terminal of the operational amplifier. N capacitors connected to the inverting terminal of the operational amplifier when the switch circuit operates the first integrator or the n-th integrator. And a capacitor multiplexed switching capacitor integrator comprising a capacitor controlled by a switch control circuit to be connected between the output terminal and the output terminal. Oversampling converter. 3. The method according to claim 2, wherein said means for detecting an (n-1) th quantization error comprises a difference between said output from said (n-1) th integrator and said output from said quantizer. To (n-
2. The oversampling converter according to claim 1, further comprising: 1) adding means for providing as a first quantization error. 4. The means for converting an output from the quantizer into the feedback signal has a digital-analog conversion function for converting a digital input signal into an analog signal.
The oversampling converter according to claim 1.