JP2000216396A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: A first object of the present invention is to provide a technique for manufacturing a crystalline TFT having a structure in which a gate electrode and an LDD region overlap with each other by a simpler method than a conventional technique. It is intended to be. SOLUTION: An n-channel TFT has a structure in which an LDD region overlaps with a gate electrode. Therefore, a gate electrode is formed from a first conductive layer and a second conductive layer,
After the formation of the conductive layer, a first impurity element imparting n-type conductivity is added to form a first impurity region to be an LDD region, and after the second conductive layer is formed, a second n-type impurity region is formed. And a second impurity region serving as a source region and a drain region is formed. Thus, a structure in which the LDD region overlaps with the gate electrode is realized. Furthermore, LD that does not overlap with the gate electrode
In order to provide the D region, a part of the second conductive layer may be removed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit composed of thin film transistors on a substrate having an insulating surface and a method for manufacturing the same. For example, the present invention relates to a configuration of an electro-optical device typified by a liquid crystal display device and an electronic apparatus equipped with the electro-optical device. Note that, in this specification, a semiconductor device generally means a device that functions by utilizing semiconductor characteristics, and includes the above-described electro-optical device and an electronic device equipped with the electro-optical device.

[0002]

2. Description of the Related Art Thin film transistors (hereinafter referred to as TFTs) can be manufactured on a transparent glass substrate.
Application development to active matrix type liquid crystal display devices has been actively promoted. A TFT in which a semiconductor film having a crystalline structure is used as an active layer (hereinafter, referred to as a crystalline TFT) has high mobility, so that a high-definition image display can be realized by integrating functional circuits on the same substrate. It is now possible.

[0003] In the specification of the present application, the semiconductor film having a crystal structure includes a single crystal semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor, and further includes JP-A-7-130652, JP-A-8-78329, JP-A-10-135
468 and Japanese Patent Application Laid-Open No. 10-135469.

In order to construct an active matrix type liquid crystal display device, 100 to 100 pixel matrix circuits alone are required.
Two million crystalline TFTs were required, and when a peripheral functional circuit was added, more crystalline TFTs were required. In order to operate the liquid crystal display device stably, it is necessary to ensure the reliability of each crystalline TF.

The characteristics of a field-effect transistor such as a TFT include a linear region in which the drain current and the drain voltage increase in proportion, a saturation region in which the drain current is saturated even if the drain voltage increases, and a characteristic in which the drain voltage is applied. Ideally, it can be divided into a cut-off region where no current flows. In this specification, the linear region and the saturation region are called an on region of the TFT, and the cutoff region is called an off region. For convenience, the drain current in the ON region is called an ON current, and the current in the OFF region is called an OFF current.

A pixel matrix circuit of an active matrix type liquid crystal display device is composed of an n-channel type TFT (hereinafter, referred to as a pixel TFT) and has an amplitude of 15 to 20.
Since a gate voltage of about V is applied, it is necessary to satisfy the characteristics of both the ON region and the OFF region. On the other hand, peripheral circuits provided for driving the pixel matrix circuit are configured based on CMOS circuits, and the characteristics of the ON region are important mainly. However, the crystalline TFT has a problem that the off-current tends to increase. Also, crystalline TF
When T was driven for a long period of time, deterioration phenomena such as a decrease in mobility and on-current and an increase in off-current were often observed. One of the causes was considered to be a hot carrier injection phenomenon caused by a high electric field near the drain.

In the technical field of LSI, as a method of lowering the off-state current of a MOS transistor and alleviating a high electric field near the drain, a lightly doped drain (LDD) is used.
opedDrain) structures are known. In this structure, a low-concentration impurity region is provided between a drain region and a channel formation region, and this low-concentration impurity region is called an LDD region.

[0008] Similarly, it has been known that a crystalline TFT also forms an LDD structure. According to the conventional technique, the gate electrode is used as a mask to perform L
A low-concentration impurity region serving as a DD region is formed in advance, and then sidewalls are formed on both sides of the gate electrode using anisotropic etching technology, and the second impurity element is formed using the gate electrode and the sidewall as a mask. This is a method of forming a high-concentration impurity region to be a source region and a drain region by an adding step.

However, the LDD structure is a TFT having a normal structure.
Compared with this, even if the off current can be reduced, the series resistance component increases structurally, and as a result, there is a disadvantage that the on current of the TFT is also reduced. Further, deterioration of the on-state current could not be completely prevented. As a method for compensating for this drawback, a structure is known in which the LDD region overlaps with the gate electrode via a gate insulating film. There are several ways to form this structure, for example,
GOLD (Gate-drain Overlapped LDD), LAT
Also known as ID (Large-tilt-angle implanted drain). With such a structure, a high electric field near the drain was relaxed to increase hot carrier resistance, and at the same time, a decrease in on-current could be prevented.

[0010] Also, in a crystalline TFT, the hot carrier resistance is improved by providing an LDD structure as compared with a crystalline TFT having a simple configuration formed only of a source region, a drain region, and a channel region.
It has been confirmed that the adoption of a structure can achieve extremely excellent effects ("A Novel Self-aligned Gate-over
lapped LDD Poly-Si TFT with High Reliability
and Performance ", Mutsuko Hatano, Hajime Akimot
o and Takeshi Sakai, IEDM97-523).

[0011]

In a crystalline TFT, forming an LDD structure to suppress the hot carrier injection phenomenon is an effective means.
With such a structure, it is possible to prevent a decrease in on-state current seen in the LDD structure. Good results have also been obtained in terms of reliability.

As described above, in order to achieve high reliability in a crystalline TFT, it is necessary to study the structure of the device. Therefore, it is desirable to form a GOLD structure. However, in the conventional method, the LDD is self-aligned.
Although a region can be formed, the step of forming a sidewall film by anisotropic etching is not suitable for processing a large-area glass substrate such as a liquid crystal display device.
Further, since the length of the LDD region is determined by the width of the sidewall, the degree of freedom in element design is extremely limited.

[0013] A first object of the present invention is to provide a technique for overcoming such a problem. In this technique, a gate electrode and an LDD region are overlapped by a simpler method than the conventional technique. It is an object of the present invention to provide a technique for manufacturing a crystalline TFT having a structure.

Although the GOLD structure can prevent the deterioration of the ON current, the OFF current increases when a high gate voltage is applied in the OFF region as in the case of an n-channel TFT forming a pixel matrix circuit. In some cases.
When the off-state current increases in the pixel TFT of the pixel matrix circuit, power consumption increases, and an inconvenience such as an abnormality in image display occurs. This is considered to be because the inversion layer is formed in the LDD region formed so as to overlap with the gate electrode in the off region, thereby creating a hole passage. In such a case, the operating range of the TFT is narrow and limited.

A second object of the present invention is to provide a gate electrode and an L
Crystalline TFT with structure overlapping DD region
In, so that the operating range can be expanded,
A second object is to provide a structure for preventing an increase in off-state current and a manufacturing method thereof.

[0016]

FIG. 17 shows the structure of a TFT and the Vg− obtained at that time based on the knowledge obtained so far.
5 is a diagram schematically showing Id (gate voltage-drain current) characteristics. FIG. 17A-1 shows the simplest structure of a TFT in which a semiconductor layer includes a channel formation region, a source region, and a drain region. FIG. 13B shows the characteristics of this TFT, where the + Vg side is the ON region of the TFT,
The Vg side is an off region. The solid line shows the initial characteristics, and the broken line shows the characteristics of deterioration due to the hot carrier injection phenomenon. In this structure, both the ON current and the OFF current are high and the deterioration is large. Therefore, for example, the TFT cannot be used as it is for a pixel TFT of a pixel matrix circuit.

FIG. 17 (A-2) shows that (D-1)
A structure in which a low concentration impurity region serving as a region is provided,
An LDD structure that does not overlap with the gate electrode.
FIG. 11B shows the characteristics of the TFT, in which the off-state current can be suppressed to some extent, but the deterioration of the on-state current cannot be prevented. FIG. 17 (A-3) shows the LD.
The D region completely overlaps with the gate electrode, and is also called a GOLD structure. FIG.
3) is a characteristic corresponding to this, and the deterioration can be suppressed to a level where there is no problem, but the off-state current is higher on the -Vg side than in the structure of (A-2).

On the other hand, the structure shown in FIG. 17A-4 is a structure that can prevent deterioration and increase the off current as shown in FIG. 17B-4. This is one in which the LDD region is divided into two regions, a region that overlaps with the gate electrode and a region that does not overlap. The LDD region that overlaps with the gate electrode suppresses the hot carrier injection phenomenon, and This has an effect of preventing an increase in off-current in an LDD region which does not overlap with the gate electrode.

According to the present invention, in order to realize a TFT having a structure as shown in FIG.
The channel type TFT has a structure in which the LDD region overlaps with the gate electrode. For that purpose, a gate electrode is formed from a first conductive layer and a second conductive layer, and after forming the first conductive layer, a first impurity element imparting n-type conductivity is added to the gate electrode.
After forming a first impurity region serving as a DD region and forming a second conductive layer, a second step of adding an impurity element imparting n-type conductivity is performed, and a second step serving as a source region and a drain region is performed. It forms an impurity region. Thus, a structure in which the LDD region overlaps with the gate electrode is realized.
Further, in order to provide an LDD region which does not overlap with the gate electrode, part of the second conductive layer may be removed.

On the other hand, in a p-channel TFT, a gate electrode is similarly formed from a first conductive layer and a second conductive layer.
A part of a third impurity region serving as a source region and a drain region overlaps with a gate electrode.

The first conductive layer is made of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (M
o) One or more elements selected from the above, or a material containing the elements as components. In the structure, at least a conductive layer (A) made of the above material and formed in contact with the gate insulating film, and one or more kinds selected from aluminum (Al) and copper (Cu) on the conductive layer (A) It is a preferred embodiment to form the conductive layer (B) made of the element or a material containing the element as a component.

The second conductive layer is made of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo).
It is formed of one or more elements selected from the group consisting of, or an alloy material containing the elements as components.

In the configuration of the pixel matrix circuit, the pixel matrix circuit is provided in contact with the second impurity region of the pixel TFT,
A storage capacitor is formed from a semiconductor layer containing an impurity element at the same concentration as the first impurity region, an insulating layer formed using the same layer as the gate insulating film, and a capacitor wiring formed over the insulating layer. Alternatively, a semiconductor layer provided in contact with the second impurity region of the pixel TFT and containing an impurity element at the same concentration as the third impurity region, an insulating layer formed of the same layer as the gate insulating film, A storage capacitor is formed from the capacitor wiring formed on the layer.

[0024]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIG. The substrate 301 is a substrate having an insulating surface. For example, a glass substrate provided with a silicon oxide film, a stainless steel substrate, a plastic substrate,
A ceramic substrate or a silicon substrate can be used. Alternatively, a quartz substrate may be used.

The semiconductor layer formed on the substrate 301 is obtained by crystallizing an amorphous semiconductor film formed by a film forming method such as a plasma CVD method, a low pressure CVD method, or a sputtering method by a laser annealing method or a thermal annealing method. It is desirable to form it with a crystalline semiconductor film. Alternatively, a microcrystalline semiconductor formed by the above film formation method can be used. The semiconductor material applicable here is silicon, germanium, silicon-germanium alloy, silicon carbide, and a compound semiconductor material such as gallium arsenide can also be used.

Alternatively, the semiconductor layer formed on the substrate 301 is an SOI (Silicon On Silicon) having a single crystal silicon layer formed thereon.
Insulators) It may be a substrate. Several types of SOI substrates are known depending on the structure and manufacturing method. Typically, SIMOX (Separation by Implan) is used.
ted Oxygen), ELTRAN (Epitaxial Layer Tra)
nsfer: a registered trademark of Canon Inc.), Smart-Cut (SOIT
(Registered trademark of EC company) can be used. Of course,
Other SOI substrates can be used.

FIG. 28 shows a cross-sectional structure of an n-channel type TFT and a p-channel type TFT formed on a substrate 301. The gate electrodes of the n-channel TFT and the p-channel TFT include a first conductive layer and a second conductive layer. The first conductive layer includes conductive layers (A) 313 and 316 provided in contact with the gate insulating film 312 and the conductive layer (A).
Conductive layer (B) 31 provided in contact with 313 and 316
4, 317. And the second conductive layer 3
15, 318 are conductive layers (A) 313 of the first conductive layer,
316, the first conductive layers (B) 314 and 317, and the gate insulating film 312.

The conductive layer (A) 31 constituting the first conductive layer
Reference numerals 3 and 316 are formed from elements such as titanium (Ti), tantalum (Ta), molybdenum (Mo), and tungsten (W), or materials containing these elements. The conductive layers (B) 314 and 317 are made of aluminum (A) having a low resistivity.
l) or copper (Cu) may be used. Here, the conductive layer (B)
Is a substrate having a large area such as a liquid crystal display.
Considering the formation of the FT, it is provided for the purpose of reducing the resistance of the gate electrode and the gate wiring.
Therefore, depending on the application, the first conductive layer may be formed of the conductive layer (A).
Alternatively, another conductive layer may be further laminated on the conductive layer (B).

The second conductive layers 315 and 318 are formed so as to be in contact with the first conductive layer and extend from above the first conductive layer onto the gate insulating film 312. As shown in FIG. 31, assuming that the lengths of the first conductive layer and the second conductive layer in the channel length direction are L1 and L2, respectively, the relationship of L1 <L2 only needs to be maintained, and the present invention is implemented. The length may be set appropriately. However, as described below, the first conductive layer and the second conductive layer function as a mask for forming a source region, a drain region, and an LDD region by adding an impurity to a semiconductor layer in a TFT manufacturing process. Therefore, it is necessary to determine the values of L1 and L2 in consideration of this point.

The semiconductor layer of the n-channel TFT includes a channel formation region 302, first impurity regions 303 and 304 provided in contact with both sides of the channel formation region, and a source region provided in contact with the first impurity region 303. 305,
Drain region 3 provided in contact with first impurity region 304
06. First impurity regions 303 and 30
4 is the second conductive layer 31 via the gate insulating film 312
5 is provided so as to overlap with a region in contact with the gate insulating film.

Channels of first impurity regions 303 and 304
The length in the length direction is 0.5 to 3 μm, typically 1.5
μm in length and the concentration of the impurity element imparting n-type is
1 × 10¹⁶~ 5 × 10¹⁹atoms / cm^Three, Typically 1 × 1
0¹⁷~ 5 × 10¹⁸atoms / cm^ThreeIt is. Also, the source area
The impurity concentration of 305 and the drain region 306 is 1 × 10
²⁰~ 1 × 10^{twenty one}atoms / cm^Three, Typically 1 × 10²⁰~ 5
× 10²⁰atoms / cm^ThreeAnd

The channel formation region 302 may be doped with boron at a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ in advance. This boron is added to control the threshold voltage, and another element can be used as long as the same effect can be obtained.

On the other hand, the first impurity regions 308 and 309, the source region 310 and the drain region 311 of the p-channel TFT are doped with an impurity element imparting p-type at the same concentration. Then, the source region 3 of the n-channel TFT
05 and the impurity concentration added to the drain region 306.
An impurity element imparting p-type is added at a concentration of 5 to 3 times.

As described above, according to the present invention, in a TFT structure, a gate electrode is formed on a first conductive layer and a second conductive layer is formed on the first conductive layer.
28, the first conductive layer located between the gate insulating film and the second conductive layer has an end portion closer to the end of the second conductive layer as shown in FIG. Is also formed inside. The structure is characterized in that the first impurity region provided in the semiconductor layer and the second conductive layer are provided so as to overlap with each other.

The TFT shown in FIG. 28 is particularly an n-channel TFT in which first low-concentration impurity regions 303 and 304 functioning as so-called LDD regions are provided so as to overlap with a gate electrode via a gate insulating film. Therefore, the GOLD structure of the MOS transistor and the LAT
Advantages such as an ID structure can be obtained.

On the other hand, a p-channel type TFT has such an LD.
It is assumed that a low-concentration impurity region having a D structure is not provided.
Of course, a structure in which a low concentration impurity region is provided may be used.
Since a p-channel TFT is inherently highly reliable, it is preferable to increase the on-current and balance the characteristics with the n-channel TFT. As shown in FIG.
When applied to an OS circuit, it is particularly important to balance these characteristics. However, there is no problem even if the structure of the present invention is applied to a p-channel TFT.

When the n-channel type TFT and the p-channel type TFT are completed in this way, they are covered with a first interlayer insulating film 319, and the source regions 305, 311 and the drain region 30 are formed.
Source electrodes 320 and 322 and a drain electrode 321 that are in contact with the first and second electrodes 6 and 310 are provided. In the structure of FIG. 28, a silicon nitride film is provided as a passivation film 323 after these are provided. Further, a second interlayer insulating film 324 made of a resin material is provided. The second interlayer insulating film does not need to be limited to a resin material. For example, when applied to a liquid crystal display device, it is preferable to use a resin material in order to ensure surface flatness.

FIG. 28 shows an example of a CMOS circuit in which an n-channel TFT and a p-channel TFT are complementarily combined.
The present invention can be applied to an OS circuit and a pixel matrix circuit of a liquid crystal display device.

[Embodiment 2] An embodiment of the present invention will be described with reference to FIG. The substrate 101 has an insulating surface. For example, in addition to a glass substrate and a plastic substrate, a stainless substrate, a ceramic substrate, or a silicon substrate provided with an insulating film on a surface can be used. Alternatively, a quartz substrate may be used.

The base film 102 is formed on the surface of the substrate 101 where the TFT is to be formed. Base film 10
Reference numeral 2 denotes a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like, which is provided to prevent impurities from diffusing from the substrate 101 into the semiconductor layer.

The semiconductor layer formed on the base film 102 is formed by transforming an amorphous semiconductor film formed by a film forming method such as a plasma CVD method, a low pressure CVD method, or a sputtering method into a solid phase by a laser crystallization method or a heat treatment. It is preferable to form a crystalline semiconductor crystallized by a growth method. Further, a microcrystalline semiconductor formed by the above film formation method can be used. Semiconductor materials applicable here are silicon, germanium,
Further, it is a silicon germanium alloy or a silicon carbide alloy. In addition, a compound semiconductor material such as gallium arsenide can be used. In addition, as in the first embodiment, the SOI
A substrate may be used.

FIG. 1 shows a cross-sectional structure of an n-channel TFT and a p-channel TFT. n-channel type TF
The gate electrodes of the T and p channel type TFTs are composed of a first conductive layer and a second conductive layer. The first conductive layer has a three-layer structure, and includes conductive layers (A) 111 and 115 provided in contact with the gate insulating film 103 and conductive layers (B) 112 and 116 stacked thereover. , Conductive layer (C)
113 and 117. The second conductive layers 114 and 118 are provided in contact with the first conductive layer and the gate insulating film 103.

The conductive layer (A) 11 constituting the first conductive layer
Reference numerals 1 and 115 are formed from elements such as Ti, Ta, Mo, and W, or alloy materials containing these elements as main components. Alternatively, a nitride, an oxide, or a silicide of these elements may be used. It is preferable that the conductive layers (B) 112 and 116 be made of Al or Cu having low resistivity. The conductive layers (C) 113 and 117 are made of Ti, T like the conductive layer (A).
It is formed of an element such as a, Mo, W, or an alloy material containing these elements as main components. Here, the conductive layer (B) is formed for the purpose of reducing the resistance of the gate electrode and the gate wiring connected to the gate electrode in consideration of forming the TFT of the present invention on a large-area substrate such as a liquid crystal display device. It is provided. Depending on the application, the first conductive layer may be formed only of the conductive layer (A), or three or more layers may be stacked.

The second conductive layers 114 and 118 correspond to the first conductive layers 114 and 118.
And is provided in contact with the gate insulating film 103. Here, as shown in FIG. 16, the second conductive layer is initially L in the channel length direction.
3 lengths, and then L5
And finally to L2 length. Therefore, assuming that the first conductive layer is L1, the length of the second conductive layer extending to the gate insulating film can be represented by L4.

Here, in the present invention, the length L1 of the first conductive layer is 0.2 to 10 μm, preferably 0.4 to 5 μm.
μm, and the length L2 of the second conductive layer is 1.2 to 16 μm, preferably 2.2 to 11 μm. Here, the length L5 for removing the second conductive layer is equal to 0.
The thickness is 5 to 3 μm, preferably 1.0 to 2.0 μm.

The first conductive layer and the second conductive layer function as masks in a first step of adding an impurity element of one conductivity type and in a second step of adding an impurity element of one conductivity type. Yes, L1 and L3, and L
It is necessary to determine the length of 2 and L5. n-channel type TF
The length of the LDD region of T is formed by the difference between L3 and L1. Then, the second conductive layer is previously set to L3
Is formed, and then L is formed by an etching process.
In order to obtain the configuration of the present invention, the first impurity region 1605 serving as an LDD region is connected to the second conductive layer via the gate insulating film in order to obtain the configuration of the present invention. This is because the overlapping area is provided with a length of L4 and the non-overlapping area is provided with a length of L5.

In FIG. 1, the semiconductor layer of the n-channel TFT includes a channel formation region 104 and first impurity regions 105 provided on both sides of the channel formation region.
And second impurity regions 106 and 107 provided in contact with the first impurity region 105.
The second impurity region 106 functions as a source region, and the second impurity region 107 functions as a drain region. The first impurity region 105 is provided over the region where the second conductive layer 114 is in contact with the gate insulating film with the gate insulating film 103 interposed therebetween.

The length of first impurity region 105 corresponding to L6 in FIG. 16 is 1.0 to 6 μm, preferably 2.0 to 6 μm.
It has a length of 4 μm (for example, 3 μm), and the concentration of the impurity element imparting n-type is 1 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm.
³ , typically 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ . The length L5 at which the first impurity region does not overlap with the second conductive layer is 0.5 to 3 μm, preferably 1.0 to 2 μm as described above. Also, the source region 10
5 and the impurity concentration of the drain region 106 are 1 × 10 ²⁰ to
1 × 10 ²¹ atoms / cm ³ , typically 2 × 10 ^{20 to} 5 × 1
It may be set to 0 ²⁰ atoms / cm ³ .

At this time, boron may be previously added to the channel forming region 104 at a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ . This boron is added to control the threshold voltage, and other elements can be used as long as the same effect can be obtained.

On the other hand, the third impurity regions 109, 110, 130 and 131 of the p-channel TFT form a source region and a drain region. The third impurity regions 130 and 131 contain an impurity element imparting n-type at the same concentration as the source region 106 and the drain region 107 of the n-channel TFT.
At three times the concentration, an impurity element imparting p-type is added.

As described above, the TFT of the present invention has a structure in which the gate electrode is provided with the first conductive layer and the second conductive layer. As shown in FIG. , Are provided in contact with the first conductive layer and the gate insulating film. In at least the n-channel TFT, a feature is that a part of the first impurity region is provided so as to overlap with a region of the second conductive layer which is in contact with the gate insulating film.

In the structure shown in FIG. 1, a first impurity region serving as an LDD region is formed using the first conductive layer as a mask, and a first impurity region serving as a source region and a drain region is used using the second conductive layer as a mask. After the second impurity region is formed, the second conductive layer is recessed by etching. Therefore, as shown in FIG. 16, the length of the LDD region is determined by the length L1 of the first conductive layer and the length L3 of the second conductive layer, and the LDD region does not overlap with the second conductive layer. The length can be determined by the length L5 at which the second conductive layer is etched. Such a method can increase the degree of freedom in designing or manufacturing a TFT.
Very effective.

On the other hand, third impurity regions 109, 110, 130, and 131 are formed in the p-channel TFT.
A region having a DD structure is not provided. The third impurity region includes the source regions 109 and 130 and the drain region 1
10 and 131 are formed. Then, part of the source region 109 and part of the drain region 110 overlap with the second conductive layer. Of course, the LDD structure of the present invention may be provided. However, since the p-channel TFT is originally high in reliability, it is preferable to increase the on-current and balance the characteristics with the n-channel TFT. When the present invention is applied to a CMOS circuit as shown in FIG. 1, it is particularly important to balance these characteristics. However, there is no problem even if the structure of the present invention is applied to a p-channel TFT.

When the n-channel type TFT and the p-channel type TFT are completed in this way, they are covered with a first interlayer insulating film 119, and source electrodes 120 and 121 and a drain electrode 122 are provided. In the structure of FIG. 1, after these are provided, a silicon nitride film is provided as the passivation film 123.
Further, a second interlayer insulating film 124 made of a resin material is provided. The second interlayer insulating film does not need to be limited to a resin material. For example, when applied to a liquid crystal display device, it is preferable to use a resin material in order to ensure surface flatness.

FIG. 1 shows an example of a CMOS circuit in which an n-channel TFT and a p-channel TFT are complementarily combined.
The present invention can also be applied to an S circuit or a pixel matrix circuit of a liquid crystal display device.

The configuration of the present invention described above will be described in more detail with reference to the following embodiments.

[Embodiment 1] In this embodiment, an example in which the configuration of the present invention is applied to a liquid crystal display device will be described, and a pixel matrix circuit and a driving circuit provided around the pixel matrix circuit will be described.
A method for simultaneously manufacturing a MOS circuit will be described with reference to FIGS.

In FIG. 29A, a substrate 401 includes
For example, an alkali-free glass substrate typified by a Corning 1737 glass substrate is used. Then, the T of the substrate 401
A base film 402 formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like over a surface where the FT is formed.
Is formed to a thickness of 200 nm.

Next, an amorphous silicon film having a thickness of 50 nm is formed on the base film 402 by a plasma CVD method. Although it depends on the hydrogen content of the amorphous silicon film, it is preferably heated to 400 to 500 ° C. to perform dehydrogenation treatment, and the hydrogen content of the amorphous silicon film is reduced to 5 atomic% or less.
A crystallization step is performed to obtain a crystalline silicon film.

In this crystallization step, a laser annealing method or a thermal annealing method may be used. In this embodiment, a crystalline silicon film is formed by condensing a pulse oscillation type KrF excimer laser beam linearly and irradiating it on an amorphous silicon film.

FIG. 32 shows the configuration of the laser annealing apparatus used here. Irradiated from the laser oscillation device 3201, the direction is changed by the reflection mirror 3202, and the optical system 32
A function of irradiating a substrate 3209 on which an amorphous silicon film is formed, by reflecting a pulsed laser beam whose optical path has been changed by 03 on a mirror 3207 and condensing it by an optical system 3208 using a cylindrical lens. have. The laser oscillation device 3201 may use a XeCl excimer laser or a KrF excimer laser.
The substrate 3209 is provided on the stage 3205.

In this embodiment, a crystalline silicon film is formed from an amorphous silicon film. However, a microcrystalline silicon film may be crystallized by a laser annealing method, or a crystalline silicon film may be formed directly. May be.

The crystalline silicon film thus formed is patterned to form island-like semiconductor layers 403, 404, and 405.
To form

Next, a gate insulating film 406 containing silicon oxide or silicon nitride as a main component is formed so as to cover the semiconductor layers 403, 404, and 405. Here, plasma C
A silicon oxynitride film is formed to a thickness of 100 nm by a VD method. Although not described in the figure, the gate insulating film 40
A first conductive layer is formed on the surface of No. 6. The first conductive layer is
10 to 200 nm of Ta, for example, 5 as the conductive layer (A)
0 nm and Al is 100 to 100 as a conductive layer (B).
It is formed by a sputtering method with a thickness of 0 nm, for example, 200 nm. Then, the conductive layers (A) 407, 408, 409 constituting the first conductive layer are formed by a known patterning technique.
410 and the conductive layers (B) 412, 413, 414, and 4
15 are formed. At this time, patterning is performed so that the length L1 of the first conductive layer shown in FIG. 31 is 3 μm.

When Al is used as the conductive layer (B) constituting the first conductive layer, pure Al may be used,
Element selected from Ti, Si, Sc is 0.1 to 5 atomic
% Added Al alloy may be used. In the case of using Cu, although not shown, a silicon nitride film is preferably provided on the surface of the gate insulating film 406.

FIG. 29 shows a structure in which a storage capacitor is provided on the drain side of the pixel TFT of the pixel matrix circuit. At this time, the capacitance wiring 4 is made of the same material as the first conductive layer.
11 and 416 are formed.

After the structure shown in FIG. 29A is formed, a first step of adding an impurity element imparting n-type is performed. Phosphorus (P), arsenic (As), antimony (Sb), and the like are known as impurity elements for imparting n-type to the crystalline conductor material. Here, phosphine (PH ₃ ) is used. Phosphorus is added by an ion doping method. In this step, the accelerating voltage is set to 80 k to add phosphorus to the underlying semiconductor layer through the gate insulating film 406.
Set to eV and higher. The impurity regions thus formed form first impurity regions 434 and 442 of an n-channel TFT described later, and function as LDD regions. Therefore, the concentration of phosphorus in this region is preferably in the range of 1 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ , and is set to 1 × 10 ¹⁸ atoms / cm ³ in this embodiment.

The impurity element added to the semiconductor layer needs to be activated by a laser annealing method or a thermal annealing method. This step may be performed after the step of adding the impurity element for forming the source region and the drain region, but it is effective to activate at this stage by the laser annealing method.

In this step, the conductive layers (A) 407, 408, 409, 410 and the conductive layers (B) 412, 413, 414, 415 constituting the first conductive layer serve as masks against the addition of phosphorus. Function. As a result, no or almost no phosphorus is added to a region directly below the first conductive layer of the semiconductor layer existing through the gate insulating film. Then, as shown in FIG. 29B, impurity regions 417, 418, 419, 420, 421, and 4 to which phosphorus has been added.
22, 423 are formed. In this specification, this impurity region is referred to as a first impurity region.

Next, using a photoresist as a mask, a region for forming an n-channel TFT is formed in a resist mask 42.
4 and 425, a step of adding a p-type impurity element is performed only in a region where a p-channel TFT is formed. Boron (B), aluminum (Al), and gallium (Ga) are known as impurity elements for imparting a p-type. In this embodiment, boron is used by ion doping with diborane (B ₂ H ₆ ). (B) is added. Again, the acceleration voltage is set to 80 keV, and boron is added to a concentration of 2 × 10 ²⁰ atmos / cm ³ . Then, as shown in FIG. 29C, a region 426 where boron (B) is added at a high concentration,
427 are formed. In this specification, this region is referred to as a third impurity region, and is hereinafter referred to as a source region and a drain region of a p-channel TFT.

After removing the resist masks 424 and 425, a step of forming a second conductive layer is performed. Here, Ta is used for the material of the second conductive layer, and 100 to 10
It is formed to a thickness of 00 nm, for example, 200 nm. Then, patterning is performed by a known technique to form second conductive layers 428, 429, 430, and 431. At this time, patterning is performed so that the length L2 of the second conductive layer shown in FIG. 31 is 6 μm. As a result, in the second conductive layer, regions in contact with the gate insulating film with a length of 1.5 μm are formed on both sides of the first conductive layer.

A storage capacitor is provided on the drain side of the pixel TFT in the pixel matrix circuit. The wiring 432 for the storage capacitor is formed simultaneously with the second conductive layer.

Then, the second conductive layers 428, 429, 4
A second step of adding an impurity element imparting n-type is performed using the masks 30 and 431 as masks. Phosphine (PH
₃ ) The gate insulating film 40 is formed by an ion doping method using
In order to add phosphorus (P) to the semiconductor layer therebelow through 6, the acceleration voltage is set as high as 80 keV. Since the region to which phosphorus (P) is added functions as the source regions 435 and 443 and the drain regions 434, 444 and 447 in the n-channel TFT, the concentration of phosphorus in this region is 1 × 10 ²⁰ to 1 × 10 ²¹ atmos / cm ³
It is preferably 1 × 10 ²⁰ atmos / cm ³ (FIG. 29D).

Although not shown here, source regions 435 and 443 and drain regions 436, 444 and 4
The gate insulating film covering 47 may be removed to expose the semiconductor layer in that region and directly add phosphorus. By this treatment, the acceleration voltage of the ion doping method can be reduced to 10 keV, and phosphorus can be efficiently added.

The source region 4 of the p-channel TFT is
Phosphorus is added at the same concentration to 39 and the drain region 440. However, since boron is added at twice the concentration in the previous step, the conductivity type is not inverted, and there is no problem in the operation of the p-channel TFT. There is no.

The n-type or p-type added at each concentration
Since the impurity element imparting the mold is not activated as it is and does not work effectively, it is necessary to perform an activation step.
This step includes a thermal annealing method using an electric heating furnace, a laser annealing method using the above-described excimer laser, and a rapid thermal annealing method using a halogen lamp (RT
A).

In the thermal annealing method, activation is performed by heating at 550 ° C. for 2 hours in a nitrogen atmosphere. In this embodiment, the conductive layer (B) constituting the first conductive layer is made of Al
However, since the conductive layer (A) and the second conductive layer formed of Ta are formed so as to cover Al, Ta functions as a blocking layer and Al atoms diffuse into other regions. Can be prevented. Also, in the laser annealing method, a pulse oscillation type KrF
Activation is performed by condensing and irradiating excimer laser light linearly. Further, if the thermal annealing method is performed after the laser annealing method, even better results can be obtained. This step also has the effect of annealing the region whose crystallinity has been destroyed by ion doping, and can improve the crystallinity of that region.

In the above steps, the gate electrode is provided with the first conductive layer, and the second conductive layer is provided so as to cover the first conductive layer. In the case of the n-channel TFT, both sides of the second conductive layer are provided. Then, a source region and a drain region are formed. In addition, a structure in which the first impurity region provided in the semiconductor layer is overlapped with the region of the second conductive layer which is in contact with the gate insulating film through the gate insulating film is formed in a self-aligned manner. . On the other hand, in the p-channel TFT, a part of the source region and the drain region is formed so as to overlap with the second conductive layer, but there is no problem in practical use.

When the state shown in FIG. 29D is obtained, a first interlayer insulating film 449 is formed to a thickness of 1000 nm. As the first interlayer insulating film 449, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film, or a stacked film thereof can be used. In this embodiment,
Although not shown, a two-layer structure in which a silicon nitride film is first formed to a thickness of 50 nm and a silicon oxide film is further formed to a thickness of 950 nm is provided.

The first interlayer insulating film 449 forms a contact hole reaching the source region and the drain region of each TFT by the patterning process. Then, the source wirings 450, 452, 453 and the drain wirings 451, 45
4 is formed. Although not shown, in this embodiment, this electrode is made of a Ti film having a thickness of 100 nm,
A film having a three-layer structure in which m and Ti films are successively stacked by 150 nm by a sputtering method is formed by patterning.

As shown in FIG. 29E, a CMOS circuit and a pixel matrix circuit are formed on the substrate 401. A storage capacitor is simultaneously formed on the drain side of the n-channel TFT of the pixel matrix circuit. As described above, an active matrix substrate can be manufactured.

Next, a process of manufacturing an active matrix type liquid crystal display device based on the CMOS circuit and the pixel matrix circuit manufactured on the same substrate by the above process will be described with reference to FIG. First, the source wirings 450, 452, 45 are placed on the substrate in the state shown in FIG.
3, a passivation film 455 is formed to cover the drain wirings 451 and 454 and the first interlayer insulating film 445.
The passivation film 455 is formed of a silicon nitride film with a thickness of 50 nm. Further, a second interlayer insulating film 456 made of an organic resin is formed to a thickness of about 1000 nm. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. The advantages of using an organic resin film include that the film forming method is simple, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. Note that an organic resin film other than those described above can also be used. Here, a polyimide that is thermally polymerized after application to the substrate is used, and is formed by baking at 300 ° C. (FIG. 30A).

Next, a light shielding layer 457 is formed in a part of the pixel region of the second interlayer insulating film 456. The light-blocking layer 457 may be formed using a metal film or an organic resin film containing a pigment. Here, a Ti film is formed by a sputtering method to form a light-shielding film.

After forming the light shielding film 457, a third interlayer insulating film 458 is formed. This third interlayer insulating film 458
Is preferably formed using an organic resin film in the same manner as the second interlayer insulating film 456. Then, the second interlayer insulating film 456
And a third interlayer insulating film 458, a contact hole reaching the drain wiring 454 is formed, and a pixel electrode 459 is formed. The pixel electrode 459 may be formed using a transparent conductive film when a transmissive liquid crystal display device is used, and a metal film may be used when a reflective liquid crystal display device is formed. Here, in order to obtain a transmissive liquid crystal display device, indium tin oxide (IT
O) A film is formed to a thickness of 100 nm by a sputtering method, and a pixel electrode 459 is formed.

The material for the transparent conductive film is etched with a hydrochloric acid-based solution. However, since a residue is easily generated in the etching of ITO, an indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) is used to improve the etching processability.
May be used. Indium zinc oxide alloys are characterized by having excellent surface smoothness and thermal stability as compared with ITO. Similarly, zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO :) to which gallium (Ga) is added to increase the transmittance and conductivity of visible light.
Ga) can be used.

After the state shown in FIG. 30A is formed, an alignment film 460 is formed. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element. Opposite substrate 47
1, a transparent conductive film 472 and an alignment film 473 are formed. After that, the alignment film is subjected to a rubbing treatment so that the liquid crystal molecules are aligned in parallel with a certain pretilt angle.

Through the above-described steps, the substrate on which the pixel matrix circuit and the CMOS circuit are formed and the counter substrate are bonded to each other by a well-known cell assembling step via a sealing material or a spacer (both not shown). Thereafter, a liquid crystal material 474 is injected between the two substrates, and completely sealed with a sealing agent (not shown). Accordingly, an active matrix liquid crystal display device illustrated in FIG. 30B is completed.

[Embodiment 2] In this embodiment, the configuration of the present invention will be described as a method of simultaneously manufacturing a pixel matrix circuit and a CMOS circuit which is a basic form of a driving circuit provided around the pixel matrix circuit.

In FIG. 2, as a substrate 201, an alkali-free glass substrate typified by, for example, a 1737 glass substrate manufactured by Corning Incorporated is used. Then, a base film 202 is formed on the surface of the substrate 201 where the TFT is to be formed. Base film 20
2 uses a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like.

The base film 202 may be formed of one layer of the above-mentioned materials, or may have a laminated structure of two or more layers. In any case, the film is formed to have a thickness of about 100 to 300 nm. For example, SiH ₄ , NH ₃ ,
The first silicon oxynitride film made of N ₂ O is
The base film 102 is formed in a two-layer structure in which a second silicon oxynitride film formed from SiH ₄ and N ₂ O is formed to a thickness of 100 to 200 nm.

The first silicon oxynitride film is formed by using a conventional parallel plate type plasma CVD method. As for the silicon oxynitride film, SiH ₄ is 10 SCCM, NH ₃ is 100 SCCM,
N ₂ O was introduced into the reaction chamber at 20 SCCM, and the substrate temperature was changed to 32 SCCM.
5 ° C., reaction pressure 40 Pa, discharge power density 0.41 W / cm ² ,
The discharge frequency was set to 60 MHz. On the other hand, the second silicon oxynitride film was introduced into the reaction chamber with SiH ₄ at ₄ SCCM and N ₂ O at 400 SCCM, and the substrate temperature was 400 ° C. and the reaction pressure was
a, the discharge power density was 0.41 W / cm ² , and the discharge frequency was 60 MHz. These films can be continuously formed only by changing the substrate temperature and switching the reaction gas. Also,
The first silicon oxynitride film is formed so that its internal stress becomes a tensile stress, considering the substrate as a center. The second silicon oxynitride film also has an internal stress in the same direction, but has a smaller stress than the first silicon oxynitride film in absolute value.

Next, 30 to 80 is formed on the underlying film 202.
An amorphous silicon film having a thickness of, for example, 50 nm is formed by a plasma CVD method. Thereafter, the amorphous silicon film preferably has a temperature of 400 to 500 ° C., although it depends on the hydrogen content.
Dehydrogenation by heating to 5 atomic% of hydrogen content
It is desirable to perform a crystallization step as follows.

The step of crystallizing the amorphous silicon film is performed by a laser annealing method or a thermal annealing method. In this embodiment, a pulse oscillation type KrF excimer laser beam is condensed linearly and irradiated on an amorphous silicon film to form a crystalline silicon film.

Although the amorphous silicon film is used in this embodiment, a microcrystalline silicon film may be used, or a crystalline silicon film may be formed directly.

The crystalline silicon film thus formed is patterned to form island-like semiconductor layers 204, 205, and 20.
6 is formed.

Next, a gate insulating film 203 containing silicon oxide or silicon nitride as a main component is formed so as to cover the semiconductor layers 204, 205, and 206. For example, plasma C
A silicon oxynitride film is formed to a thickness of 100 nm by a VD method. Although not described in the drawing, the gate insulating film 20
A Ta film as the conductive layer (A) constituting the first conductive layer of the gate electrode on the surface of No. 3 with a thickness of 10 to 200 nm, for example, 50
and a 10 nm thick Al film as a conductive layer (B).
It was formed by a sputtering method with a thickness of 0 to 1000 nm, for example, 200 nm. Then, the conductive layers (A) 207 and 2 forming the first conductive layer are formed by a known patterning technique.
08, 209, 210 and conductive layers (B) 212, 21
3, 214 and 215 are formed. At this time, the length L1 of the first conductive layer shown in FIG.
Patterning is performed with a length of 10 μm to 10 μm, here 3 μm (FIG. 2A).

When Al is used as the conductive layer (B) constituting the first conductive layer, pure Al may be used,
Element selected from Ti, Si, Sc is 0.1 to 5 atomic
% Added Al alloy may be used. In the case of using copper, although not shown, it is preferable to provide a silicon nitride film with a thickness of 30 to 100 nm on the surface of the gate insulating film 203.

Conductive layers (A) 207, 208, 209, 2
When a Ta film is used for 10, it can be similarly formed by a sputtering method. The Ta film is made of Ar as a sputtering gas.
Is used. In addition, an appropriate amount of Xe
If Kr or Kr is added, the internal stress of the film to be formed can be relaxed to prevent the film from peeling. The α-phase Ta film has a resistivity of about 20 μΩcm and can be used as a gate electrode, but the β-phase Ta film has a resistivity of about 180 μΩcm and is not suitable for a gate electrode. But T
Since the aN film has a crystal structure close to the α phase, Ta
When a film is formed, an α-phase Ta film can be easily obtained. Therefore, although not shown, the conductive layers (A) 207, 208, 20
A TaN film having a thickness of 10 to 50 nm may be formed under 9, 210. Similarly, although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm below the conductive layer (A).
Thereby, the adhesion of the conductive film formed thereon is improved and oxidation is prevented, and at the same time, a small amount of an alkali metal element contained in the conductive layer (A) or the conductive layer (B) diffuses into the gate insulating film 203. Can be prevented. In any case, the resistivity of the conductive layer (A) is preferably in the range of 10 to 50 μΩcm.

In addition, the conductive layers (A) 207, 208,
It is also possible to use a W film for 209 and 210. In this case, an argon (Ar) gas and a nitrogen (N ₂ ) gas are introduced into the conductive layer (A) by a sputtering method using W as a target to form a W film. To a thickness of 200 nm. Further, the W film can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, in order to use it as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 μΩcm or less. W
The resistivity of the film can be reduced by enlarging the crystal grains. However, when the W film contains many impurity elements such as oxygen, the crystallization is inhibited and the resistance is increased. Thus, in the case of using the sputtering method, a W target having a purity of 99.9999% is used, and further, the W film is formed with sufficient care so as not to mix impurities from the gas phase during film formation. 9 to 20 μΩcm can be realized.

In FIG. 2, a storage capacitor is provided on the drain side of the pixel TFT of the pixel matrix circuit. At this time, the wirings 211 and 216 of the storage capacitor are formed using the same material as the first conductive layer.

Thus, the structure shown in FIG. 2A was formed.
Then, a first step of adding an impurity element imparting n-type
Is performed to form a first impurity region. Crystalline semiconductor material
Examples of the impurity element that imparts n-type to the material include phosphorus.
(P), arsenic (As), antimony (Sb), etc.
For example, using phosphine (PH
_Three) Is performed by the ion doping method. In this step,
Phosphorous is added to the underlying semiconductor layer through the gate insulating film 203.
To increase the acceleration voltage to 80 keV.
Was. The first impurity region thus formed has an n
First impurity regions 229, 236 of the channel type TFT;
240 and functions as an LDD region.
It is. Therefore, the concentration of phosphorus in this region is 1 × 10¹⁶
~ 5 × 10¹⁹atoms / cm^ThreeThe range is preferably
Here is 1 × 10¹⁸atoms / cm^Three(FIG. 2B).

The impurity element added to the semiconductor layer needs to be activated by a laser annealing method or a thermal annealing method. This step may be performed after the step of adding an impurity element for forming the source region and the drain region, but it is effective to activate by laser annealing at this stage.

In this step, the conductive layers (A) 207, 208, 209, and 210 and the conductive layers (B) 212, 213, 214, and 215 constituting the first conductive layer serve as masks against the addition of phosphorus. Function. As a result, no or almost no phosphorus is added to a region of the semiconductor layer which overlaps with the first conductive layer. Here, as shown in FIG. 2B, the first impurity region 218 to which phosphorus is added,
219, 220, 221 and 222 are formed.

Next, using the photoresist film as a mask, n
A region for forming a channel type TFT is formed by a resist mask 22.
The step of adding an impurity for imparting p-type is performed only on the region where the p-channel TFT is formed, which is covered with 5, 226.
As the impurity element imparting the p-type, boron (B), aluminum (Al), and gallium (Ga) are known. Here, boron is used as the impurity element and diborane (B ₂ H ₆ ) is added to the semiconductor layer by an ion doping method. The acceleration voltage is 80 keV and 2 × 10 ²⁰ atoms / cm
Add boron to a concentration of ³ . Then, third impurity regions 227 and 228 to which boron is added at a high concentration are formed as shown in FIG. The third impurity region will later become a source region and a drain region of the p-channel TFT (FIG. 2C).

After removing the resist masks 225 and 226, a step of forming a second conductive layer is performed. Using Ta as the material, 100 to 1000 nm (for example, 2
(00 nm). Then, patterning is performed by a known technique, and the second conductive layers 243, 244,
245 and 246 are formed. At this time, as shown in FIG. 16, the length L3 of the second conductive layer in the channel length direction is 1.3 to 1.3.
Patterning is performed so as to be 20 μm, for example, 9 μm. As a result, in the second conductive layer, a region (L6) having a length of 3 μm and being in contact with the gate insulating film is formed on both sides of the first conductive layer.

A storage capacitor is provided on the drain side of an n-channel TFT (pixel TFT) constituting the pixel matrix circuit, and the electrode 247 of the storage capacitor is formed simultaneously with the second conductive layer.

Then, the second conductive layers 243, 244, 2
Using the masks 45 and 246 as masks, a second step of adding an impurity element imparting n-type is performed to form a second impurity region. At this time, as shown in FIG. 3A, a resist mask 28 provided when patterning the second conductive layer is used.
3, 284, 285, 286, 287 may be left as they are. The addition of the impurity element is performed by phosphine (P
H ₃ ) was used. Also in this step, the acceleration voltage was set as high as 80 keV in order to add phosphorus to the underlying semiconductor layer through the gate insulating film 203. The second impurity regions formed here are the source regions 230 and 237 of the n-channel TFT,
In order to function as the drain regions 231, 238, and 241, the concentration of phosphorus in this region is 1 × 10 ²⁰ to 1
It is preferably set to × 10 ²¹ atoms / cm ^3, and in this embodiment, set to 1 × 10 ²⁰ atoms / cm ³ (FIG. 3A).

Although not shown here, the source regions 230, 237, 289 and the drain regions 231, 211
38, 241, 288, the gate insulating film is removed,
The semiconductor layer in that region may be exposed and phosphorus may be directly added. By adding this step, the acceleration voltage of the ion doping method can be reduced to 10 keV, and phosphorus can be efficiently added.

Further, phosphorus is added at the same concentration to portions 288 and 289 of the third impurity region of the p-channel type TFT, but boron is added at twice the concentration, so that the conductivity type is There is no problem in operation of the p-channel TFT without inversion. In a p-channel TFT, the third
The source region is formed by 234 and 289, and the drain region is formed by 233 and 288 by the impurity regions 234, 289, 233, and 288 of FIG. At this time, the source region 234 and the drain region 233 overlap with the second conductive layer 244.

When the state shown in FIG. 3A is obtained, the resist masks 283, 284, 285, 286, and 287 are removed, a photoresist film is formed again, and a resist mask is formed by exposure from the back. At this time, FIG.
As shown in (B), resist masks 248, 249, and 2 are self-aligned using the first and second conductive layers as masks.
50, 256, 257 are formed. Exposure from the back
This is performed by using direct light and scattered light. By performing over-exposure, the resist mask is changed to the second as shown in FIG.
Can be provided inside the conductive layer.

Then, the unmasked region of the second conductive layer is removed by etching. The etching may be performed using a normal dry etching technique, and is performed using CF ₄ and O ₂ gas. Then, as shown in FIG.
Remove the length of The length of L5 may be appropriately adjusted in the range of 0.5 to 3 μm, and is 1.5 μm in this case.
As a result, in the n-channel TFT, 1.5 μm out of 3 μm in the length of the first impurity region serving as the LDD region.
A region overlapping with the second conductive layer was formed with a length of (L4), and a region not overlapping with the second conductive layer was formed with a length of 1.5 μm (L5).

N-type or p-type added at each concentration
Since the impurity element imparting the mold is not activated as it is and does not work effectively, it is necessary to perform an activation step.
This step includes a thermal annealing method using an electric heating furnace, a laser annealing method using an excimer laser described above, and a rapid thermal annealing method (R
TA method).

In the thermal annealing method, activation is performed by heat treatment in a nitrogen atmosphere at 300 to 700 ° C., preferably 350 to 550 ° C., for example, 450 ° C. for 2 hours. In this embodiment, the conductive film (B) constituting the first conductive layer is formed of A
1 and the conductive film (A) formed of Ta and the second conductive layer are formed so as to cover Al.
Can function as a blocking layer to prevent Al atoms from diffusing into other regions. In the laser annealing method, activation is performed by condensing and irradiating a pulse oscillation type KrF excimer laser beam in a linear shape. Further, if the thermal annealing method is performed after the laser annealing method, even better results can be obtained. This step also has an effect of annealing a region whose crystallinity has been destroyed by the ion doping method, and can improve the crystallinity of the region.

In the above steps, the gate electrode is provided with the first conductive layer, and the second conductive layer is provided in contact with the first conductive layer.
Impurity region and a second region serving as a source region and a drain region.
Is formed. Then, a region which does not overlap with a region overlapping with the second conductive layer with the gate insulating film interposed therebetween is formed in the first impurity region. On the other hand, p-channel type TF
At T, a channel formation region, a source region, and a drain region are formed.

When the steps up to FIG. 3B are completed, the resist masks 248, 249, 250, 256, 257 are removed, and the first interlayer insulating film 263 is formed to 500 to 1500.
It is formed to a thickness of nm. As the first interlayer insulating film 263, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film, or a stacked film thereof can be used. In this embodiment, although not shown, a silicon nitride film is first formed to a thickness of 50 nm, and
It has a two-layer structure of 50 nm. Alternatively, a silicon oxynitride film made of SiH ₄ and N ₂ O is 1000
m.

Thereafter, a contact hole reaching the source region and the drain region of each semiconductor layer is formed in the first interlayer insulating film 263. Then, the source wiring 26
4, 265, 266 and drain wirings 267, 268 are formed. Although not shown, in this embodiment, the wiring has a three-layer structure, a Ti film 100 nm, an Al film 3 containing Ti.
It is formed continuously by sputtering with a thickness of 00 nm and a thickness of 150 nm of Ti film.

Then, the source electrodes 264, 265, 26
6, a passivation film 269 is formed to cover the drain electrodes 267 and 268 and the first interlayer insulating film 263.
The passivation film 269 is a silicon nitride film having a thickness of 50 n.
m. Further, a second interlayer insulating film 270 made of an organic resin is formed to a thickness of about 1000 nm.
As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. The advantages of using an organic resin film include that the film formation method is simple, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. Note that an organic resin film other than those described above can be used. Here, it is formed by baking at 300 ° C. using a type of polyimide which is thermally polymerized after being applied to the substrate.

In this way, as shown in FIG.
01 on the CMOS circuit and the pixel T of the pixel matrix circuit.
An active matrix substrate on which the FT is formed is manufactured. A storage capacitor is simultaneously formed on the drain side of the pixel TFT of the pixel matrix circuit.

[Embodiment 3] In this embodiment, after the state shown in FIG. 3A is obtained in the same steps as in Embodiment 1, a part of the second conductive layer is removed by another method, and An example in which one impurity region forms a region overlapping with the second conductive layer and a region not overlapping with the second conductive layer will be described.

First, as shown in FIG. 3A, the resist mask 28 used in the step of patterning the second conductive layer is used.
3, 284, 285, 286, 287 are used as they are, and a part of the second conductive layer is etched as shown in FIG.
As shown in (A), the length is removed by the length of L5.

This step can be performed by dry etching. Although it depends on the material of the second conductive layer, isotropic etching basically proceeds by using a fluorine (F) -based gas, and the material of the second conductive layer below the resist mask can be removed. it can. For example, in the case of Ta, CF
It is possible with _four gases, in the case of Ti, it is possible with CF ₄ or CCl ₄ gas, and in the case of Mo, it is possible with SF ₆ or NF ₃ .

Then, as shown in FIG. 4A, 1.5 μm is removed here by the length of L5. As a result, n
In the channel type TFT, the first impurity region serving as the LDD region is formed with a length (L6) of 3 μm,
A region overlapping with the second conductive layer is formed with a length (L4) of 1.5 μm, and a region not overlapping with the second gate electrode can be formed with a length (L5) of 1.5 μm.

Then, the resist masks 283, 284, 2
85, 286, and 287 are removed, and an activation step is performed in the same manner as in the first embodiment. The first interlayer insulating film 263, the source wirings 264, 265, 266, and the drain wirings 267, 26
8, passivation film 269, second interlayer insulating film 27
By forming 0, the active matrix substrate shown in FIG. 4B can be formed.

[Embodiment 4] In this embodiment, a process for manufacturing an active matrix liquid crystal display device from the active matrix substrates formed in Embodiments 1 to 3 and Embodiment 5 will be described.

A second interlayer insulating film 27 is formed on the active matrix substrate in the state shown in FIG.
At 0, a contact hole reaching the drain electrode 268 is formed, and a pixel electrode 271 is formed. The pixel electrode 271 is
When a transmission type liquid crystal display device is used, a transparent conductive film is used,
In the case of a reflective liquid crystal display device, a metal film may be used. Here, in order to form a transmissive liquid crystal display device, an indium tin oxide (ITO) film is formed to a thickness of 100 nm by a sputtering method, and the pixel electrode 271 is formed.

After the state of FIG. 5A is formed, the alignment film 2
72 is formed on the second interlayer insulating film 270 and the pixel electrode 271. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element. A transparent conductive film 274 and an alignment film 275 are formed on the substrate 273 on the opposite side. After the alignment film is formed, a rubbing treatment is performed so that the liquid crystal molecules are parallel-aligned with a certain pretilt angle.

Through the above steps, the pixel matrix circuit, the active matrix substrate on which the CMOS circuit is formed, and the counter substrate are pasted by a known cell assembling step via a sealing material or a spacer (both not shown). Fit together. Thereafter, a liquid crystal material 276 is injected between the two substrates, and completely sealed with a sealing agent (not shown). Therefore, FIG.
The active matrix type liquid crystal display device shown in FIG.

Next, the structure of the active matrix type liquid crystal display device of this embodiment will be described with reference to FIGS. FIG. 7 is a perspective view of the active matrix substrate of this embodiment. The active matrix substrate includes a pixel matrix circuit 701 formed on a glass substrate 201, a scanning (gate) line side driving circuit 702, and a data (source) line side driving circuit 703. Pixel TF of pixel matrix circuit
T700 is an n-channel TFT, and a peripheral driving circuit is configured based on a CMOS circuit. The scan (gate) line side drive circuit 702 and the data (source) line side drive circuit 703 are each provided with a gate wiring 802.
And a source wiring 803 connected to the pixel matrix circuit 701.

FIG. 8A is a top view of the pixel matrix circuit 701, and is a top view of substantially one pixel. A pixel TFT is provided in the pixel matrix circuit. The gate electrode 820 formed continuously with the gate wiring 802 is connected to a semiconductor layer 8 thereunder via a gate insulating film (not shown).
Intersects with 01. Although not shown, a source region, a drain region, and a first impurity region are formed in the semiconductor layer. On the drain side of the pixel TFT, a storage capacitor 8 is formed by a semiconductor layer, a gate insulating film, and a capacitor wiring 821 formed of the same material as the first and second conductive layers.
07 is formed. Further, A- shown in FIG.
The cross-sectional structure along A ′ is shown in FIG.
Corresponds to the sectional view of the pixel TFT of the pixel matrix circuit shown in FIG.

On the other hand, in the CMOS circuit shown in FIG. 8B, a gate electrode 813 extending from a gate wiring 815,
Reference numeral 814 intersects the semiconductor layers 810 and 812 thereunder via a gate insulating film (not shown).
Although not shown, a source region, a drain region, and a first impurity region are similarly formed in the semiconductor layer 810 of the n-channel TFT. Also, a p-channel TFT
In the semiconductor layer 812, a source region and a drain region are formed. The cross-sectional structure along BB ′ corresponds to the cross-sectional view of the pixel matrix circuit illustrated in FIG. 3C or 4C.

In this embodiment, the pixel TFT 700 has a double gate structure, but may have a single gate structure or a multi-gate structure having a triple gate. The structure of the active matrix substrate of this embodiment is not limited to the structure of this embodiment. The structure of the present invention is characterized by the structure of a gate electrode, the structure of a source region, a drain region, and other impurity regions of a semiconductor layer provided with a gate insulating film interposed therebetween. The practitioner may decide appropriately.

[Embodiment 5] This embodiment is the same as the embodiment 2, except that the pixel TFT of the pixel matrix circuit and the CMOS
S-circuit n-channel TFT and p-channel TFT
2 shows an example in which the structure of the second conductive layer is different. At this time, as shown in FIG.
Reference numeral 91 denotes a form in contact with the first conductive layer and extending only to the drain side of each TFT. In a CMOS circuit, a high electric field region formed on the drain side of the TFT can be reduced even when the second conductive layer of the n-channel TFT has such a shape. On the other hand, the second pixel TFT
The conductive layers 292 and 293 and the capacitor wiring 294 are formed in the same manner as in the first embodiment.

The steps of the present embodiment may basically follow the steps described in the second embodiment, and the shape of the second conductive layer is changed only by changing the photomask used in the patterning step. No changes are required. However, the first impurity region of the n-channel TFT is formed only on the drain region side.

Then, as shown in FIG. 6B, the resist masks 223, 224, 225, 226, and 227 are removed, a photoresist film is formed again, and patterning is performed by exposure from the back surface. At this time, as shown in FIG. 6B, the resist masks 248, 249, 250, and 25 are self-aligned using the first and second conductive layers as masks.
6, 257 are formed. Exposure from the back surface is performed using direct light and scattered light. By performing overexposure, a resist mask can be provided inside the second conductive layer as shown in FIG. 6B.

Then, the unmasked region of the second conductive layer is removed by etching. The etching may be performed using a normal dry etching technique, and is performed using CF ₄ and O ₂ gas. Then, as shown in FIG.
Remove the length of The length of L5 may be appropriately adjusted in the range of 0.5 to 3 μm, and is set to 1.5 μm here.
As a result, in the n-channel TFT, 1.5 μm out of 3 μm in the length of the first impurity region serving as the LDD region.
A region overlapping with the second conductive layer is formed with a length of (L4), and a region not overlapping with the second gate electrode can be formed with a length of 1.5 μm (L5). The subsequent steps are:
The active matrix substrate shown in FIG. 6C is formed in the same manner as in the first embodiment.

[Embodiment 6] In this embodiment, Embodiments 1 and 2 will be described.
In Examples 1, 2, 3, and 5, a crystalline semiconductor film used as a semiconductor layer is formed by a thermal annealing method using a catalytic element. When a catalyst element is used, it is desirable to use the technology disclosed in JP-A-7-130652 and JP-A-8-78329.

FIG. 9 shows an example in which the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652 is applied to the present invention. First, a silicon oxide film 902 was provided over a substrate 901, and an amorphous silicon film 903 was formed thereover. Further, a nickel acetate solution containing 10 ppm by weight of nickel is applied to form a nickel-containing layer 904 (FIG. 9A).

Next, after the dehydrogenation step at 500 ° C. for 1 hour, the temperature is set at 500-650 ° C. for 4-12 hours, for example, 550 ° C.
A heat treatment is performed at 8 ° C. for 8 hours to form a crystalline silicon film 905. The crystalline silicon film 905 thus obtained has very excellent crystallinity (FIG. 9B).

Further, the technique disclosed in Japanese Patent Application Laid-Open No. 8-78329 allows selective crystallization of an amorphous semiconductor film by selectively adding a catalytic element. FIG. 1 shows a case where the same technology is applied to the present invention.
0 will be described.

First, a silicon oxide film 1002 is provided on a glass substrate 1001, and an amorphous silicon film 100
3. A silicon oxide film 1004 is formed continuously. At this time, the thickness of the silicon oxide film 1004 is set to 150 nm.

Next, the silicon oxide film 1004 is patterned to selectively form openings 1005, and then a nickel acetate salt solution containing 10 ppm by weight of nickel is applied. Thus, a nickel-containing layer 1006 is formed, and the nickel-containing layer 1006 is in contact with the amorphous silicon film 1002 only at the bottom of the opening 1005 (FIG. 10A).

Next, at 500 to 650 ° C. for 4 to 24 hours,
For example, heat treatment at 570 ° C. for 14 hours is performed to form a crystalline silicon film 1007. In this crystallization process, the portion of the amorphous silicon film in contact with nickel is first crystallized, and the crystallization proceeds laterally from there. The crystalline silicon film 1007 thus formed is made up of a collection of rod-shaped or needle-shaped crystals, each of which grows in a specific direction when viewed macroscopically, and thus has uniform crystallinity. (FIG. 10B).

The catalyst elements that can be used in the above two technologies are iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), and nickel (Ni). Platinum (Pt), copper (Cu), gold (Au),
May be used.

By forming a crystalline semiconductor film (including a crystalline silicon film and a crystalline silicon germanium film) using the above-described techniques and performing patterning, a crystalline T
An FT semiconductor layer can be formed. The TFT manufactured from the crystalline semiconductor film using the technique of the present embodiment is:
Although excellent characteristics can be obtained, high reliability is required. However, by adopting the TFT structure of the present invention, the TFT utilizing the technology of this embodiment to the maximum
Can be manufactured.

[Embodiment 7] This embodiment is directed to a method of forming a semiconductor layer used in Embodiments 1 and 2 and Embodiments 1, 2, 3, and 5 by using an amorphous semiconductor film as an initial film to form the catalyst. An example in which a step of removing a catalytic element from a crystalline semiconductor film after forming a crystalline semiconductor film using an element is described. In this embodiment, the method is disclosed in
7735, the technique described in JP-A-10-135468 or 10-135469.

The technique described in the publication is a technique for removing the catalytic element used for crystallization of the amorphous semiconductor film by using the gettering action of phosphorus after crystallization. By using this technique, the concentration of the catalytic element in the crystalline semiconductor film can be reduced to 1 × 1
It can be reduced to 0 ¹⁷ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ .

The configuration of this embodiment will be described with reference to FIG. Glass substrate 1101 is Corning 1737
A non-alkali glass substrate represented by a substrate is used.
FIG. 11A shows a state in which a base 1102 and a crystalline silicon film 1103 are formed by using the crystallization technique described in Embodiment 5. Then, the crystalline silicon film 1
A silicon oxide film 1104 for a mask is
It is formed to a thickness of 50 nm, an opening is provided by patterning, and a region exposing the crystalline silicon film is provided. Then, a step of adding phosphorus is performed to provide a region 1105 to which phosphorus is added in the crystalline silicon film.

In this state, 550-80
When heat treatment is performed at 0 ° C. for 5 to 24 hours, for example, at 600 ° C. for 12 hours, the region 1105 in which phosphorus is added to the crystalline silicon film functions as a gettering site, and the catalyst remaining in the crystalline silicon film 1103 The element can be segregated in the region 1105 to which phosphorus is added.

Then, the silicon oxide film 110 for the mask is used.
4 and the phosphorus-added region 1105 are removed by etching, so that the concentration of the catalytic element used in the crystallization step is reduced to 1 × 10 ¹⁷ atoms / cm ³ or less. Can be obtained. This crystalline silicon film can be used as it is as the semiconductor layer of the TFT of the present invention shown in Examples 1, 2, and 4.

[Embodiment 8] In this embodiment, Embodiments 1 and 2
And TFTs of the present invention shown in Examples 1, 2, 3, and 5
Another embodiment in which a semiconductor layer and a gate insulating film are formed in the step of fabricating the semiconductor device will be described. The configuration of this embodiment will be described with reference to FIG.

Here, at least 700 to 1100 ° C.
A substrate having a high degree of heat resistance is required.
01 is used. Then, a crystalline semiconductor is formed by using the technique described in the fifth embodiment. In order to make this a semiconductor layer of the TFT, it is patterned in an island shape to form a semiconductor layer 1202, 1
203 is formed. Then, the semiconductor layers 1202, 120
3, a gate insulating film 1204 was formed with a film containing silicon oxide as a main component. In this embodiment, the plasma CV
A silicon oxynitride film is formed with a thickness of 70 nm by Method D (FIG. 12A).

Then, heat treatment is performed in an atmosphere containing halogen (typically chlorine) and oxygen. In this embodiment, 95
0 ° C., 30 minutes. Incidentally, the processing temperature is 700 to 1100.
The temperature may be selected within the range of ° C., and the processing time may be selected from 10 minutes to 8 hours (FIG. 12B).

As a result, under the conditions of this embodiment, a thermal oxide film is formed at the interface between the semiconductor layers 1202 and 1203 and the gate insulating film 1204, and a gate insulating film 1207 is formed. Further, in the process of oxidation in a halogen atmosphere, impurities included in the gate insulating film 1204 and the semiconductor layers 1202 and 1203, particularly metal impurity elements, form a compound with halogen and can be removed in the gas phase.

Gate insulating film 12 manufactured by the above steps
In No. 07, the withstand voltage was high and the interface between the semiconductor layers 1205 and 1206 and the gate insulating film 1207 was very good. In order to obtain the structure of the TFT of the present invention, the subsequent steps may be performed in accordance with the first, second and fourth embodiments.

[Embodiment 9] In this embodiment, an example of manufacturing a crystalline TFT in a different process order from that of Embodiment 2 is shown in FIG. First, in Embodiment 2, as the semiconductor layers 204, 205, and 206 shown in FIG. 2A, a crystalline silicon film manufactured by the method described in Embodiment 6 is used. At this time, a small amount of the catalyst element used in the crystallization step remains in the semiconductor layer. Subsequent steps are performed in accordance with FIG.
The process up to the step of adding an impurity for imparting a p-type shown in FIG. Then, the resist masks 258 and 259 are removed.

At this time, as shown in FIG. 13, source regions 230 and 237 of the n-channel TFT, drain regions 231 238 and 241, source regions 234 and 289 and a drain region 233 of the p-channel TFT are formed. 28
No. 8 contains phosphorus added in the step of FIG. 3 (A). According to Example 1, the phosphorus concentration at this time is 1
× 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ .

In this state, 400 to 80 in a nitrogen atmosphere.
A heat treatment process is performed at 0 ° C. for 1 to 24 hours, for example, 550 ° C. for 4 hours. By this step, the added impurity element imparting n-type and p-type can be activated.
Further, the region to which the phosphorus is added becomes a gettering site, and the catalyst element remaining after the crystallization step can be segregated. As a result, the catalyst element can be removed from the channel formation region.

After the step of FIG. 13 is completed, the subsequent steps follow the steps of Embodiment 1 to form the state of FIG. 3C, whereby an active matrix substrate can be manufactured.

[Embodiment 10] In this embodiment, the T
FIG. 14 illustrates an example of a structure of a gate electrode in an FT. The gate electrode includes a first conductive layer and a second conductive layer formed in contact with the first conductive layer. And the first
Are formed from one or a plurality of conductive layers.

FIG. 14A shows a conductive layer (A) 17 formed in contact with the gate insulating film of the first conductive layer of the gate electrode.
01 is formed of a Mo—Ti film, laminated on the conductive layer (A), the conductive layer (B) 1702 is formed of a Ti film, and the conductive layer (C) 1703 is formed of a film containing Al as a main component. The conductive layer (D) 1704 is formed of a Ti film. Here, the thickness of the conductive layer (A) is 30 to 200 nm, and the thickness of the conductive layer (B) to the conductive layer (D) is 5 nm.
It is desirable to form it with a thickness of 0 to 100 nm.

The conductive layer (A) in contact with the gate insulating film serves as a barrier layer for preventing the constituent elements of the conductive layer formed thereon from seeping into the gate insulating film. It is desirable to use a high melting point metal such as W or Mo or an alloy material thereof. FIG. 14A
The conductive layer (C) 1703 formed by is a film containing Al as a main component, and is provided to reduce the resistivity of the gate electrode. Then, in order to improve the flatness of the Al film to be formed, elements such as Sc, Ti, and Si are added in an amount of 0.1 to 5 atoms.
It is desirable to use an Al alloy film containing ic%. In any case, when the present invention is applied to a liquid crystal display device of a 10-inch class or more, use a material having a low resistivity mainly composed of Al or Cu in order to reduce the resistance of the gate electrode. Is desirable. Further, the second conductive layer 1705 formed in contact with the first conductive layer and the gate insulating film is formed of Ti, Ta,
It is desirable to use a high melting point metal such as W or Mo or an alloy material thereof.

FIG. 14B shows another configuration example, in which the conductive layer (A) 1706 is a single layer made of a Mo—W alloy film or a W film, and the second conductive layer 1707 is a Ti film. Things. The second conductive layer 1707 is made of Ta, M
o and W may be formed. The conductive layer (A) 1706 may have a thickness of 50 to 100 nm.

FIG. 14C shows that a conductive layer (A) 1708 constituting a first conductive layer of a gate electrode is formed of a Ti film,
The conductive layer (B) 1709 is formed of a film containing copper (Cu) as a main component, and the conductive layer (C) 1710 is formed of a Ti film. Even if a Cu film is used similarly to the Al film, the resistivity of the gate electrode and the gate wiring can be reduced. The second conductive layer 1711 is formed using a film of Ti, Mo, W, Ta, or the like.

FIG. 14D shows that the conductive layer (A) 1712 forming the first conductive layer is formed of a Ti film and the conductive layer (B) is formed.
1713 is formed by a film containing Al as a main component, and the conductive layer (C) 1714 is formed by a Ti film. The second conductive layer 1715 is formed using a film of Ti, Mo, W, Ta, or the like.

FIG. 14E shows that a conductive layer (A) 1716 constituting a first conductive layer of a gate electrode is formed of a Ti film,
The surface is nitrided to provide a titanium nitride (TiN) film 1720. The thickness of the TiN film is 30 to 200
The thickness may be set to 10 to 100 nm with respect to nm, and is set to 20 nm here. TiN film is a conductive layer (A) by sputtering.
When forming the Ti film 1716, a nitrogen gas having a flow rate ratio of about 10 to 30% may be added to the argon gas. At this time, the content in the film may be set to 20 to 50 atomic%, preferably 40 atomic%. . And the conductive layer (B) 171
7 is formed of a film mainly containing Al, and a conductive layer (C) 17 is formed.
18 is formed of a Ti film. At this time, before forming the Ti film, T
The iN film 1721 may be formed. And the second
Is formed of a Ti film. At this time, Ti
The TiN film 1722 may be formed before the film is formed.

By providing a TiN film at the interface with the conductive layer (B) 1717 as shown in FIG.
1 can be prevented from directly reacting. Such a configuration of the gate electrode is effective for the heat activation process of the first embodiment and the heat treatment process performed in the eighth embodiment.
300-700 ° C, preferably 350-550 ° C
The process can be carried out within the range.

FIG. 14F shows that a conductive layer (A) 1723 forming the first conductive layer of the gate electrode is formed of a Ti film,
The conductive layer (B) 1724 is formed using a film mainly containing Al, and the second conductive layer 1725 is formed using a Ta film. Similarly, a TiN film 1726 and a TaN film 1727 are formed on a surface in contact with the conductive layer (B) 1724. Similarly, the TaN film may be formed by adding nitrogen to argon gas at a flow rate of 1 to 10% by a sputtering method.
It is preferable that the amount of nitrogen contained in the film is 35 to 60 atomic%, preferably 45 to 50 atomic%. With such a structure, heat resistance can be improved as in the structure example of FIG.

Such a configuration of the gate electrode can be suitably used in combination with the TFTs of Embodiments 1 and 2 and Examples 1, 2, 3, and 5.

[Embodiment 11] In this embodiment, an example in which L4 shown in FIG. 16 is different between the semiconductor layer and its periphery will be described with reference to FIG.

In FIG. 18, a first conductive layer 1841 and a second conductive layer 1 of a gate electrode are formed on a semiconductor layer 1840.
842 are formed. At this time, the second conductive layer 184
2 is formed so as to cover the first conductive layer 1841. In this specification, the length of a portion which does not overlap with the first conductive layer 1841 is defined as L4.

In the case of this embodiment, the length of L4 (referred to as WDDD here) is 0.5 to 3 μm on the semiconductor layer. Then, in the wiring portion (the peripheral portion other than above the semiconductor layer), the length of L4 ′ (referred to here as WL) is set to 0.1 to 1.5 μm.
m.

That is, the present embodiment is characterized in that the line width of the second conductive layer is narrower in the wiring portion than on the semiconductor layer. This is because a region corresponding to L4 is not necessary in the wiring portion, which is a factor that hinders high-density integration of the wiring. Therefore, it is preferable to reduce the line width as much as possible.

Therefore, by using the structure of this embodiment, high-density integration of wirings is facilitated, and high-density integration of a semiconductor device becomes possible. Note that the configuration of this embodiment can be freely combined with any of the configurations of Embodiments 1 to 10.

[Embodiment 12] In this embodiment, Embodiments 1 and 2
14 shows another example of the step of forming the storage capacitor provided on the active matrix substrate of FIG. An n-channel type T is formed on the substrate in the state shown in FIG.
A region for forming an FT is covered with resist masks 225 and 295, and a region for forming a p-channel TFT and a region for forming a storage capacitor are subjected to an impurity doping process for imparting p-type conductivity. Here, as in the first embodiment, 2 × 10 ²⁰ at
Add boron to a concentration of oms / cm ³ . Then, as shown in FIG. 19, third impurity regions 227, 228, and 296 to which boron is added at a high concentration are formed.

When boron (B) is added at a high concentration to the semiconductor layer in the region where the storage capacitor is formed, the resistivity can be reduced, which is a preferable state. Note that the subsequent steps may be performed in accordance with the first embodiment.

[Embodiment 13] In this embodiment, the validity of the configuration of the present invention was verified using computer simulation. Here, ISE (Integrated system
engineering AG) A semiconductor device simulator comprehensive package was used.

The structure of the TFT used for the calculation is shown in FIG.
Shown in The structure of the TFT was such that the channel length was 10 μm, the channel width was 10 μm, and the length of the low concentration impurity region (LDD) was fixed at 2.5 μm. Also, as other conditions,
The phosphorus concentration of the low concentration impurity region (n ⁻ ) is set to 4.2 × 10 ¹⁷
/ Cm ³ , the phosphorus concentration of the source region and the drain region (n ⁺ ) is 2 × 10 ²⁰ / cm ³ , the thickness of the semiconductor layer is 50 nm,
The thickness of the gate insulating film was 150 nm, and the thickness of the gate electrode was 400 nm. In the calculation, the GOLD structure in which the low-concentration impurity region (n ⁻ ) completely overlaps the gate electrode and the GOLD structure in which the low-concentration impurity region (n ⁻ ) is shifted outward at 0.5 μm pitch and partially overlaps (GOLD + L
DD).

FIG. 21 shows the result of calculating the electric field intensity distribution on the drain side with reference to the center of the channel formation region. Here, the calculation was performed with the gate voltage Vg = -8 V and the drain voltage Vds = 16 V. As a result, in the case of the GOLD structure in which the low-concentration impurity region (n ⁻ ) completely overlaps with the gate electrode, the electric field intensity at the gate-drain end becomes the strongest, and the low-concentration impurity region (n ⁻ ) region is connected to the drain side. , The electric field strength was reduced when the amount of overlap was reduced.

FIG. 22 shows that the drain voltage Vds = 16
The figure shows the result of calculating Vg-Id (gate voltage-drain current) characteristics with V constant. In the case of the GOLD structure, there is an increase in off-state current. However, it is shown that an increase in off-state current can be prevented by shifting the low-concentration impurity region (n ⁻ ) region to the drain side and reducing the amount of overlap.

FIG. 23 and FIG. 24 show the case where the low-concentration impurity region (n ⁻ ) completely overlaps the gate electrode.
For the case of the OLD structure and the structure (GOLD + LDD) which is shifted to the outside by 0.5 μm and partially overlapped, the calculation results of the electron concentration distribution and the hole concentration distribution of the channel forming region, the source region, and the drain region are shown. Is shown. In the figure, the concentration distribution is shown by contour lines.
In FIG. 23, it can be seen that the hole concentration is high in a region where the surface of the low concentration impurity region (n ⁻ ) overlaps the gate electrode. At this time, an increase in off-current caused by the high hole concentration is reduced. This can be seen as the hole current in FIG. On the other hand, in FIG. 24, since the electric field intensity at the gate electrode and the drain end is reduced by the GOLD + LDD structure, the hole concentration is not high. Further, the distribution of the electron concentration becomes gentle, and the tunnel current is blocked due to the existence of the LDD region, so that the off current does not increase. Similarly, in FIG. 26, both the electron current and the hole current are reduced.

The results of the above computer simulation are as follows:
The phenomenon of the GOLD structure, which is the subject of the present invention, is well described. This shows that the configuration of the present invention can prevent an increase in off-state current.

[Embodiment 14] In this embodiment, the T
Semiconductor device incorporating active matrix type liquid crystal display device using FT circuit FIGS. 15, 40, 41
Will be described.

Such semiconductor devices include portable information terminals (electronic notebooks, mobile computers, mobile phones, etc.), video cameras, still cameras, personal computers,
TV and the like. Examples of these are shown in FIGS.
0, shown in FIG.

FIG. 15A shows a portable telephone, and a main body 90.
01, audio output unit 9002, audio input unit 9003, display device 9004, operation switch 9005, antenna 900
6. The present invention is an audio output unit 900
2. The present invention can be applied to a display device 9004 including an audio input unit 9003 and an active matrix substrate.

FIG. 15B shows a video camera, which includes a main body 9101, a display device 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 91.
06. The present invention provides a voice input unit 9103,
910 provided with active matrix substrate
2. It can be applied to the image receiving unit 9106.

FIG. 15C shows a mobile computer, which includes a main body 9201, a camera section 9202, and an image receiving section 920.
3, an operation switch 9204, and a display device 9205. The present invention can be applied to the display device 9205 including the image receiving portion 9203 and the active matrix substrate.

FIG. 15D shows a head-mounted display, which is composed of a main body 9301, a display device 9302, and an arm portion 9303. The present invention can be applied to the display device 9302. Although not shown, it can be used for other signal control circuits.

FIG. 15E shows a portable book, and a main body 95.
01, display devices 9502 and 9503, storage medium 950
4, comprising an operation switch 9505 and an antenna 9506 for displaying data stored on a mini disk (MD) or a DVD or data received by the antenna. The display devices 9502 and 9503 are direct-view display devices, and the present invention can be applied to this.

FIG. 40A shows a personal computer, which includes a main body 9601, an image input section 9602, and a display device 9.
603 and a keyboard 9604.

FIG. 40B shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 9701, a display device 9702, and a speaker unit 97.
03, a recording medium 9704, and operation switches 9705. This device uses a DVD (Di) as a recording medium.
It is possible to watch music, watch a movie, play a game, or use the Internet by using a CD (g. Versatile Disc) or a CD.

FIG. 40C shows a digital camera, which comprises a main body 9801, a display device 9802, an eyepiece 9803, operation switches 9804, and an image receiving unit (not shown).

FIG. 27A shows a front type projector, which comprises a display device 2601 and a screen 2602. The present invention can be applied to a display device and other signal control circuits.

FIG. 27B shows a rear type projector, which includes a main body 2701, a display device 2702, and a mirror 270.
3. It is composed of a screen 2704. The present invention can be applied to a display device and other signal control circuits.

FIG. 27C is a diagram showing an example of the structure of the display devices 2601 and 2702 in FIGS. 27A and 27B. Display devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
10. An optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 27D is a diagram showing an example of the structure of the light source optical system 2810 in FIG. 27C. In this embodiment, the light source optical system 2810 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 27D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system. Further, the invention of the present application can also be applied to an image sensor and an EL display device. As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields.

[Embodiment 15] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured by using the present invention will be described.

FIG. 33A is a top view of an EL display device using the present invention. In FIG. 33A, 4010
Denotes a substrate, 4011 denotes a pixel portion, 4012 denotes a source side driver circuit, and 4013 denotes a gate side driver circuit. Each of the driver circuits is connected to an FPC 4017 through wirings 4014 to 4016.
And connected to the external device.

At this time, the cover member 600 is formed so as to surround at least the pixel portion, preferably the drive circuit and the pixel portion.
0, sealing material (also referred to as housing material) 7000,
A sealing material (a second sealing material) 7001 is provided.

FIG. 33B shows a cross-sectional structure of the EL display device of this embodiment.
A driving circuit TFT 4022 (here, a CMOS circuit combining an n-channel TFT and a p-channel TFT is illustrated) 4022 and a pixel portion TFT 40
23 (however, here, TF for controlling the current to the EL element)
Only T is shown. ) Is formed. These T
The FT may use a known structure (top gate structure or bottom gate structure).

The present invention relates to a TFT 4022 for a driving circuit,
It can be used for the pixel portion TF4023.

By using the present invention, the TFT 402 for the driving circuit
2. When the pixel portion TFT 4023 is completed, the pixel portion TFT is formed on an interlayer insulating film (flattening film) 4026 made of a resin material.
A pixel electrode 4027 made of a transparent conductive film electrically connected to the drain of the FT 4023 is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used. After the pixel electrode 4027 is formed, an insulating film 4028 is formed, and an opening is formed over the pixel electrode 4027.

Next, an EL layer 4029 is formed. The EL layer 4029 is formed of a known EL material (a hole injection layer, a hole transport layer,
A light-emitting layer, an electron transport layer, or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. Also, E
The L material includes a low molecular material and a high molecular (polymer) material. When a low molecular material is used, an evaporation method is used, but when a high molecular material is used, a spin coating method,
A simple method such as a printing method or an inkjet method can be used.

In this embodiment, an EL layer is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask, color display becomes possible. In addition, the color conversion layer (CC
M) and a color filter are combined, and a white light-emitting layer and a color filter are combined. Either method may be used. Needless to say, a monochromatic EL display device can be used.

After forming the EL layer 4029, the cathode 4030 is formed thereon. Cathode 4030 and EL layer 4029
It is desirable to remove as much as possible moisture and oxygen existing at the interface. Therefore, the EL layer 4029 and the cathode 40 in vacuum
It is necessary to devise a method of continuously forming the film 30 or forming the EL layer 4029 in an inert atmosphere and forming the cathode 4030 without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, as the cathode 4030,
A laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1-nm-thick LiF (lithium fluoride) film is formed over the EL layer 4029 by a vapor deposition method, and a 300-nm-thick aluminum film is formed thereover. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 4030 is connected to the wiring 4016 in a region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and the FPC 401 via the conductive paste material 4032.
7 is connected.

In the region indicated by 4031, the cathode 40
In order to electrically connect the wiring 30 and the wiring 3016, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These are at the time of etching the interlayer insulating film 4026 (at the time of forming the contact hole for the pixel electrode).
Or when the insulating film 4028 is etched (when an opening is formed before the EL layer is formed). Also, the insulating film 40
When etching 28, etching may be performed all at once up to the interlayer insulating film 4026. In this case, the interlayer insulating film 40
If the same resin material is used for the insulating film 26 and the insulating film 4028, the shape of the contact hole can be made good.

The passivation film 6003 and the filler 600 cover the surface of the EL element thus formed.
4. The cover material 6000 is formed.

Furthermore, a sealing material is provided inside the cover member 7000 and the substrate 4010 so as to surround the EL element portion, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.

At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000.
As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0210] The filler 6004 may contain a spacer. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

In the case where a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

[0212] As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

[0213] However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have translucency.

The wiring 4016 is made of a sealing material 700.
0 and through the gap between the sealing material 7001 and the substrate 4010, and is electrically connected to the FPC 4017. Although the wiring 4016 has been described here, the other wiring 401
4, 4015 are similarly electrically connected to the FPC 4017 under the sealant 7000 and the sealant 7001.

[Embodiment 16] In this embodiment, an example in which an EL display device having a form different from that of Embodiment 15 is manufactured by using the present invention will be described with reference to FIGS. 33 (A) and 33 (B) denote the same parts, and a description thereof will not be repeated.

FIG. 34A is a top view of the EL display device of this embodiment, and FIG. 34B is a cross-sectional view taken along line AA ′ of FIG.

According to the fifteenth embodiment, up to the passivation film 6003 is formed to cover the surface of the EL element.

[0218] Further, the filling material 6 is formed so as to cover the EL element.
004 is provided. This filler 6004 is used for the cover material 60.
It also functions as an adhesive for bonding 00. As the filler 6004, PVC (polyvinyl chloride),
Epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0219] The filler 6004 may contain a spacer. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

In the case where a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

Further, as the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have translucency.

Next, the cover material 6
After bonding 000, the side surface of filler 6004 (exposed surface)
Frame material 6001 is attached so as to cover. The frame material 6001 is a sealing material (functions as an adhesive)
Glued by 6002. At this time, a photocurable resin is preferably used as the sealing material 6002, but a thermosetting resin may be used as long as the heat resistance of the EL layer is allowed. Note that the sealing material 6002 is preferably a material that does not transmit moisture or oxygen as much as possible. Further, a desiccant may be added to the inside of the sealing material 6002.

The wiring 4016 is made of the sealing material 600.
2 is electrically connected to the FPC 4017 through a gap between the substrate 2 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 6002 in the same manner.

[Embodiment 17] The present invention can be applied to an EL display panel having the structure as in Embodiments 15 and 16. FIG. 35 shows a detailed sectional structure of the pixel portion.
36A shows a top view structure, and FIG. 36B shows a circuit diagram.
Shown in In FIG. 35, FIG. 36 (A) and FIG. 36 (B), a common reference numeral is used, so that they may be referred to each other.

In FIG. 35, a switching TFT 3502 provided on a substrate 3501 is formed using the n-channel TFT of the present invention (see Examples 1 to 12). In this embodiment, a double gate structure is used. However, since there is no significant difference in the structure and the manufacturing process, the description is omitted. However, the double gate structure has a structure in which two TFTs are substantially connected in series, and has an advantage that an off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure, a triple gate structure, or a multi-gate structure having more gates may be used. Further, it may be formed using the p-channel TFT of the present invention.

The current controlling TFT 3503 is formed using the n-channel TFT of the present invention. At this time, the drain wiring 35 of the switching TFT 3502
Is the gate electrode 37 of the current controlling TFT by the wiring 36.
Is electrically connected to The wiring indicated by 38 is the gate electrode 39 of the switching TFT 3502.
This is a gate wiring for electrically connecting a and 39b.

At this time, it is very important that the current control TFT 3503 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or hot carriers. Therefore, the structure of the present invention in which the LDD region is provided on the drain side of the current controlling TFT so as to overlap the gate electrode via the gate insulating film is extremely effective.

In this embodiment, the current controlling TFT 35 is used.
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

Further, as shown in FIG. 36A, the wiring to be the gate electrode 37 of the current controlling TFT 3503 is 35
In a region indicated by 04, the region overlaps with the drain wiring 40 of the current control TFT 3503 via an insulating film. At this time, 3
In the region indicated by 504, a capacitor is formed. This capacitor 3504 functions as a capacitor for holding a voltage applied to the gate of the current control TFT 3503. The drain wiring 40 is connected to a current supply line (power supply line) 3506, and a constant voltage is constantly applied.

The first passivation film 4 is formed on the switching TFT 3502 and the current control TFT 3503.
And a planarizing film 42 made of a resin insulating film thereon.
Is formed. It is very important to flatten the step due to the TFT using the flattening film 42. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

Reference numeral 43 denotes a pixel electrode (cathode of an EL element) made of a conductive film having high reflectivity.
503 is electrically connected to the drain. Pixel electrode 43
It is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof. Of course, a stacked structure with another conductive film may be employed.

A light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, R (red), G (green),
Light emitting layers corresponding to each color of B (blue) may be separately formed.
As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. Typical polymer-based materials include polyparaphenylenevinylene (PPV), polyvinylcarbazole (PVK), and polyfluorene.

Although there are various types of PPV-based organic EL materials, for example, “H. Shenk, H. Becker, O. Ge
lsen, E. Kluge, W. Kreuder, and H. Spreitzer, “Polymers
forLight Emitting Diodes ”, Euro Display, Proceeding
s, 1999, p.33-37 "and JP-A-10-92576.

As a specific light emitting layer, cyanopolyphenylenevinylene is used for a red light emitting layer, polyphenylenevinylene is used for a green light emitting layer, and polyphenylenevinylene or polyalkylphenylene is used for a blue light emitting layer. Good. The film thickness is 30-150n
m (preferably 40 to 100 nm).

However, the above example is an example of an organic EL material that can be used as a light emitting layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

For example, in this embodiment, an example in which a polymer material is used as the light emitting layer is shown, but a low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, PEDOT is formed on the light emitting layer 45.
This is an EL layer having a laminated structure provided with a hole injection layer 46 made of (polythiophene) or PAni (polyaniline). An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of this embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

When the anode 47 is formed, the EL element 3
505 is completed. Note that the EL element 3505 mentioned here
Are the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 4
6 and the anode 47. FIG.
As shown in A, since the pixel electrode 43 substantially matches the area of the pixel, the entire pixel functions as an EL element. Therefore,
The utilization efficiency of light emission is very high, and a bright image can be displayed.

In the present embodiment, a second passivation film 48 is further provided on the anode 47. Second
As the passivation film 48, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 35, and a switching TFT having a sufficiently low off-current value and a current control device which is strong against hot carrier injection. And a TFT. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.

The structure of this embodiment is similar to that of the first to twelfth embodiments.
It can be implemented in any combination with the configuration.
Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic device of the fourteenth embodiment.

[Embodiment 18] In this embodiment, a structure in which the EL element 3505 is inverted in the pixel portion shown in Embodiment 17 will be described. FIG. 37 is used for the description. Note that the only difference from the structure of FIG. 35 is the EL element portion and the current controlling TFT, and therefore, the other description will be omitted.

In FIG. 37, the current controlling TFT 350
Reference numeral 3 is formed using the p-channel TFT of the present invention. Embodiments 1 to 12 may be referred to for the manufacturing process.

In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

Then, the banks 51a and 51b made of an insulating film are used.
Is formed, a light emitting layer 52 made of polyvinyl carbazole is formed by solution coating. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode 54 made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 3701 is formed.

In the case of this embodiment, the light generated in the light emitting layer 52 is radiated toward the substrate on which the TFT is formed, as indicated by the arrow.

The structure of this embodiment is similar to that of the first to twelfth embodiments.
Can be freely combined with the above configuration. Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic device of the fourteenth embodiment.

[Embodiment 19] In this embodiment, FIG.
38A to 38C show an example in which a pixel having a structure different from that of the circuit diagram shown in FIG. In this embodiment, reference numeral 3801 denotes a source wiring of the switching TFT 3802, 3803 denotes a gate wiring of the switching TFT 3802, 3804 denotes a current control TFT, 3805 denotes a capacitor, 3806 and 3808 denote a current supply line, 380
Reference numeral 7 denotes an EL element.

FIG. 38A shows an example in which a current supply line 3806 is shared between two pixels. That is, the feature is that two pixels are formed to be line-symmetric with respect to the current supply line 3806. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 38B shows the current supply line 380
8 is provided in parallel with the gate wiring 3803. Note that in FIG. 38B, the current supply line 3808 and the gate wiring 3803 are provided so as not to overlap with each other.
They can be provided so as to overlap with each other via an insulating film. In this case, since the power supply line 3808 and the gate wiring 3803 can share an occupied area, the pixel portion can have higher definition.

In FIG. 38C, a current supply line 3808 is provided in parallel with the gate wiring 3803, and two pixels are connected to the current supply line 3808 in the same manner as in the structure of FIG.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 3808 so as to overlap with one of the gate wirings 3803. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

The structure of this embodiment is similar to those of Embodiments 1 to 1.
It can be implemented in any combination with the configuration of 2, 15 or 16. In addition, it is effective to use an EL display panel having the pixel structure of this embodiment as a display unit of the electronic device of Embodiment 14.

[Embodiment 20] FIG. 36 shown in Embodiment 17
36A and 36B, a capacitor 3504 for holding the voltage applied to the gate of the current controlling TFT 3503 is used.
, But the capacitor 3504 can be omitted. In the case of the seventeenth embodiment, since the n-channel TFT of the present invention as shown in the first to twelfth embodiments is used as the current controlling TFT 3503, the LD provided to overlap the gate electrode via the gate insulating film is provided.
It has a D region. A parasitic capacitance generally called a gate capacitance is formed in the overlapped region. The present embodiment is characterized in that this parasitic capacitance is actively used instead of the capacitor 3504.

Since the capacitance of the parasitic capacitance changes depending on the area where the gate electrode and the LDD region overlap, it is determined by the length of the LDD region included in the overlapping region.

Further, FIG. 38 (A) shown in Embodiment 19,
Similarly, in the structures (B) and (C), the capacitor 3
It is possible to omit 805.

The structure of this embodiment is similar to that of the first to first embodiments.
2, 15 to 19 can be freely combined. In addition, it is effective to use an EL display panel having the pixel structure of this embodiment as a display unit of the electronic device of Embodiment 14.

[Embodiment 21] Various liquid crystals other than nematic liquid crystals can be used in the liquid crystal display device shown in Embodiment 1 or 4. For example, 1998, SID, "
Characteristicsand Driving Scheme of Polymer-Stabi
lized Monostable FLCD Exhibiting FastResponse Time
and High Contrast Ratio with Gray-Scale Capabilit
y "by H. Furue et al., 1997, SID DIGEST, 841," A
Full-Color Thresholdless Antiferroelectric LCD Exh
ibiting Wide Viewing Angle with Fast Response Tim
e "by T. Yoshida et al., 1996, J. Mater. Chem. 6
(4), 671-673, "Thresholdless antiferroelectricity
in liquid crystals and its application to display
s "by S. Inui et al. and U.S. Pat. No. 5,594,569.

A ferroelectric liquid crystal (FLC) exhibiting an isotropic phase-cholesteric phase-chiral smectic C phase transition series
FIG. 39 shows the electro-optical characteristics of a monostable FLC in which the cholesteric phase-chiral smectic C phase transition was performed while applying a DC voltage and the cone edge was almost aligned with the rubbing direction. The display mode using the ferroelectric liquid crystal as shown in FIG. 39 is called “Half-V switching mode”. The vertical axis of the graph shown in FIG. 39 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. "Hal
For the fV-shaped switching mode, see Terada et al.
Half-V switching mode FLCD ", 46th
Proceedings of the JSCE Lecture Meeting, March 1999
Tsuki, p. 1316, and Yoshihara et al., "Time-Division Full-Color LCD with Ferroelectric Liquid Crystal", Liquid Crystal Vol. 3, No. 19, No. 19
See page 0 for details.

As shown in FIG. 39, it is understood that the use of such a ferroelectric mixed liquid crystal enables low-voltage driving and gradation display. The liquid crystal display device of the present invention includes:
A ferroelectric liquid crystal having such electro-optical characteristics can also be used.

A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). As a mixed liquid crystal having an antiferroelectric liquid crystal, there is a so-called thresholdless antiferroelectric mixed liquid crystal exhibiting an electro-optical response characteristic in which transmittance changes continuously with an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optical response characteristic, and its driving voltage is about ± 2.5 V.
Some (cell thicknesses of about 1 μm to 2 μm) have been found.

In general, a thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and a high dielectric constant of the liquid crystal itself. Therefore, when a thresholdless antiferroelectric mixed liquid crystal is used for a liquid crystal display device, a relatively large storage capacitance is required for a pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.

By using such a thresholdless antiferroelectric mixed liquid crystal in the liquid crystal display device of the present invention, low-voltage driving can be realized, so that low power consumption can be realized.

[0264]

According to the present invention, a stable operation can be obtained even when the pixel TFT of the pixel matrix circuit is driven by applying a gate voltage of 15 to 20 V. As a result, a semiconductor device including a CMOS circuit made of a crystalline TFT, and more specifically, a liquid crystal display
The reliability of a pixel matrix circuit such as an L display device and a driver circuit provided therearound can be improved, and a liquid crystal display device or an EL display device that can withstand long-term use can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view of a TFT according to an embodiment.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 7 is a perspective view of an active matrix substrate.

FIG. 8 is a top view of a pixel matrix circuit and a CMOS circuit.

FIG. 9 is a view showing a manufacturing process of a crystalline silicon film.

FIG. 10 is a diagram showing a manufacturing process of a crystalline silicon film.

FIG. 11 is a view showing a manufacturing process of a crystalline silicon film.

FIG. 12 is a view showing a manufacturing process of a crystalline silicon film.

FIG. 13 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG 14 illustrates a structure of a gate electrode.

FIG. 15 illustrates an example of an electronic device.

FIG. 16 illustrates a structure of a gate electrode.

FIG. 17 illustrates a structure and electric characteristics of a TFT.

FIG. 18 illustrates a structure of a gate electrode.

FIG. 19 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 20 is a diagram showing a basic structure of a simulation.

FIG. 21 is a diagram showing a simulation result of an electric field intensity distribution in a channel length direction.

FIG. 22 is a diagram showing a simulation result of gate voltage-drain current characteristics.

FIG. 23 is a diagram showing a simulation result of electron / hole concentration distribution.

FIG. 24 is a diagram showing a simulation result of an electron-hole concentration distribution.

FIG. 25 is a diagram showing a simulation result of an electron / hole current density distribution.

FIG. 26 is a diagram showing a simulation result of an electron / hole current density distribution.

FIG. 27 illustrates a configuration of a projector.

FIG. 28 is a sectional view of a TFT according to the embodiment.

FIG. 29 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 30 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 31 illustrates a structure of a gate electrode.

FIG. 32 illustrates a configuration of a laser annealing apparatus.

FIG. 33 illustrates a structure of an active matrix EL display device.

FIG. 34 illustrates a structure of an active matrix EL display device.

FIG. 35 is a cross-sectional view illustrating a structure of a pixel portion of an active matrix EL display device.

36A and 36B are a top view and a circuit diagram illustrating a structure of a pixel portion of an active matrix EL display device.

FIG. 37 is a cross-sectional view illustrating a structure of a pixel portion of an active matrix EL display device.

FIG. 38 is a circuit diagram illustrating a structure of a pixel portion of an active matrix EL display device.

FIG. 39 is a view showing an example of light transmittance characteristics of an antiferroelectric mixed liquid crystal.

FIG. 40 illustrates an example of an electronic device.

Claims (29)

[Claims] 1. An n-channel TFT and a p-channel TFT
In the semiconductor device including the CMOS circuit formed by the above, the gate electrodes of the n-channel TFT and the p-channel TFT are a first conductive layer formed in contact with a gate insulating film, and the first conductive layer. And a second insulating film formed in contact with the gate insulating film.
A semiconductor layer of the n-channel TFT, a channel formation region, a first impurity region formed in contact with the channel formation region, and a semiconductor layer formed in contact with the first impurity region. The semiconductor layer of the p-channel TFT has a channel formation region and a third impurity region formed in contact with the channel formation region; The first impurity region of the TFT is provided so as to entirely overlap with the second conductive layer, and the third impurity region of the p-channel TFT partially overlaps with the second conductive layer. A semiconductor device characterized by being provided. 2. A pixel TFT of a pixel matrix circuit, and a C TFT formed by an n-channel TFT and a p-channel TFT.
In a semiconductor device including a MOS circuit, the pixel TFT and an n-channel type T of the CMOS circuit are provided.
The gate electrodes of the FT and the p-channel TFT are a first conductive layer formed in contact with the gate insulating film and a second conductive layer formed in contact with the first conductive layer and the gate insulating film.
The pixel TFT and the semiconductor layer of the n-channel TFT have a channel formation region, a first impurity region formed in contact with the channel formation region, and a first impurity region. A semiconductor layer of the p-channel TFT has a channel formation region and a third impurity region formed in contact with the channel formation region; The pixel TFT and the first impurity region of the n-channel TFT are provided so as to entirely overlap the second conductive layer, and the third impurity region of the p-channel TFT is the second impurity region. A semiconductor device characterized in that a part thereof is provided so as to overlap with the conductive layer. 3. An n-channel TFT and a p-channel TFT
Wherein the gate electrodes of the n-channel TFT and the p-channel TFT are a first conductive layer formed in contact with a gate insulating film; A second layer formed in contact with the layer and the gate insulating film.
A semiconductor layer of the n-channel TFT, a channel formation region, a first impurity region formed in contact with the channel formation region, and a semiconductor layer formed in contact with the first impurity region. The semiconductor layer of the p-channel TFT has a channel formation region and a third impurity region formed in contact with the channel formation region; A part of the first impurity region of the TFT is provided so as to partially overlap the second conductive layer, and the third impurity region of the p-channel TFT is formed so as to be in contact with the second conductive layer. A semiconductor device which is provided so as to partially overlap. 4. A pixel TFT of a pixel matrix circuit, and a C formed by an n-channel TFT and a p-channel TFT.
In a semiconductor device including a MOS circuit, the pixel TFT and an n-channel type T of the CMOS circuit are provided.
The gate electrodes of the FT and the p-channel TFT are a first conductive layer formed in contact with the gate insulating film and a second conductive layer formed in contact with the first conductive layer and the gate insulating film.
The pixel TFT and the semiconductor layer of the n-channel TFT have a channel formation region, a first impurity region formed in contact with the channel formation region, and a first impurity region. A semiconductor layer of the p-channel TFT has a channel formation region and a third impurity region formed in contact with the channel formation region; Part of the first impurity region of the pixel TFT and part of the first impurity region of the n-channel TFT are provided so as to partially overlap with the second conductive layer, and part of the third impurity region of the p-channel TFT is provided. The semiconductor device, wherein the portion is provided so as to overlap a part of the second conductive layer. 5. One pixel includes two n-channel TFTs.
Wherein the gate electrodes of the two n-channel TFTs are formed in contact with a first conductive layer formed in contact with a gate insulating film, and formed in contact with the first conductive layer and the gate insulating film. A semiconductor layer of the two n-channel TFTs, wherein the semiconductor layers of the two n-channel TFTs include a channel forming region, a first impurity region formed in contact with the channel forming region, A second impurity region formed in contact with the second impurity region, and a part of the first impurity region of the two n-channel TFTs partially overlaps with the second conductive layer. A semiconductor device, which is provided. 6. The semiconductor device according to claim 5, wherein at least one n-channel TFT has a multi-gate structure. 7. The semiconductor device according to claim 5, wherein an element having a light emitting layer is connected to the other n-channel TFT. 8. A semiconductor device having an n-channel TFT and a p-channel TFT in one pixel, wherein the gate electrodes of the n-channel TFT and the p-channel TFT are formed in contact with a gate insulating film. A first conductive layer, and a second conductive layer formed in contact with the first conductive layer and the gate insulating film. The semiconductor layer of the n-channel TFT has a channel formation region. A first impurity region formed in contact with the channel formation region; and a second impurity region formed in contact with the first impurity region, and a part of the first impurity region. Is provided so as to partially overlap with the second conductive layer. The semiconductor layer of the p-channel TFT has a channel formation region and a third impurity region formed in contact with the channel formation region. A part of the third impurity region is Wherein a is provided to overlap with a portion of the second conductive layer. 9. The semiconductor device according to claim 8, wherein the n-channel thin film transistor has a multi-gate structure. 10. The method of claim 8, wherein the p-channel type T
A semiconductor device, wherein an element having a light-emitting layer is connected to the FT. 11. The method according to claim 1, wherein:
The impurity element imparting n-type conductivity in the first impurity region;
Element concentration is 1 × 10 ¹⁶~ 5 × 10¹⁹atoms / cm^ThreeIs
A semiconductor device characterized by the above-mentioned. 12. The semiconductor layer according to claim 1, wherein the semiconductor layer is provided in contact with the second impurity region and contains an impurity element at the same concentration as the first impurity region. A semiconductor device, wherein a storage capacitor is formed from an insulating layer formed of the same layer as a gate insulating film and a capacitor wiring formed over the insulating layer. 13. The semiconductor layer according to claim 1, wherein the semiconductor layer is provided in contact with the second impurity region and contains an impurity element at the same concentration as the third impurity region. A semiconductor device, wherein a storage capacitor is formed from an insulating layer formed of the same layer as a gate insulating film and a capacitor wiring formed over the insulating layer. 14. The method according to claim 1, wherein the first conductive layer of the n-channel TFT and the p-channel TFT is formed of titanium (Ti), tantalum (T
a) a semiconductor device formed of one or more elements selected from tungsten (W), molybdenum (Mo), or a material containing the elements as components; 15. The semiconductor device according to claim 1, wherein the first conductive layer of the n-channel TFT and the p-channel TFT is formed of one or more layers. Semiconductor device. 16. The n-channel TFT and the p-channel TFT according to claim 1, wherein the first conductive layers of the n-channel TFT and the p-channel TFT are formed in contact with the gate insulating film. A conductive layer (A) formed from one or more elements selected from Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo), or a material containing the elements as main components; The aluminum (A) is formed on the layer (A).
1) A semiconductor device comprising at least one or more elements selected from copper (Cu) or a conductive layer (B) formed of a material containing the elements. 17. The semiconductor device according to claim 1, wherein the second conductive layer is made of titanium (Ti), tantalum (T
a) a semiconductor device formed from one or more elements selected from tungsten (W) and molybdenum (Mo), or a material containing the elements as components. 18. The semiconductor device according to claim 1, wherein the semiconductor device is a display device using an organic electroluminescent material. 19. The semiconductor device according to claim 1, wherein the semiconductor device is a mobile phone, a personal computer, a video camera, a portable information terminal, a digital camera,
A semiconductor device, which is one selected from a player using a recording medium on which a program is recorded, a goggle type display, an electronic book, and a projector. 20. A first step of forming a first semiconductor layer and a second semiconductor layer on a substrate having an insulating surface, and a gate in contact with the first semiconductor layer and the second semiconductor layer. A second step of forming an insulating film; a third step of forming a first conductive layer on the first semiconductor layer and the second semiconductor layer in contact with the gate insulating film; A fourth step of forming a first impurity region by adding an element belonging to Group 15 of the periodic table to a region of the semiconductor layer that does not overlap with the first conductive layer; A fifth step of forming a third impurity region by adding an element belonging to Group 13 of the periodic table to only a region that does not overlap with the first conductive layer, and contacting the first conductive layer and the gate insulating film. A sixth step of forming a second conductive layer, and if the first semiconductor layer overlaps with the second conductive layer. To have regions, a method for manufacturing a semiconductor device, characterized in that it comprises a seventh step of forming a second impurity region by adding an element belonging to periodic table group 15. 21. A first step of forming a first semiconductor layer and a second semiconductor layer on a substrate having an insulating surface, and a gate in contact with the first semiconductor layer and the second semiconductor layer. A second step of forming an insulating film; a third step of forming a first conductive layer on the first semiconductor layer and the second semiconductor layer in contact with the gate insulating film; A fourth step of forming a first impurity region by adding an element belonging to Group 15 of the periodic table to a region of the semiconductor layer that does not overlap with the first conductive layer; A fifth step of forming a third impurity region by adding an element belonging to Group 13 of the periodic table to only a region that does not overlap with the first conductive layer, and contacting the first conductive layer and the gate insulating film. A sixth step of forming a second conductive layer, and if the first semiconductor layer overlaps with the second conductive layer. A seventh region for forming a second impurity region by adding an element belonging to Group 15 of the periodic table to a region that is not formed, and an eighth step for removing a part of the second conductive layer. A method for manufacturing a semiconductor device, comprising: 22. The semiconductor device according to claim 20, wherein the second conductive layer is in contact with the first conductive layer and the first conductive layer on a semiconductor layer extending from the second impurity region. Forming a capacitor wiring from the step of: adding a group 15 element belonging to the periodic table of the same concentration as the first impurity region to the semiconductor layer extending from the second impurity region; Forming a semiconductor device. 23. The semiconductor device according to claim 20, wherein the second conductive layer is in contact with the first conductive layer and the first conductive layer on a semiconductor layer extending from the second impurity region. Forming a capacitor wiring from the step of: adding a group 13 element belonging to the periodic table in the same concentration as the first impurity region to the semiconductor layer extending from the second impurity region; Forming a semiconductor device. 24. The semiconductor device according to claim 20, wherein the first conductive layer is made of titanium (Ti), tantalum (T
a), one or more elements selected from tungsten (W), molybdenum (Mo), or a material containing the elements as a component. 25. The method according to claim 20, wherein the first conductive layer is formed in contact with the gate insulating film, and comprises titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo). A) forming a conductive layer (A) using one or a plurality of elements selected from the group consisting of aluminum or aluminum (Al) and copper (C) on the conductive layer (A);
forming a conductive layer (B) made of one or more elements selected from u) or a material containing the elements as components. 26. The semiconductor device according to claim 20, wherein the second conductive layer is made of titanium (Ti), tantalum (T
a) a method of manufacturing a semiconductor device, which is formed using one or more elements selected from tungsten (W) and molybdenum (Mo), or an alloy material containing the elements. 27. The semiconductor device according to claim 20, wherein the first impurity region has a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁹ atoms /
A method for manufacturing a semiconductor device, comprising adding an element belonging to Group 15 of the periodic table in cm ³ . 28. The method for manufacturing a semiconductor device according to claim 20, wherein the semiconductor device is a display device using an organic electroluminescent material. 29. The semiconductor device according to claim 20, wherein the semiconductor device is a mobile phone, a personal computer, a video camera, a portable information terminal, a digital camera,
A method for manufacturing a semiconductor device, which is one selected from a player using a recording medium on which a program is recorded, a goggle-type display, an electronic book, and a projector.