JP2000215684A - Semiconductor storage device - Google Patents

Abstract

(57) Abstract: A state of a memory cell is determined for every data line in a nonvolatile memory device, and control such as continuation and stop of writing is automatically performed. SOLUTION: A first data line D1, a second data line D2 arranged parallel to and opposed to the first data line, and a plurality of words crossing both the first and second data lines are provided. Lines W1 and W2, a plurality of memory cells provided at desired intersections of the first and second data lines and a plurality of word lines, and first and second data lines are input to the input. A first sense amplifier SAC and a second sense amplifier SAC connected to each other, and a first sense amplifier SAC connected to an output of the first sense amplifier.
, And a second common data line CD connected to the output of the second sense amplifier, and the plurality of memory cells are connected between the first sense amplifier and the second sense amplifier. And between the first common data line and the second common data line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having an electrical rewriting function, and more particularly, to a semiconductor memory device capable of automatically judging and controlling the continuation and stop of a repetitive writing operation performed at the time of rewriting. The present invention relates to a semiconductor memory device capable of speeding up operation and reading operation and miniaturizing the device.

[0002]

2. Description of the Related Art Conventionally, nonvolatile semiconductor memory elements (memory cells) are arranged in an array, and the electric power of a memory cell group (hereinafter referred to as a sector) connected to a control gate common line of the memory cell group, that is, the same word line. In a nonvolatile semiconductor memory device that performs a dynamic rewrite (electrical erasure, electrical write), a semiconductor nonvolatile memory device having a collective simultaneous electrical rewrite function for a drain common line of the memory cell group, that is, for the same data line is as follows. , Symposium on VLS
I Circuits Digest of Technical Papers pp20-21 1992
Has proposed a NAND-EEPROM rewriting circuit configuration. FIG. 22, FIG. 23, and FIG. 24 illustrate the above conventional example.

A conventional NAND-EEPRO shown in FIG.
The rewriting circuit configuration of M is connected in an open bit line configuration centering on one read / write circuit, and a verify circuit is connected to each bit line. In other words, two sets of verify circuits and read / write circuits are connected in an open bit line configuration for each bit line. FIGS. 22 and 23 show, for example, that the bit line BLb
i is a dummy bit line. The read / write circuit operates as a sense amplifier having flip-flop characteristics during a read operation, and operates as a data latch circuit during a write operation. The operation of incorporating data information into the semiconductor nonvolatile memory device refers to an operation of incorporating a plurality of byte data in a continuous manner (page operation) and latching the data information in a read / write circuit. The memory cell is, for each cell to be written simultaneously,
They are connected to the same control gate line (CG), that is, a word line.

In the writing in the NAND-EEPROM system, a threshold value of a memory cell is selectively lowered from a state (negative threshold value) due to an erasing operation to some memory cells (positive threshold value). Value). At the time of writing, Vpp18V is applied to a selected word line, and Vm10V is applied to a non-selected word line. For the data line voltage, the power supply voltage Vrw of the read / write circuit is changed to Vcc (3 V).
, To Vmb8V, but in "1" programming (writing state), 0V is applied to the drain of the memory cell with the input data voltage Vss. At this time, a large potential difference occurs between the control gate and the channel of the memory cell, electrons are injected by the Fowler-Nordheim tunnel phenomenon, and the threshold value of the memory cell increases. on the other hand,
In “0” programming (maintaining the erased state), the voltage of the input data is boosted from Vcc to Vmb 8 V and applied to the drain of the memory cell. In this case, since no high potential is generated between the control gate and the channel of the memory cell,
The threshold value of the memory cell maintains a low value in the erased state.

After the completion of the writing, the state read (write verify) of the memory cell is performed. FIG. 23 shows a signal timing waveform diagram during the write verify operation.
Now, if the cell on the memory cell array (a) side is selected, the potential of the bit line BLai becomes Va voltage = φpa.
It is precharged to (3/5) Vcc, that is, 1.8 V. On the other hand, the potential of the dummy bit line of bit line BLbi is Vb = (1/2) Vcc, that is, 1.5 due to φpb.
It is precharged to V (t1 to t2).

After the bit line is precharged, the potential of the selected word line (CG) is reduced to the write verify voltage 0.6 V, and Vcc is supplied to the unselected word lines (CG). If the threshold value of the selected memory cell is 0.6V
In the following cases, a current flows through the selected memory cell, and the voltage of the bit line becomes 1.5 V or less. On the other hand, when the threshold value of the memory cell is larger than 0.6 V, no current flows, and the voltage of the bit line is maintained at the precharge voltage of 1.8 V (t2 to t3).

Thereafter, when all word lines (CG) enter a non-selected state of 0 V, verify circuit signal φav enters an activated state (Vcc). If the latch data of the read / write circuit is "1" (voltage value 0 V), the MOS transistor T1 is turned off, and the voltage of the bit line BLai is maintained at the level before φav enters the active state. . On the other hand, when the latch data is “0” (voltage value Vcc),
The MOS transistor T1 turns on, and the bit line BLa
The voltage of i becomes 1.5 V or more (t3 to t4).

When the verify circuit signal φav is low (Vs
s), the read / write circuit is in the equalized state (φ
p: high, φn: low, φe: high), and then
The verification circuit signals φa and φb are activated to operate as a sense amplifier (t4 to).

The voltage of the bit line BLai is read by the open bit line method, and the read (write verify) data after the writing is reprogrammed to the latch data of the read / write circuit. FIG. 24 shows the relationship among the program data, the reprogram data, and the data of the memory cells. Now, when a certain memory cell is programmed to “1” (latch data voltage 0 V) and the threshold voltage of the memory cell reaches a value higher than 0.6 V in the write verify operation, excessive writing of the memory cell is prevented. For example, the latch data voltage is programmed to Vcc, ie, “0”.

[0010]

In the above-mentioned prior art, the above-described electrical rewriting operation algorithm controls the repetitive write operation and write verify operation for each bit of the rewrite sector. However, since it is not determined whether or not all the bits for which writing is selected have completed writing, it is not possible to determine whether or not to stop the write operation and the write verify operation that are repeatedly performed. For this reason, the stop is conventionally controlled using a timer or the like. In such a control method in which the write operation and the write verify operation are stopped by a timer or the like without performing the write end detection / judgment operation, in general, the set time of the timer at the time of writing is sufficient in consideration of the rewriting endurance. It is necessary to set a proper time. On the other hand, if a sufficient time is set for the timer, the write disturb resistance is a problem because a high voltage such as a drain voltage of the memory cell is 8 V or a control gate (word) voltage of the memory cell is 18 V is used. Becomes

When the CPU in a system (for example, a portable system such as a still camera, a small recorder, a pocket computer, etc.) outside the semiconductor nonvolatile storage device executes the write end detection / determination operation, The operation must be performed without disconnecting the bus between the semiconductor nonvolatile memory device and the system, which is complicated.
There is a problem that U is occupied by the rewrite control of the semiconductor nonvolatile memory device. A first object of the present invention is to solve the above problems and propose a semiconductor memory device in which electrical rewriting of sector information can be easily performed while a bus between a semiconductor memory device and a used system is disconnected. That is.

Further, the above-mentioned conventional NAND-EEPR
As shown in FIG. 19A, the definition of the memory cell threshold and the write drain voltage in the OM write operation is as described in “(1) Write memory cell threshold is selectively removed from a low state after erasing a part of the memory. (2) Apply 0 V to the drain line selected for writing, and apply a positive voltage to the drain line not selected. " In this definition, the verifying method, which is the above-mentioned conventional technique, can be used. However, as shown in FIG. 19B, "(1) the threshold value of some memory cells is selectively lowered from the high state after erasing, and (2) the drain line selected for writing. In the definition of the write operation, "a positive voltage is applied and 0 V is applied to the non-selection drain voltage", it is impossible to control the continuation and stop of the write by the above-mentioned conventional verify method.

The reason will be specifically described below with reference to FIG. Now, it is assumed that the memory cells connected to the data lines b1 and b2 are to be written, and that the threshold value of the memory cells connected to the data lines b3 and b4 is low at the time of write verification after writing. I do. In other words, since the data line b2 has a high threshold value after the write verify, the write operation is further continuously repeated.
Further, the data line b4 drops to a desired threshold value by the writing, and stops the next writing operation.

In the verify method, all data lines are precharged regardless of the latch data of the sense amplifier circuit,
After the word line is selected, a current flows through the data lines b3 and b4 connected to the memory cells having a low threshold value, and the data line potential becomes 0V. The potential of the data line is set to 3 V by the data rewriting performed thereafter and the data lines b2 and b4 and the data line b1 maintaining the precharge potential are set to 3 V by the initial write data of the sense amplifier circuit. Therefore, although there is no problem with the data line b2 for which the data is to be continued as it is with respect to the initial write data and the data line b3 for which it is desired to maintain a low threshold state, the data line b4 for which rewriting is to be stopped and the initial write data 0V are Data line b you want to hold
In No. 1, rewriting by the verify method cannot be used because rewriting data is different.

Therefore, a second object of the present invention is to define a write operation of a semiconductor memory element (memory cell) by selectively selecting a write threshold from a high state after erasing a threshold of some memory cells. In the semiconductor memory device in which the drain line voltage of the non-selection write is set to 0 V, the continuation or stop of the repetition of the write is determined for each data line, and all the data lines to be written are connected. An object of the present invention is to propose a write stop control when writing to a selected memory cell is completed.

[0016]

According to the present invention, in order to achieve the above object, in a semiconductor memory device, a memory cell state detection circuit is provided for each data line, and a memory cell associated with a write operation and a write verify operation is provided. Is characterized by detecting the write state of the write operation and controlling the continuation and stop of the write operation repeatedly performed at the time of rewriting based on the result. Further, a precharge control circuit and a sense amplifier circuit are provided for each data line.

According to the present invention, as described above, by providing a memory cell state detection circuit for each data line in the memory cell array, control from the CPU in the system in which the memory cell state detection circuit is used is slightly reduced when rewriting is started. Only time is required, and subsequent rewriting (including control such as continuation and stop of the writing operation) is automatically performed only inside the semiconductor memory device, so that the load on the CPU is significantly reduced. Further, when the precharge method is used, only the data line to be written is to be precharged, and the data in the final data latch always becomes 0V. Therefore, it is advantageous in terms of current consumption as compared with the conventional verify method.

[0018]

FIG. 1 is a circuit block diagram showing a semiconductor integrated circuit having a semiconductor nonvolatile memory device which is a flash memory (an electrically erasable nonvolatile memory) according to an embodiment of the present invention. It is. In the embodiment shown in FIG. 1, a memory cell state detection circuit A is provided for each data line.
It is characterized in that LLC is provided. The memory cell state detection circuit ALLC determines, for each data line, whether to continue or stop the repetitive write operation during the rewrite process, and selects the selected memory connected to all the data lines to be written. The writing operation is stopped when the writing to the cell is completed. On the other hand, the repeated erase operation is continued until all the memory cells connected to the data lines reach the erase threshold, and all the memory cells reach the erase threshold by the memory cell state detection circuit ALLC. When the determination is made, the erase operation is stopped.

The embodiment shown in FIG. 1 will be described in more detail. In the figure, a transistor M1 of a nonvolatile memory cell,
M2, M4, and M5 are known flash memory cells (nonvolatile memory cells that can be electrically erased collectively). The control gate (control gate) electrodes of the memory cells M1 and M4 are connected to the word line W1, and the memory cells M2 and M4
The control gate (control gate) electrode of M5 is connected to the word line W2. Further, the word lines W1, W2 are connected to a row decoder XDCR. The drain electrodes of the memory cells M1 and M2 are connected to the data line D1, and the drain electrodes of the memory cells M4 and M5 are connected to the data line D2. A precharge control circuit PCC that controls precharge for each of the data lines D1 and D2,
It is connected to a sense amplifier circuit SAC that serves both as a sense function and a data latch function of write data, in other words, a write drain voltage setting function, and to a memory cell state detection circuit ALLC that simultaneously determines the state of a memory cell on a data line. It is connected to gates Q4 and Q5.
The data lines D1 and D2 are connected to the data line discharge MOSFETs Q1 and Q2, respectively. The source electrodes of the memory cells M1 to M5 are connected to the common source line S and are grounded (ground potential Vss).

The electrical rewriting operation inside the semiconductor memory device according to the present invention is as follows. After determining the memory cell state detection operation by the memory cell state detection circuit ALLC, the sense amplifier circuit SA connected to each data line
When the information of the data latch of C indicates that at least one write is designated, the write operation is repeated again.
In addition, in the determination of the memory cell state detection operation, when all the information of the data latch of the sense amplifier circuit SAC is in the write non-selection state, after the detection determination operation is completed, the repeatedly performed write operation is terminated.

[0021] The first object of the present invention is achieved by the above configuration. That is, the continuation or stop of the repetitive write operation during the rewrite operation is determined by the memory cell state detection circuit ALLC provided for each data line, and the selected memory cell connected to all the data lines to be written is determined. When the writing is completed, the writing is stopped.

The memory cell state detection circuit ALLC has at least one MOS write state detection circuit for each data line.
It suffices if it is constituted by an FET and the output from the sense amplifier circuit SAC is connected to the gate input of the MOSFET. Therefore, if the data latch of the sense amplifier circuit SAC specifies writing to at least one data line after the state detection operation determination, the write operation is repeated again, and all the sense amplifier circuits are determined by the state detection operation determination. If the data latch is in the write non-selected state, the write operation repeatedly performed after the detection determination operation is terminated.

The MOSFET constituting the memory cell state detection circuit ALLC may be the same nonvolatile semiconductor memory cell as the memory cell. In this case, the threshold value of the nonvolatile semiconductor memory cell corresponding to the data line connected to the defective memory cell is made programmable, and the data latch information of the sense amplifier circuit SAC connected to the data line is determined from the determination target. Can be removed.

As shown in FIG. 19B, the write operation of the memory cell is defined as "(1) selectively lower the write threshold from a high state after erasing, and (2) non-selected drain. When "0 V is applied to the line", to simultaneously control writing continuation and stop for each data line, use the latch data of the sense amplifier circuit SAC and selectively precharge only the data line to be written. May be used.

FIG. 21 shows the relationship. Now, data line b
It is assumed that the memory cells connected to 2 and b4 are to be written, and the threshold value of the memory cells connected to data lines b3 and b4 is low at the time of write verification after writing. In other words, since the data line b2 has a high threshold value after write verification, the write operation is continuously repeated, and the data line b4 is lowered to a desired threshold value by the write operation, and the subsequent write operation is stopped. In the precharge method, only the data lines b2 and b4 for which writing is specified by the information of the latch data of the sense amplifier circuit are data lines to be precharged. After the write verify voltage is supplied to the word line, the voltages of the data lines b1, b3, and b4 become 0 V, and the data line b
Only 2 is at 3V. By making the potential information of the data line the rewriting of the latch data, the writing operation is stopped (b1, b3, b4) and the writing operation is continued (b2).
Control.

The precharge control circuit PCC in FIG.
MOS with at least precharge signal as gate input
It is composed of an FET, a MOSFET having a terminal signal inside the sense amplifier circuit SAC as a gate input, and the like.

FIG. 2 is a circuit diagram of a semiconductor nonvolatile memory device according to one embodiment of the present invention. Although each circuit element in the figure is not particularly limited, a known CMOS (complementary M
OS) It may be formed on a semiconductor substrate such as one single crystal silicon by a manufacturing technique of an integrated circuit. Although not particularly limited, the present integrated circuit may be formed on a semiconductor substrate made of single crystal p-type silicon. The n-channel MOSFET is made of polysilicon or the like formed on the semiconductor substrate between the source region and the drain region, and between the source region and the drain region via a thin gate insulating film on the semiconductor substrate. It is constituted by a gate electrode. The p-channel MOSFET is formed in an n-type well region formed on the surface of the semiconductor substrate. Thereby, the semiconductor substrate forms a common substrate gate of the plurality of n-channel MOSFETs formed thereon, and the ground potential of the circuit is supplied. The common substrate gate of the p-channel MOSFET, that is, the n-type well region is connected to the power supply voltage Vcc. Alternatively, if it is a high voltage circuit, it is connected to an internally generated high voltage or the like. Further, the integrated circuit may be formed on a semiconductor substrate made of single-crystal n-type silicon. In this case n
The channel MOSFET is formed in a p-type well region.

Although not particularly limited, the semiconductor non-volatile memory device of this embodiment has a complementary address formed through address buffer circuits XADB and YADB which receive a row address signal AX and a column address signal AY supplied from external terminals. A signal is supplied to a row address decoder XDCR and a column address decoder YDCR.

FIG. 3 shows an address buffer circuit ADB (XA
DB, YADB). Although not particularly limited, the above row and column address buffer circuits XADB, YAD
B is activated by a selection signal / CE (chip enable signal) inside the device, takes in an address signal Ax from an external terminal, and outputs an internal address signal ax having the same phase as the address signal supplied from the external terminal and an address signal having the opposite phase. / Ax to form a complementary address signal. Note that “/” in this specification indicates a complementary signal. In FIG. 2, a row address decoder XDCR forms a selection signal of a word line Wi of a memory array in accordance with a complementary address signal of a row address buffer circuit XADB. Similarly, a column address decoder YDCR forms a column address buffer circuit YAD
A selection signal for the data line Di of the memory array according to the complementary address signal of B is formed.

Although not particularly limited, the address input signal in the present device may be only a word line address signal. In that case, the data line address signal is generated inside the device, and the data of the memory cell group connected to the selected word line may be continuously handled. The number of bytes of the memory cells connected to the same word line is, for example, 512 bytes or 256 bytes, and the unit is defined as a sector. In this case, a data unit to be continuously processed may be a sector unit. In the address buffer circuit ADB of FIG. 3, the word line address buffer circuit XADB receives at least a signal Ax from the outside and converts the signal into internal signals ALTCH and / ALTCH.
Therefore, a function of latching is required. The data line address buffer circuit YADB needs to receive at least the internally generated signal Axi and output complementary address signals ax and / ax.

The internal generation signal Axi is generated by an internal address automatic generation circuit shown in FIG. The circuit shown in FIG. 4 includes an oscillation circuit and a plurality of binary counters B.
C. In other words, the internal oscillation circuit activation signal / OSC is received, the internal oscillation circuit is oscillated, the oscillation period signal is received by the binary counter BC, and the output of each binary counter BC is output to the data line address signal A.
1i to Axi.

In FIG. 2, although there is no particular limitation, the selection of a memory cell is performed, for example, in writing or reading in units of 8 bits or 16 bits.
Row address decoder XDCR and column address decoder YD
Eight or sixteen memory cells are selected by CR. The number of memory cells in one data block is n in the word line direction (row direction) and m in the data line direction (column direction). In other words, the memory array is provided with 8 or 16 data blocks of nxm memory cell groups.

The memory array shown in FIG. 2 has a memory cell MOS having a stacked gate structure having a control gate (control gate) and a floating gate (floating gate).
FETs M1 to M9, word lines W1 to Wn, data lines D1 to Dm, and a common source line CS. The common source line CS is connected to the ground potential Vss. In the memory array shown in the figure, the control gates of the memory cells arranged in the same row, for example, M1, M4, M7 are connected to the same word line W1, and the memory cells arranged in the same column, for example, M1, M2 , M3 are connected to the same data line D1.

The data lines D1 to Dm in FIG. 2 are connected to a precharge control circuit PC for controlling precharge for each data line.
C, a sense amplifier circuit SAC which also serves as a sense function and a data latch function of write data, in other words, a write drain voltage setting function, and a memory cell state detection circuit ALLC which simultaneously determines the state of the memory cell on the data line, It is connected to column gates Q4, Q5, Q6. Each data line is also connected to data line discharge MOSFETs Q1, Q2, Q3. Column selection switch MOSFETs Q4, Q which receive a selection signal formed by the address decoder YDCR.
5, and connected to the common data line CD via Q6. Further, the common data line CD is connected to an external terminal I / O via a MOSFET Q8 which receives an internally generated write control signal we which is turned on at the time of writing and a write data input buffer DIB which receives a write signal inputted from the external terminal I / O.
Connected to O. The common data line CD is connected to an external terminal I / O via a switch MOSFET Q7 that receives an internally generated read control signal se that is turned on at the time of reading and a read data output buffer DOB.

FIG. 5 shows an embodiment of the internal configuration of the input buffer circuit DIB and the output buffer circuit DOB. The input buffer circuit DIB is a buffer for receiving data from the external terminal I / O by activating the internal signal we and its inverted signal / we. For data transfer to the sense amplifier circuit SAC having a data latch function, the column gates Q4, Q5, and Q6 described above are selected according to the address. The output buffer circuit DOB is a buffer that outputs data to the external terminal I / O at the time of reading by activating the internal signals oe and / oe from the internal signal se described above and an external terminal output enable signal described later. is there. As a circuit configuration, a voltage conversion function is provided after a pass gate having the internal signal se as a gate input. This is to compensate for the threshold drop due to the pass gate.

The timing control circuit CONT in FIG.
Are not particularly limited, but the external terminals / CE, / OE, /
Chip ena supplied to WE, SC, RDY / BSY, etc.
ble signal, output enable signal, write enable signal, seri
al control signal, ready / busy signal, etc., internal control signals ce, se, we, oe, DDC, PG, DG, / R0, / P0, / R1,
/ P1 and a word line supply voltage Vword and a data line supply voltage V for selectively supplying a row address decoder XDCR, a column address decoder YDCR, and the like.
yg, sense amplifier circuit pMOS power supply voltage Vcd, nMOS
An internal power supply voltage such as the power supply voltage Vsd is generated from the power supply voltage Vcc by internal boosting and internal stepping down. Further, the respective power supply voltages may be supplied from outside.

Although there is no particular limitation, a read operation,
The operation modes such as the rewrite operation (erase operation and write operation) include the activation of the external signals / CE and / WE and the data of the external terminal I / O such as the read operation 00H, the erase operation 20H, and the write operation 10H. Each operation mode is set by a command input, and internal signals necessary for each operation are generated by the timing control circuit CONT in FIG. In particular, for the operation of rewriting a sector, a rewrite command, a rewrite sector address, sector information (data), etc. are taken into the device from an external terminal. Also,
Whether the rewrite operation is in progress, the rewrite operation is completed,
Whether or not an erasing operation or a writing operation is being performed can be externally known by information (polling) of a status register or a ready / busy signal. In the continuous read operation of the sector and the reception of the sector data, the output and the input may be performed in synchronization with the signal from the external terminal SC.

The memory cell is not particularly limited, but may be an EPROM (Erasable Programmable Read O / O).
nly Memory).
However, the rewriting operation uses a tunneling phenomenon between the floating gate and the substrate, the drain coupled to the data line, or the source coupled to the source line, or a photoelectron injection that applies a high voltage to the control gate and the drain. This is different from the conventional EPROM rewriting method using ultraviolet light in that it is electrically performed. Hereinafter, as shown in FIG. 19B, an operation for raising the threshold value of the memory cell above the thermal equilibrium state is defined as an erasing operation, and reducing the threshold value to about the thermal equilibrium state is defined as a writing operation. Non-selection not to write (holds threshold after erase operation)
Of the memory cell at the ground potential Vss (= 0
V).

The erasing operation is an operation in which the threshold value of the memory cell group (sector) connected to the common gate of the memory cell group, that is, the word line, is higher than the thermal equilibrium state, and a high voltage is selectively applied to the word line. . In that case, by setting the potential of the substrate to a negative potential, the high voltage applied to the word line can be reduced by the potential of the substrate. At this time, the drain terminal, the source terminal, and the channel potential are set to the ground potential Vss or a memory cell is formed in the p-type well region in order to lower the maximum voltage inside the device, and a negative voltage potential is supplied to the p-type well region. In the erased memory cell, electrons are accumulated in the floating gate, and no memory cell current flows ("0" state) even when a word line and a drain line are selected at the time of reading.

When the write data is taken into the device, the internal signals / ce and we are activated. Input buffer circuit DIB and column address decoder YDC
R operates, and data from the external terminal I / O is continuously written to the sense amplifier circuit SAC as information on a plurality of memory cells (sectors) of a predetermined word line. It is also possible to temporarily store data in the sense amplifier circuit SAC and partially rewrite only necessary memory cell information from outside the device.

During the write operation, the sense amplifier circuit SA
Writing is performed using the data taken into C.
The data of the sense amplifier circuit SAC corresponding to the memory cell to be written holds a positive voltage, and the data of the sense amplifier circuit SAC not to be written is at the ground potential Vss. By selectively setting the word line potential corresponding to the sector to be written to a negative voltage, selectively causing a tunnel phenomenon due to the potential difference between the drain terminals, and extracting electrons accumulated in the floating gate to the drain side. A write operation is performed ("1" state).

At the time of reading, the selected word line potential becomes the power supply voltage Vcc, and the data line potential is supplied with a low voltage of about 1 V from the precharge control circuit PCC so that weak writing does not occur.
At C, the memory cell information is read. In the erased memory cell in the "0" state, electrons are accumulated in its floating gate, the threshold voltage increases, and no drain current flows even when the word line W is selected at the time of reading, so that the memory cell holds 1 V. ing. The threshold voltage of the memory cell in the "1" state where electrons have not been injected is low. When the word line W is selected, a current flows, and the data line potential becomes lower than the precharge potential 1V. Data line potential is sense amplifier SAC
To determine “0” and “1”, and select the column select switch MOS.
The data is output to the external terminal I / O through the common data line CD through the FETs Q4, Q5, and Q6, through the data output circuit DOB.

In a flash memory, the threshold value of a memory cell that causes an erroneous read must be accurately controlled so as not to become a negative voltage. For this reason, writing in the writing operation is divided into several times, reading is performed every time writing is performed, and it is checked whether the threshold value of the memory cell has reached the writing threshold value (writing bay fi). If so, the writing is repeated again. A voltage lower than the voltage used at the time of normal reading is applied to the word line at the time of the write verify. As a result, the distribution of the threshold values in the memory cell group (sector) controls the upper limit of the distribution. The word line potential at the time of this write verification is set to a voltage such that the threshold values of all the memory cells in the memory cell group do not become negative.

Also, in the case of checking the threshold value of the memory cell after erasing, reading is performed after erasing to check whether the threshold value has reached the erasing level (erase verify).
By applying a voltage higher than the normal read voltage as the word line voltage at the time of erase verification, it is possible to determine whether or not the threshold value of the memory cell has reached the erase threshold value, thereby confirming insufficient erasure. The voltage applied to the word line during write verify and erase verify is equal to the power supply voltage Vc.
The power may be supplied from a built-in power supply that is created by dropping or boosting the voltage from inside the device from c, or may be supplied from an external power supply.

The read operation and the rewrite operation deal with data of a memory cell group (sector) connected to the selected word line. However, the present invention is not limited to this. It may be a unit.

FIG. 6 shows a configuration diagram of the first embodiment of the rewriting circuit. Each data line D1, D2 is the same (equivalent)
Connection configuration. Regarding the data line D1 (D2), memory cells M1, M2 (M4, M5),
A precharge control circuit PCC for controlling precharge between the column selection switch MOSFETs Q4 (Q5), a sense amplifier circuit SAC having both a sense function and a data latch function of write data, in other words, a write drain voltage setting function, and a memory cell. A state detection circuit ALLC for judging the state at the same time as the data lines is connected.

M constituting precharge control circuit PCC
The OSFET group includes a series connection of a MOSFETa having at least an output of the sense amplifier circuit SAC as a gate input and a MOSFETb having a gate input of a precharge signal PG;
And data line D provided in parallel with MOSFETb
1 (D2) and a data line gate signal DG for connecting the sense amplifier circuit SAC to the gate of the MOSF
ETc. The data line can be selectively precharged by the precharge signal PG and data of the sense amplifier circuit SAC. The voltage value of the precharge signal PG supplies a voltage lower than the power supply voltage at least at the time of each verification and at the time of reading. This is to prevent weak writing and weak erasing by setting the voltage of the data line to about 1V. Weak writing occurs when a memory cell connected to an unselected word line emits floating gate electrons injected by a drain voltage. In addition, weak erasure occurs when memory cells connected to the selected word line inject electrons into the floating gate by photoelectrons.

The sense amplifier circuit SAC is composed of a MOSFET d having a gate input of an internal signal / SET for setting the sense amplifier circuit SAC and a plurality of MOSFETs forming a latch circuit. Sense amplifier circuit SA
C operates as a sense amplifier having flip-flop characteristics at the time of reading, and operates as a latch circuit for holding write data at the time of rewriting. The power supply voltage Vcd of the sense amplifier circuit SAC during the rewrite operation may be equal to the drain voltage of the memory cell during the write operation. In the write operation during the rewrite operation and the read (write-verify) operation, the power supply is turned off. The operation may be fixed at the write drain voltage without switching.

The memory cell state detection circuit ALLC uses a p-channel MOSFET ei (i = 1, 2) for detecting the erase state for each data line Di (i = 1, 2, ie, D1, D2).
And n-channel MOSFET fi for detecting write state
(I = 1, 2) each composed of one MOSFET,
An output from the sense amplifier circuit SAC is detected by a state detection MOSF.
It has a configuration connected to the gate of the ET. Those p
Channel MOSFETei, n-channel MOSFET
The drains and sources of MOSFETs of Tfi are shared (A0a, A0b, A1a, A1b).
In other words, the memory cell state detection circuit ALLC has a multi-input NAND gate configuration in the erase state detection circuit and a multi-input NOR gate configuration in the write state detection circuit as a precharge dynamic circuit. Further, since the erase state detection circuit has a multi-input NAND gate structure,
It is possible to detect a simultaneous erase state of a memory cell group (a plurality of sectors) connected to one or more word lines. Note that the state detection method is not limited to the precharge method, but may be a current sense method or a voltage sense method.

M constituting precharge control circuit PCC
On the opposite side of the OSFETc memory cell group, a column selection switch MOSFET Q4 (Q5) for receiving a data selection signal
Is connected to the common data line CD. The data line D1 (D2) on the memory cell group side is provided with a data line discharge MOSFET Q1 (Q2) for discharging a drain voltage at the time of writing or reading.

FIG. 7 shows an internal signal timing waveform of the device in the rewriting operation by the precharge method. As described above, in the rewrite operation, the write, write verify, and write state detection operations are repeated. By t1, write data is written in advance to the sense amplifier circuit SA.
Take in C. The data of the sense amplifier circuit connected to the data line for selecting writing may be the Vcd power supply voltage or the external power supply voltage Vcc. The data not selected for writing is the ground potential Vss. t1 to t2
In the meantime, the precharge signal PG is activated, and selectively precharges only the data line to be written by the data of the sense amplifier circuit SAC. Since the data to be written ("1") is the Vcd power supply voltage, FIG.
The MOSFET a in the middle precharge control circuit PCC is turned on and can supply a potential to the data line Di. On the other hand, when maintaining the erased state (“0”), the MOSF
ETa is turned off, and does not supply a potential to the data line Di.

In the period from t2 to t3 in FIG.
DG of the gate input of MOSFETc in the precharge control circuit PCC connecting the i and the sense amplifier circuit SAC
The signal is activated, and data information (“1” is a Vcd voltage,
"0" is the Vss voltage). The reason why the precharge is performed in advance between t1 and t2 is that when the gate signal DG of the MOSFET c is activated without precharge, the parasitic capacitance of the data line Di and the sense amplifier circuit SAC
This is because charge sharing occurs between the parasitic capacitances of the sense amplifier circuits SAC and the Vcd voltage which is the write selection data information of the sense amplifier circuit SAC may become the Vss voltage. FIG.
When the sector of the selected memory cell group (M1, M4) is the word line W1, the selected word line W1 is set to a negative voltage, and a potential difference is generated between the drain voltages as the write data voltage Vcd, and the data is selectively written by a tunnel phenomenon. Is performed. As the potential of the unselected word line W2, a positive power supply voltage is applied to control the disturbance of the drain voltage (data voltage Vcd).

From t3 to t4, DDC which is the gate signal of the data line discharge MOSFET is set to high, and the data line discharge MOSFET Q in FIG.
1. Activate Q2 to discharge the data line voltage. Thereafter, a write verify operation is started.

From t4 to t5, the precharge signal P
G is activated, and only the data line selected for writing is applied to the sense amplifier circuit SAC as in the operation between t1 and t2.
And precharge is performed by the operation of MOSFETa in precharge control circuit PCC. From t5 to t6
Between them, a voltage (for example, about 1.5 V) lower than the power supply voltage used during normal reading is applied to the selected word line W1. Discharge is selectively performed based on the parasitic capacitance of the data line Di according to the threshold value of the memory cell. When the threshold value of the memory cell to be written reaches a desired low threshold value, a current flows through the memory cell. When the threshold value of the memory cell has not reached the write threshold value, the precharged potential is applied to the parasitic capacitance of the data line Di. Keep. Data line precharge signal P
By setting the timing (t5) for deactivating G before the activation of the word line selection signal, the current of the memory cell is prevented from constantly flowing.

From t6 to t7, the DG signal at the gate input of the MOSFET c in the precharge control circuit PCC connecting the data line Di and the sense amplifier circuit SAC is activated, and the potential of the data line Di is changed to the sense amplifier circuit SAC.
Is determined. The determination is made based on the parasitic capacitance of the data line Di, the parasitic capacitance in the sense amplifier circuit SAC, and the result of charge sharing between the voltage of the data line Di and the data potential (Vcd) of the sense amplifier circuit. When the potential of the data line Di is higher than the logical threshold value of the sense amplifier circuit SAC, the selection potential (Vcd) of the write data is kept as it is, and when the potential is lower than the logical threshold value, the sense amplifier circuit SAC Is the ground potential Vs
s, and the write data is automatically rewritten.
The MOSFET c in the precharge control circuit PCC
Becomes inactive as soon as the determination of the sense amplifier is completed. In other words, the data line D
The process ends without charging the potential of i to the power supply voltage Vcd of the sense amplifier circuit SAC.

During the period from t7 to t8, it is determined whether or not all the memory cells to be written have completed writing. In FIG. 10, the write state detection circuit ALLC includes one n-channel MOSFET fi for each data line Dia, and the MOSFET f
i is connected to the output Dia of the sense amplifier circuit SAC, and the source and the drain are shared (A1
a, A1b), a multi-input NOR gate configuration of a precharge dynamic circuit. The common source line A1a and drain line A1b are connected to the signal / R
1, / P1 and the MOSFETs h and j are reset to the ground potential Vss in advance, and the reset is stopped at the timing of t7.

When the internal signal / P1 goes low, the signal MO shown in FIG.
The activation of the SFETg causes the common source line A1a to rise to the power supply voltage Vcc, and the ON / OFF of the n-channel MOSFET fi is controlled by the data of the sense amplifier circuit SAC. All data lines can be performed simultaneously. When the data of at least one sense amplifier circuit SAC is data (Vcd) for continuing writing, the potential of the common source line A1a becomes the ground potential Vss. On the other hand, in the case where all the data is data for which writing has been completed (ground potential Vcc), the potential of the common source line A1a maintains the power supply voltage Vcc which is a precharged voltage value. Based on this information, the continuation and stop of the repetitive write operation are controlled inside the device. In other words, after t8, when the potential of the common source line A1a is the ground potential Vss, the operation returns to t1, and the operation is repeated. When the potential of the common source line A1a is the power supply voltage Vcc,
The rewrite operation of the write operation and the write verify operation is completed.

FIG. 8 shows an internal signal timing waveform in a normal read operation. In this case, since the memory cell group (sector) to be read is connected to all the data lines, the sense amplifier circuit SA in FIG.
C data is activated to activate the internal signal / SET, and the power supply voltage V
Set to cd. The period from t2 to t5 is the same as the above-described write verify operation (t4 to t7 in FIG. 7) except that only the selected word line Wi potential is different, and the power supply voltage is Vcc during normal reading. Further, the power supply voltage Vcd of the sense amplifier circuit SAC may be the external power supply voltage Vcc.

FIG. 9 shows the internal signal timing waveforms of the device in the erase operation and the erase verify operation. t1 to t2
In between, a positive high voltage is applied to the selected word line W1 in FIG. 6, and the data line Di is connected to the discharge MOSFE.
The memory cell is activated by the common gate signal DDC of TQ1 and Q2 and becomes the ground potential Vss, a potential difference occurs between the channel of the memory cell and the floating gate, and an erase operation is performed in which electrons are injected into the floating gate. From t2 to t6, the erase verify operation is performed in the same manner as the normal read operation described above. As the potential of the selected word line W1 at the time of erase verification, a voltage (for example, 5 V) higher than the power supply voltage Vcc at the time of normal reading is applied.

Between t5 and t6, data line D in FIG.
DG of the gate input of MOSFETc in the precharge control circuit PCC connecting the i and the sense amplifier circuit SAC
The signal is activated, and the potential of the data line Di is determined by the sense amplifier circuit SAC. The determination is made based on the parasitic capacitance of the data line Di, the parasitic capacitance in the sense amplifier circuit SAC, the potential of the data line Di, and the data voltage (Vcd) of the sense amplifier circuit.
It depends on the result of charge sharing between When the potential of the data line Di is higher than the logical threshold value of the sense amplifier circuit SAC, the selection potential (Vcd) of the erase data is kept as it is, and when it is lower than the logical threshold value, the sense amplifier circuit SAC Becomes the ground potential Vss, and the erase data is automatically rewritten. The MOSF in the precharge control circuit PCC
The activity of the DG signal at the gate input of ETc becomes inactive as soon as the determination of the sense amplifier is completed. In other words, the potential of the data line Di is set to the power supply voltage V of the sense amplifier circuit SAC.
It ends without charging up to cd.

Between t6 and t7, a state detection determination of the memory cells is performed to determine whether all thresholds of the memory cell group (sector) to be erased have reached the erase threshold. In FIG. 6, the erase state detection circuit is constituted by one p-channel MOSFET ei for each data line Dia, and its M
The output Dia of the sense amplifier circuit SAC and the source and drain are shared by the gate of the OSFET ei (A
0a, A0b), a multi-input NAND gate configuration of a precharge dynamic circuit. The common source line A0a and drain line A0b are reset to the substrate voltage Vss in advance by the signals / P0, / RO and the MOSFETs m, n, and the reset is stopped at the timing of t6.

When the internal signal / P0 goes low, the MOSFET
The activation of k causes the common drain line A0b to be at the power supply voltage V
cc, and on / off of the p-channel MOSFET ei is controlled by the data of the sense amplifier circuit SAC, so that the erasure determination of the memory cell group (sector) can be performed simultaneously on all data lines. Data (Vcd) in which data of at least one sense amplifier circuit SAC continues to be erased
In this case, the potential of the common source line A0a maintains the power supply voltage Vcc which is a precharged voltage value. on the other hand,
In the case where all the data is erased data (ground potential Vss), the potential of the common source line A0a is changed to the substrate potential Vs
s. Based on this information, the continuation and stop of the erase operation that is repeatedly performed are controlled inside the device. In other words, after t8, the potential of the common source line A0a becomes equal to the power supply voltage Vc.
In the case of c, the return operation is repeated at t1, and when the ground potential of the common source line A0a is Vss, the erase operation and the erase verify operation are completed. However, the power supply voltage Vcd of the sense amplifier circuit SAC is equal to or higher than the power supply voltage Vcc.

FIG. 10 shows a configuration diagram of an embodiment of the second rewriting circuit. As in the first rewrite circuit configuration diagram, each data line Di is provided with a precharge control circuit PCC, a sense amplifier circuit SAC, and a state detection circuit ALLC. The difference from the first rewrite circuit configuration diagram will be described. First, in the precharge control circuit PCC, the precharge voltage to the data line is controlled by the voltage value of the precharge signal PG. This control is performed with the source voltage VPG of the MOSFETa connected in series.
Second, the sense amplifier circuit SAC sets the set signal to SET.
And is connected to Dib on the opposite side of the data line Dia in the latch circuit constituting the sense amplifier circuit SAC.
Third, the power supply lines Vcd and Vsd in the sense amplifier circuit SAC are shared by a plurality of sense amplifier circuits SAC (for example, mats), and supply of a power supply voltage or the power supply line can be in an open node state. .

The memory cell array is divided into two or more blocks, and activation timings of various internal control signals such as a precharge signal PG, a data line gate signal DG, and a latch set signal / SET used in each block are determined. By shifting each block, the peak value of the current consumption can be reduced.

FIG. 11 shows a NAND-EEPR according to the present invention.
FIG. 4 shows an OM rewrite circuit configuration diagram. NAND-EEPRO
In the M device, the memory cell state detection circuit ALLC is composed of one MOSFET each having both terminal wirings of the read / write circuit as gate inputs. The drains and sources of these MOSFETs are shared by the data lines, and have a multi-input NOR gate configuration as a precharge dynamic circuit. For simultaneous determination of the low threshold value (erased state) of all data lines of the memory cell group on the array a side, A
The a and Ab sides may be used in the precharge method in the same manner as the timing described above, and the Ba and Bb sides are used in a high threshold value (writing state). FIG. 12 shows a second memory array circuit diagram of the present invention. At least two or more memory cells are connected by a diffusion layer D1 nm or the like,
A drain selection M having a word signal Wn as a gate input between the common drain diffusion layer wiring D1 nm and the data line Dm.
FIG. 4 is a circuit diagram to which OSFET nm is connected.

When the word lines have a hierarchical structure, the memory array structure shown in FIGS. 13 and 14 is also possible. FIG. 13 shows a third memory array circuit diagram of the present invention. At least two or more memory cells are connected to the diffusion layers D1 nm and S1
nm, and the common drain diffusion layer wiring D
1 nm and the data line Dm, a drain selection MOSFET SDnm having a gate input of the word signal Wnd, and a word signal Ws between the common source diffusion layer wiring S1nm and the diffusion layer wiring CS1n connected to the common source line CS.
Source selection MOSFET SSnm with n as gate input
FIG. In FIG. 13, W11, W1
2, W1, W2, W21, W22,..., Wn, Wn1, Wn2 are word lines having a hierarchical structure, and access is controlled in two stages. Generally, when word lines are represented by Wn and Wnd, the subscript n indicates a first signal (main signal) for selecting a word line, and d indicates a second signal (sub signal) for selecting a word line. For example, W2 is a first signal (main signal) for selecting a word line.
Is activated when is "2", and W21 is activated when the first signal (main signal) for selecting the word line is "2" and the second signal (sub-signal) for selecting the word line is "1". Is activated.

In the layout of the device, almost the entire surface of the memory cell array region is covered with word line wiring. In a normal read operation and each verify operation, there are thousands of non-selected word lines, and the potential thereof is the ground potential Vss.
Therefore, a stable capacitance between the data line wiring and the word line wiring can be secured.

FIG. 14 shows an embodiment of a mat structure according to the present invention in which a second plurality of memory cell groups are used as blocks. Instead of the ground potential Vss, a reference voltage Vref is applied to an opposite wiring (Dib in FIG. 10) which is not connected to the precharge control circuit PCC and the state detection circuit ALLC of the latch circuit constituting the sense amplifier circuit SAC. As a result, the read determination ("1", "0") of the sense amplifier circuit SAC is compared with the reference voltage Vref.

FIG. 15 shows an embodiment of the third mat structure of the present invention. It has an open bit line configuration in which a memory mat is divided into two. The second rewrite circuit configuration diagram shown in FIG. 10 corresponds to this mat configuration.

FIG. 16 shows an embodiment of the fourth mat structure of the present invention. The difference from FIG. 14 is that there is a reference dummy data line, which has the same parasitic capacitance as the normal data line Di, and uses the reference dummy data line voltage as the generation of the reference voltage Vref.

FIG. 17 shows an embodiment of the fifth mat structure of the present invention. A precharge control circuit PCC, a sense amplifier circuit SAC, and a state detection circuit ALLC are arranged above and below the memory mat, and operated in units of odd data lines and even data lines. When the odd data lines are operated, the even data lines are used as reference dummy data lines. When the even-numbered data lines are operated, the odd-numbered data lines become reference dummy data lines.

FIG. 18 shows an embodiment of the sixth mat structure of the present invention. The memory cells constituting the memory mat are arranged at the intersections of the odd word lines and the odd word lines, and at the intersections of the even word lines and the even word lines. The sense amplifier circuit SAC and the state detection circuit ALLC are arranged for each pair of adjacent data lines, and each of the adjacent data lines is used as a reference dummy data line.

[0073]

As described above, the present invention automatically and collectively detects the states of the memory cells performing the electrical rewriting operation, ie, the erasing operation and the writing operation, on all the data lines, and based on the information, This has a remarkable effect that controls such as insufficient erasing, continuation and stop of writing can be performed only inside the apparatus.

[Brief description of the drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a circuit diagram of a semiconductor nonvolatile memory device according to an embodiment of the present invention. .

FIG. 3 is a diagram showing an example of an internal address buffer circuit of the present invention.

FIG. 4 is a diagram showing an example of an internal address automatic generation circuit according to the present invention.

FIG. 5 is a diagram showing an example of an input / output buffer circuit of the present invention.

FIG. 6 is a configuration diagram of a first rewriting circuit according to the present invention.

FIG. 7 is a timing chart of write and write-verify operation of the present invention.

FIG. 8 is a read operation timing waveform of the present invention.

FIG. 9 is a timing waveform of an erase and erase verify operation of the present invention.

FIG. 10 is a configuration diagram of a second rewriting circuit according to the present invention.

FIG. 11 is a configuration diagram of a NAND-EEPROM rewriting circuit according to the present invention.

FIG. 12 is a circuit diagram of a second memory array according to the present invention.

FIG. 13 is a third memory array circuit diagram of the present invention.

FIG. 14 is a second mat configuration diagram of the present invention.

FIG. 15 is a diagram showing the configuration of a third mat of the present invention.

FIG. 16 is a diagram showing the configuration of a fourth mat according to the present invention.

FIG. 17 is a fifth mat configuration diagram of the present invention.

FIG. 18 is a configuration diagram of a sixth mat of the present invention.

FIG. 19 is a diagram illustrating a write operation definition and a write method.

FIG. 20 is a diagram for explaining a verify method based on the write definition of the present invention.

FIG. 21 is a diagram for explaining a precharge method based on a write definition according to the present invention.

FIG. 22 is a configuration diagram of a conventional NAND-EEPROM rewriting circuit.

FIG. 23 is a timing chart of a conventional NAND-EEPROM.

FIG. 24 is a diagram illustrating NAND-EEPROM cell data and write data of a conventional example.

[Explanation of symbols]

PCC precharge control circuit SAC sense amplifier circuit ALLC state detection circuit W1 to Wn word line D1 to Dm data line CS common source line CD common data line M1 to M9 memory cell XDCR row address decoder YDCR column address decoder XADB row address buffer YADB column Address buffer DOB Output buffer DIB Input buffer CONT Timing control circuit Q1 to Q8 MOSFET Vss Ground voltage Vcc Power supply voltage Vword Word line supply voltage Vyg Data line supply voltage Vcd Sense amplifier circuit pMOS power supply voltage Vsd Sense amplifier circuit nMOS power supply voltage Vref Reference voltage Ax Row address signal Ay Column address signal / CE, / OE, / WE, SC, RDY / BSY, I /
O External terminal ce, DDC, PG, BG, R0, P0, / R1, / P
1, se, we, oe, AIS, ALTCH, / AIE
ND timing signal

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshio Sasaki 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory of Hitachi, Ltd. (72) Inventor Hitoshi Kume 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Hitachi, Ltd. Within the Central Research Laboratory (72) Inventor Hiroaki Kotani 2326 Imai, Ome-shi, Tokyo Inside Hitachi, Ltd.Device Development Center (72) Inventor Kazunori Furuzawa 5-2-1 Kamisumihonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Business Division

Claims (17)

[Claims] A first data line; a second data line disposed in parallel to the first data line; and a plurality of data lines intersecting both the first and second data lines. A word line; a plurality of memory cells provided at desired intersections of the first and second data lines with the plurality of word lines; and the first data line and the second data line. A first sense amplifier and a second sense amplifier connected to the input; a first common data line connected to the output of the first sense amplifier; and a first common amplifier connected to the output of the second sense amplifier. A second common data line, wherein the plurality of memory cells are arranged between the first sense amplifier and the second sense amplifier, and the first common data line and the second 2 common data lines The semiconductor memory device according to symptoms. 2. The semiconductor memory device according to claim 1, wherein said first sense amplifier and said second sense amplifier have the same circuit configuration. 3. The semiconductor memory device according to claim 1, wherein said plurality of memory cells are nonvolatile memory cells. 4. The semiconductor memory device according to claim 3, wherein: a first precharge circuit connected to said first data line; and a second precharge circuit connected to said second data line. Wherein the plurality of memory cells further include the first precharge circuit and the second precharge circuit. 5. The semiconductor memory device according to claim 3, wherein: a first state detection circuit provided between an output of the first sense amplifier and the first common data line; A semiconductor memory device further comprising a second state detection circuit provided between an output of a sense amplifier and the second common data line. 6. The semiconductor memory device according to claim 3, wherein when reading data from a memory cell to said first data line, said second data line is a reference dummy, and said second data line is a reference dummy. Wherein the first data line is a reference dummy when data is read from the memory cell. 7. A plurality of data line pairs, a plurality of word lines intersecting with the plurality of data line pairs, and a plurality of word lines provided at desired intersections between the plurality of data line pairs and the plurality of word lines. A memory cell; a plurality of first sense amplifiers provided for each data line pair of the plurality of data line pairs; a first common data line connected to outputs of the plurality of first sense amplifiers; A plurality of second sense amplifiers provided for each data line pair of the plurality of data line pairs, and a second common data line connected to outputs of the plurality of second sense amplifiers; Is arranged between the plurality of first sense amplifiers and the plurality of second sense amplifiers, and is arranged between the first common data line and the second common data line. A semiconductor memory device characterized by the following. 8. The semiconductor memory device according to claim 7, wherein said plurality of first sense amplifiers and said plurality of second sense amplifiers have the same circuit configuration. 9. The semiconductor memory device according to claim 8, wherein said plurality of memory cells are nonvolatile memory cells. 10. The semiconductor memory device according to claim 9, wherein: a first precharge circuit connected to one of the data line pairs of the plurality of data line pairs; A second precharge circuit connected to the other data line of each data line pair. 11. The semiconductor memory device according to claim 9, wherein said first sense amplifier is provided between an output of each of said plurality of first sense amplifiers and said first common data line.
A second state sense circuit provided between an output of each second sense amplifier of the plurality of second sense amplifiers and the second common data line.
And a state detecting circuit. 12. The semiconductor memory device according to claim 9, wherein when data from a memory cell is read out to one data line of each of said plurality of data line pairs, each of said plurality of data line pairs is read out. The other data line of the data line pair is a reference dummy, and when reading data from a memory cell to the other data line of each data line pair of the plurality of data line pairs, A semiconductor memory device according to claim 1, wherein said one data line of said data line pair is a reference dummy. 13. A first data line, a second data line arranged parallel to and opposed to the first data line, and a word line intersecting both the first and second data lines. And two memory cells provided at two intersections of the first and second data lines and the word line; and the first data line and the second data line are connected to their inputs. A first sense amplifier, wherein the two memory cells are non-volatile memory cells, and when reading data from the memory cells to the first data line, the second data line is a reference dummy cell. A semiconductor memory device characterized by the following. 14. The semiconductor memory device according to claim 13, wherein said first data line and said second data line are connected to their inputs, and said second sense line has the same circuit configuration as said first sense amplifier. Further comprising an amplifier, wherein the two memory cells are arranged between the first sense amplifier and the second sense amplifier, and when reading data from the memory cell to the second data line, The semiconductor memory device, wherein the first data line is a reference dummy. 15. The semiconductor memory device according to claim 14, wherein: a first precharge circuit connected to said first data line; and a second precharge circuit connected to said second data line. Wherein the two memory cells are arranged between the first sense amplifier and the second sense amplifier. 16. The semiconductor memory device according to claim 13, further comprising a first state detection circuit connected to an output of said first sense amplifier. 17. The semiconductor memory device according to claim 13, wherein a first state detection circuit connected to an output of said first sense amplifier, and a second state detection circuit connected to an output of said second sense amplifier. A semiconductor memory device further comprising a state detection circuit.